* [PATCH v3 3/7] dt-bindings: soc: qcom: Add RSC power domain specifier
[not found] <1580736940-6985-1-git-send-email-mkshah@codeaurora.org>
@ 2020-02-03 13:35 ` Maulik Shah
2020-02-03 13:35 ` [PATCH v3 6/7] arm64: dts: qcom: sc7180: Add cpuidle low power states Maulik Shah
1 sibling, 0 replies; 4+ messages in thread
From: Maulik Shah @ 2020-02-03 13:35 UTC (permalink / raw)
To: swboyd, agross, david.brown, sudeep.holla, Lorenzo.Pieralisi
Cc: linux-arm-msm, linux-kernel, linux-pm, linux-arm-kernel,
bjorn.andersson, evgreen, dianders, rnayak, ilina, lsrao,
ulf.hansson, rjw, Maulik Shah, devicetree
In addition to transmitting resource state requests to the remote
processor, the RSC is responsible for powering off/lowering the
requirements from CPUs subsystem for the associated hardware like
buses, clocks, and regulators when all CPUs and cluster is powered down.
The power domain is configured to a low power state and when all the
CPUs are powered down, the RSC can lower resource state requirements
and power down the rails that power the CPUs.
Add PM domain specifier property for RSC controller.
Cc: devicetree@vger.kernel.org
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt b/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
index 9b86d1e..5682806 100644
--- a/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
+++ b/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
@@ -83,6 +83,14 @@ Properties:
Value type: <string>
Definition: Name for the RSC. The name would be used in trace logs.
+- #power-domain-cells:
+ Usage: optional
+ Value type: <u32>
+ Definition: Must be 0. Number of cells in power domain specifier.
+ Optional for controllers that may be in 'solver' state
+ where they can be in autonomous mode executing low power
+ modes.
+
Drivers that want to use the RSC to communicate with RPMH must specify their
bindings as child nodes of the RSC controllers they wish to communicate with.
@@ -112,6 +120,7 @@ TCS-OFFSET: 0xD00
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
+ #power-domain-cells = <0>;
};
Example 2:
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v3 6/7] arm64: dts: qcom: sc7180: Add cpuidle low power states
[not found] <1580736940-6985-1-git-send-email-mkshah@codeaurora.org>
2020-02-03 13:35 ` [PATCH v3 3/7] dt-bindings: soc: qcom: Add RSC power domain specifier Maulik Shah
@ 2020-02-03 13:35 ` Maulik Shah
2020-02-04 23:15 ` Matthias Kaehlcke
1 sibling, 1 reply; 4+ messages in thread
From: Maulik Shah @ 2020-02-03 13:35 UTC (permalink / raw)
To: swboyd, agross, david.brown, sudeep.holla, Lorenzo.Pieralisi
Cc: linux-arm-msm, linux-kernel, linux-pm, linux-arm-kernel,
bjorn.andersson, evgreen, dianders, rnayak, ilina, lsrao,
ulf.hansson, rjw, Maulik Shah, devicetree
Add device bindings for cpuidle states for cpu devices.
Cc: devicetree@vger.kernel.org
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 78 ++++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 8011c5f..0aa0ced 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -86,6 +86,9 @@
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
@@ -103,6 +106,9 @@
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_100>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
@@ -117,6 +123,9 @@
compatible = "arm,armv8";
reg = <0x0 0x200>;
enable-method = "psci";
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_200>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
@@ -131,6 +140,9 @@
compatible = "arm,armv8";
reg = <0x0 0x300>;
enable-method = "psci";
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_300>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
@@ -145,6 +157,9 @@
compatible = "arm,armv8";
reg = <0x0 0x400>;
enable-method = "psci";
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_400>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
@@ -159,6 +174,9 @@
compatible = "arm,armv8";
reg = <0x0 0x500>;
enable-method = "psci";
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_500>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
@@ -173,6 +191,9 @@
compatible = "arm,armv8";
reg = <0x0 0x600>;
enable-method = "psci";
+ cpu-idle-states = <&BIG_CPU_SLEEP_0
+ &BIG_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_600>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1>;
@@ -187,6 +208,9 @@
compatible = "arm,armv8";
reg = <0x0 0x700>;
enable-method = "psci";
+ cpu-idle-states = <&BIG_CPU_SLEEP_0
+ &BIG_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_700>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1>;
@@ -195,6 +219,60 @@
next-level-cache = <&L3_0>;
};
};
+
+ idle-states {
+ entry-method = "psci";
+
+ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "little-power-down";
+ arm,psci-suspend-param = <0x40000003>;
+ entry-latency-us = <549>;
+ exit-latency-us = <901>;
+ min-residency-us = <1774>;
+ local-timer-stop;
+ };
+
+ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "little-rail-power-down";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <702>;
+ exit-latency-us = <915>;
+ min-residency-us = <4001>;
+ local-timer-stop;
+ };
+
+ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "big-power-down";
+ arm,psci-suspend-param = <0x40000003>;
+ entry-latency-us = <523>;
+ exit-latency-us = <1244>;
+ min-residency-us = <2207>;
+ local-timer-stop;
+ };
+
+ BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "big-rail-power-down";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <526>;
+ exit-latency-us = <1854>;
+ min-residency-us = <5555>;
+ local-timer-stop;
+ };
+
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "cluster-power-down";
+ arm,psci-suspend-param = <0x40003444>;
+ entry-latency-us = <3263>;
+ exit-latency-us = <6562>;
+ min-residency-us = <9926>;
+ local-timer-stop;
+ };
+ };
};
memory@80000000 {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v3 6/7] arm64: dts: qcom: sc7180: Add cpuidle low power states
2020-02-03 13:35 ` [PATCH v3 6/7] arm64: dts: qcom: sc7180: Add cpuidle low power states Maulik Shah
@ 2020-02-04 23:15 ` Matthias Kaehlcke
2020-02-05 12:07 ` Maulik Shah
0 siblings, 1 reply; 4+ messages in thread
From: Matthias Kaehlcke @ 2020-02-04 23:15 UTC (permalink / raw)
To: Maulik Shah
Cc: swboyd, agross, david.brown, sudeep.holla, Lorenzo.Pieralisi,
linux-arm-msm, linux-kernel, linux-pm, linux-arm-kernel,
bjorn.andersson, evgreen, dianders, rnayak, ilina, lsrao,
ulf.hansson, rjw, devicetree
On Mon, Feb 03, 2020 at 07:05:39PM +0530, Maulik Shah wrote:
> Add device bindings for cpuidle states for cpu devices.
>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 78 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 78 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 8011c5f..0aa0ced 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -86,6 +86,9 @@
> compatible = "arm,armv8";
> reg = <0x0 0x0>;
> enable-method = "psci";
> + cpu-idle-states = <&LITTLE_CPU_SLEEP_0
> + &LITTLE_CPU_SLEEP_1
> + &CLUSTER_SLEEP_0>;
These entries are deleted again by the next patch in this series ('arm64:
dts: qcom: sc7180: Convert to the hierarchical CPU topology layout').
What is the point in adding them in the first place?
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v3 6/7] arm64: dts: qcom: sc7180: Add cpuidle low power states
2020-02-04 23:15 ` Matthias Kaehlcke
@ 2020-02-05 12:07 ` Maulik Shah
0 siblings, 0 replies; 4+ messages in thread
From: Maulik Shah @ 2020-02-05 12:07 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: swboyd, agross, david.brown, sudeep.holla, Lorenzo.Pieralisi,
linux-arm-msm, linux-kernel, linux-pm, linux-arm-kernel,
bjorn.andersson, evgreen, dianders, rnayak, ilina, lsrao,
ulf.hansson, rjw, devicetree
On 2/5/2020 4:45 AM, Matthias Kaehlcke wrote:
> On Mon, Feb 03, 2020 at 07:05:39PM +0530, Maulik Shah wrote:
>> Add device bindings for cpuidle states for cpu devices.
>>
>> Cc: devicetree@vger.kernel.org
>> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
>> ---
>> arch/arm64/boot/dts/qcom/sc7180.dtsi | 78 ++++++++++++++++++++++++++++++++++++
>> 1 file changed, 78 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> index 8011c5f..0aa0ced 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> @@ -86,6 +86,9 @@
>> compatible = "arm,armv8";
>> reg = <0x0 0x0>;
>> enable-method = "psci";
>> + cpu-idle-states = <&LITTLE_CPU_SLEEP_0
>> + &LITTLE_CPU_SLEEP_1
>> + &CLUSTER_SLEEP_0>;
> These entries are deleted again by the next patch in this series ('arm64:
> dts: qcom: sc7180: Convert to the hierarchical CPU topology layout').
> What is the point in adding them in the first place?
Clubbed 6th and 7th patch in v4 series.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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2020-02-03 13:35 ` [PATCH v3 3/7] dt-bindings: soc: qcom: Add RSC power domain specifier Maulik Shah
2020-02-03 13:35 ` [PATCH v3 6/7] arm64: dts: qcom: sc7180: Add cpuidle low power states Maulik Shah
2020-02-04 23:15 ` Matthias Kaehlcke
2020-02-05 12:07 ` Maulik Shah
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