* [PATCH 1/3] dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK
@ 2020-06-16 20:24 Dinh Nguyen
2020-06-16 20:24 ` [PATCH 2/3] clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk Dinh Nguyen
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Dinh Nguyen @ 2020-06-16 20:24 UTC (permalink / raw)
To: linux-clk; +Cc: dinguyen, devicetree, mturquette, sboyd, robh+dt
Add the NAND_X_CLK and NAND_ECC_CLK clocks.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
include/dt-bindings/clock/agilex-clock.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/agilex-clock.h b/include/dt-bindings/clock/agilex-clock.h
index f19cf8ccbdd2..06feca07e08e 100644
--- a/include/dt-bindings/clock/agilex-clock.h
+++ b/include/dt-bindings/clock/agilex-clock.h
@@ -65,6 +65,8 @@
#define AGILEX_SDMMC_CLK 50
#define AGILEX_SPI_M_CLK 51
#define AGILEX_USB_CLK 52
-#define AGILEX_NUM_CLKS 53
+#define AGILEX_NAND_X_CLK 53
+#define AGILEX_NAND_ECC_CLK 54
+#define AGILEX_NUM_CLKS 55
#endif /* __AGILEX_CLOCK_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk
2020-06-16 20:24 [PATCH 1/3] dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK Dinh Nguyen
@ 2020-06-16 20:24 ` Dinh Nguyen
2020-06-20 2:37 ` Stephen Boyd
2020-06-16 20:24 ` [PATCH 3/3] clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk Dinh Nguyen
2020-06-20 2:37 ` [PATCH 1/3] dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK Stephen Boyd
2 siblings, 1 reply; 6+ messages in thread
From: Dinh Nguyen @ 2020-06-16 20:24 UTC (permalink / raw)
To: linux-clk; +Cc: dinguyen, devicetree, mturquette, sboyd, robh+dt
And the nand_x_clk and nand_ecc_clk. Make the nand_x_clk be the main
clock that is feeding the NAND IP and correct it's parent to be the
l4_mp_clk.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
drivers/clk/socfpga/clk-agilex.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
index 699527f7e764..1b2e0ad01b24 100644
--- a/drivers/clk/socfpga/clk-agilex.c
+++ b/drivers/clk/socfpga/clk-agilex.c
@@ -294,8 +294,12 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = {
8, 0, 0, 0, 0, 0, 0},
{ AGILEX_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
9, 0, 0, 0, 0, 0, 0},
- { AGILEX_NAND_CLK, "nand_clk", "l4_main_clk", NULL, 1, 0, 0x7C,
+ { AGILEX_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
10, 0, 0, 0, 0, 0, 0},
+ { AGILEX_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
+ 10, 0, 0, 0, 0, 0, 4},
+ { AGILEX_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
+ 10, 0, 0, 0, 0, 0, 4},
};
static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk
2020-06-16 20:24 [PATCH 1/3] dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK Dinh Nguyen
2020-06-16 20:24 ` [PATCH 2/3] clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk Dinh Nguyen
@ 2020-06-16 20:24 ` Dinh Nguyen
2020-06-20 2:37 ` Stephen Boyd
2020-06-20 2:37 ` [PATCH 1/3] dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK Stephen Boyd
2 siblings, 1 reply; 6+ messages in thread
From: Dinh Nguyen @ 2020-06-16 20:24 UTC (permalink / raw)
To: linux-clk; +Cc: dinguyen, devicetree, mturquette, sboyd, robh+dt
Preliminary documentation documented the mpu_l2ram_clk, but since then,
the mpu_l2ram_clk is no longer documented. It's now referred to as
mpu_ccu_clk.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
drivers/clk/socfpga/clk-agilex.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
index 1b2e0ad01b24..8fb12cbe0208 100644
--- a/drivers/clk/socfpga/clk-agilex.c
+++ b/drivers/clk/socfpga/clk-agilex.c
@@ -252,7 +252,7 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = {
0, 0, 0, 0, 0x30, 0, 0},
{ AGILEX_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x24,
0, 0, 0, 0, 0, 0, 4},
- { AGILEX_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x24,
+ { AGILEX_MPU_CCU_CLK, "mpu_ccu_clk", "mpu_clk", NULL, 1, 0, 0x24,
0, 0, 0, 0, 0, 0, 2},
{ AGILEX_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x24,
1, 0x44, 0, 2, 0, 0, 0},
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK
2020-06-16 20:24 [PATCH 1/3] dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK Dinh Nguyen
2020-06-16 20:24 ` [PATCH 2/3] clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk Dinh Nguyen
2020-06-16 20:24 ` [PATCH 3/3] clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk Dinh Nguyen
@ 2020-06-20 2:37 ` Stephen Boyd
2 siblings, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2020-06-20 2:37 UTC (permalink / raw)
To: Dinh Nguyen, linux-clk; +Cc: dinguyen, devicetree, mturquette, robh+dt
Quoting Dinh Nguyen (2020-06-16 13:24:15)
> Add the NAND_X_CLK and NAND_ECC_CLK clocks.
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/3] clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk
2020-06-16 20:24 ` [PATCH 2/3] clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk Dinh Nguyen
@ 2020-06-20 2:37 ` Stephen Boyd
0 siblings, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2020-06-20 2:37 UTC (permalink / raw)
To: Dinh Nguyen, linux-clk; +Cc: dinguyen, devicetree, mturquette, robh+dt
Quoting Dinh Nguyen (2020-06-16 13:24:16)
> And the nand_x_clk and nand_ecc_clk. Make the nand_x_clk be the main
> clock that is feeding the NAND IP and correct it's parent to be the
> l4_mp_clk.
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk
2020-06-16 20:24 ` [PATCH 3/3] clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk Dinh Nguyen
@ 2020-06-20 2:37 ` Stephen Boyd
0 siblings, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2020-06-20 2:37 UTC (permalink / raw)
To: Dinh Nguyen, linux-clk; +Cc: dinguyen, devicetree, mturquette, robh+dt
Quoting Dinh Nguyen (2020-06-16 13:24:17)
> Preliminary documentation documented the mpu_l2ram_clk, but since then,
> the mpu_l2ram_clk is no longer documented. It's now referred to as
> mpu_ccu_clk.
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-06-20 2:37 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2020-06-16 20:24 [PATCH 1/3] dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK Dinh Nguyen
2020-06-16 20:24 ` [PATCH 2/3] clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk Dinh Nguyen
2020-06-20 2:37 ` Stephen Boyd
2020-06-16 20:24 ` [PATCH 3/3] clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk Dinh Nguyen
2020-06-20 2:37 ` Stephen Boyd
2020-06-20 2:37 ` [PATCH 1/3] dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK Stephen Boyd
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