* [PATCH] arm64: dts: uniphier: Add missing clock-names and reset-names to pcie-phy
@ 2020-07-08 8:56 Kunihiko Hayashi
2020-07-10 1:56 ` Masahiro Yamada
0 siblings, 1 reply; 2+ messages in thread
From: Kunihiko Hayashi @ 2020-07-08 8:56 UTC (permalink / raw)
To: Rob Herring, Masahiro Yamada
Cc: devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi
This adds missing clock-names and reset-names to pcie-phy node according to
Documentation/devicetree/bindings/phy/socionext,uniphier-pcie.yaml.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index f4a56b2..a87b8a6 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -936,7 +936,9 @@
compatible = "socionext,uniphier-ld20-pcie-phy";
reg = <0x66038000 0x4000>;
#phy-cells = <0>;
+ clock-names = "link";
clocks = <&sys_clk 24>;
+ reset-names = "link";
resets = <&sys_rst 24>;
socionext,syscon = <&soc_glue>;
};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index 72f1688..0e52dadf 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -833,7 +833,9 @@
compatible = "socionext,uniphier-pxs3-pcie-phy";
reg = <0x66038000 0x4000>;
#phy-cells = <0>;
+ clock-names = "link";
clocks = <&sys_clk 24>;
+ reset-names = "link";
resets = <&sys_rst 24>;
socionext,syscon = <&soc_glue>;
};
--
2.7.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] arm64: dts: uniphier: Add missing clock-names and reset-names to pcie-phy
2020-07-08 8:56 [PATCH] arm64: dts: uniphier: Add missing clock-names and reset-names to pcie-phy Kunihiko Hayashi
@ 2020-07-10 1:56 ` Masahiro Yamada
0 siblings, 0 replies; 2+ messages in thread
From: Masahiro Yamada @ 2020-07-10 1:56 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: Rob Herring, DTML, linux-arm-kernel, Linux Kernel Mailing List
On Wed, Jul 8, 2020 at 5:56 PM Kunihiko Hayashi
<hayashi.kunihiko@socionext.com> wrote:
>
> This adds missing clock-names and reset-names to pcie-phy node according to
> Documentation/devicetree/bindings/phy/socionext,uniphier-pcie.yaml.
Applied, but I tend to consider
b36a2472539293bcab0521bcbc284d6be0448d4b
was a misconversion (or intentional breakage)
because the original uniphier-pcie-phy.txt
did not require clock/reset-names
for ld20, pxs3.
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
> arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++
> arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
> index f4a56b2..a87b8a6 100644
> --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
> +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
> @@ -936,7 +936,9 @@
> compatible = "socionext,uniphier-ld20-pcie-phy";
> reg = <0x66038000 0x4000>;
> #phy-cells = <0>;
> + clock-names = "link";
> clocks = <&sys_clk 24>;
> + reset-names = "link";
> resets = <&sys_rst 24>;
> socionext,syscon = <&soc_glue>;
> };
> diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
> index 72f1688..0e52dadf 100644
> --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
> +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
> @@ -833,7 +833,9 @@
> compatible = "socionext,uniphier-pxs3-pcie-phy";
> reg = <0x66038000 0x4000>;
> #phy-cells = <0>;
> + clock-names = "link";
> clocks = <&sys_clk 24>;
> + reset-names = "link";
> resets = <&sys_rst 24>;
> socionext,syscon = <&soc_glue>;
> };
> --
> 2.7.4
>
--
Best Regards
Masahiro Yamada
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