* [PATCH v1 1/6] sdhci: tegra: Remove SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK for Tegra210
2020-08-03 19:44 [PATCH v1 0/6] Fix timeout clock used by hardware data timeout Sowjanya Komatineni
@ 2020-08-03 19:44 ` Sowjanya Komatineni
2020-08-03 19:44 ` [PATCH v1 2/6] sdhci: tegra: Remove SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK for Tegra186 Sowjanya Komatineni
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Sowjanya Komatineni @ 2020-08-03 19:44 UTC (permalink / raw)
To: adrian.hunter, ulf.hansson, thierry.reding, jonathanh, robh+dt
Cc: skomatineni, devicetree, linux-tegra, linux-kernel, linux-mmc
commit b5a84ecf025a ("mmc: tegra: Add Tegra210 support")
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK is set for Tegra210 from the
beginning of Tegra210 support in the driver.
Tegra210 SDMMC hardware by default uses timeout clock (TMCLK)
instead of SDCLK and this quirk should not be set.
So, this patch remove this quirk for Tegra210.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/mmc/host/sdhci-tegra.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 0a3f9d0..2be3511 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -1418,7 +1418,6 @@ static const struct sdhci_ops tegra210_sdhci_ops = {
static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
- SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
SDHCI_QUIRK_SINGLE_POWER_WRITE |
SDHCI_QUIRK_NO_HISPD_BIT |
SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v1 2/6] sdhci: tegra: Remove SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK for Tegra186
2020-08-03 19:44 [PATCH v1 0/6] Fix timeout clock used by hardware data timeout Sowjanya Komatineni
2020-08-03 19:44 ` [PATCH v1 1/6] sdhci: tegra: Remove SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK for Tegra210 Sowjanya Komatineni
@ 2020-08-03 19:44 ` Sowjanya Komatineni
2020-08-03 19:44 ` [PATCH v1 3/6] arm64: tegra: Add missing timeout clock to Tegra210 SDMMC Sowjanya Komatineni
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Sowjanya Komatineni @ 2020-08-03 19:44 UTC (permalink / raw)
To: adrian.hunter, ulf.hansson, thierry.reding, jonathanh, robh+dt
Cc: skomatineni, devicetree, linux-tegra, linux-kernel, linux-mmc
commit 4346b7c7941d ("mmc: tegra: Add Tegra186 support")
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK is set for Tegra186 from the
beginning of its support in driver.
Tegra186 SDMMC hardware by default uses timeout clock (TMCLK) instead
of SDCLK and this quirk should not be set.
So, this patch remove this quirk for Tegra186.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/mmc/host/sdhci-tegra.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 2be3511..31ed321 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -1455,7 +1455,6 @@ static const struct sdhci_ops tegra186_sdhci_ops = {
static const struct sdhci_pltfm_data sdhci_tegra186_pdata = {
.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
- SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
SDHCI_QUIRK_SINGLE_POWER_WRITE |
SDHCI_QUIRK_NO_HISPD_BIT |
SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v1 3/6] arm64: tegra: Add missing timeout clock to Tegra210 SDMMC
2020-08-03 19:44 [PATCH v1 0/6] Fix timeout clock used by hardware data timeout Sowjanya Komatineni
2020-08-03 19:44 ` [PATCH v1 1/6] sdhci: tegra: Remove SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK for Tegra210 Sowjanya Komatineni
2020-08-03 19:44 ` [PATCH v1 2/6] sdhci: tegra: Remove SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK for Tegra186 Sowjanya Komatineni
@ 2020-08-03 19:44 ` Sowjanya Komatineni
2020-08-03 19:44 ` [PATCH v1 4/6] arm64: tegra: Add missing timeout clock to Tegra186 SDMMC nodes Sowjanya Komatineni
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Sowjanya Komatineni @ 2020-08-03 19:44 UTC (permalink / raw)
To: adrian.hunter, ulf.hansson, thierry.reding, jonathanh, robh+dt
Cc: skomatineni, devicetree, linux-tegra, linux-kernel, linux-mmc
commit 742af7e7a0a1 ("arm64: tegra: Add Tegra210 support")
Tegra210 uses separate SDMMC_LEGACY_TM clock for data timeout and
this clock is not enabled currently which is not recommended.
Tegra SDMMC advertises 12Mhz as timeout clock frequency in host
capability register.
So, this clock should be kept enabled by SDMMC driver.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 829f786..8cca216 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1194,8 +1194,9 @@
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0000 0x0 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
- clock-names = "sdhci";
+ clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
+ <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
+ clock-names = "sdhci", "tmclk";
resets = <&tegra_car 14>;
reset-names = "sdhci";
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
@@ -1222,8 +1223,9 @@
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0200 0x0 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
- clock-names = "sdhci";
+ clocks = <&tegra_car TEGRA210_CLK_SDMMC2>,
+ <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
+ clock-names = "sdhci", "tmclk";
resets = <&tegra_car 9>;
reset-names = "sdhci";
pinctrl-names = "sdmmc-1v8-drv";
@@ -1239,8 +1241,9 @@
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0400 0x0 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
- clock-names = "sdhci";
+ clocks = <&tegra_car TEGRA210_CLK_SDMMC3>,
+ <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
+ clock-names = "sdhci", "tmclk";
resets = <&tegra_car 69>;
reset-names = "sdhci";
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
@@ -1262,8 +1265,9 @@
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0600 0x0 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
- clock-names = "sdhci";
+ clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
+ <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
+ clock-names = "sdhci", "tmclk";
resets = <&tegra_car 15>;
reset-names = "sdhci";
pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v1 4/6] arm64: tegra: Add missing timeout clock to Tegra186 SDMMC nodes
2020-08-03 19:44 [PATCH v1 0/6] Fix timeout clock used by hardware data timeout Sowjanya Komatineni
` (2 preceding siblings ...)
2020-08-03 19:44 ` [PATCH v1 3/6] arm64: tegra: Add missing timeout clock to Tegra210 SDMMC Sowjanya Komatineni
@ 2020-08-03 19:44 ` Sowjanya Komatineni
2020-08-03 19:44 ` [PATCH v1 5/6] arm64: tegra: Add missing timeout clock to Tegra194 " Sowjanya Komatineni
2020-08-03 19:44 ` [PATCH v1 6/6] sdhci: tegra: Add missing TMCLK for data timeout Sowjanya Komatineni
5 siblings, 0 replies; 8+ messages in thread
From: Sowjanya Komatineni @ 2020-08-03 19:44 UTC (permalink / raw)
To: adrian.hunter, ulf.hansson, thierry.reding, jonathanh, robh+dt
Cc: skomatineni, devicetree, linux-tegra, linux-kernel, linux-mmc
commit 39cb62cb8973 ("arm64: tegra: Add Tegra186 support")
Tegra186 uses separate SDMMC_LEGACY_TM clock for data timeout and
this clock is not enabled currently which is not recommended.
Tegra186 SDMMC advertises 12Mhz as timeout clock frequency in host
capability register and uses it by default.
So, this clock should be kept enabled by the SDMMC driver.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 34d249d..8eb61dd 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -337,8 +337,9 @@
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03400000 0x0 0x10000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
- clock-names = "sdhci";
+ clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
+ <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
+ clock-names = "sdhci", "tmclk";
resets = <&bpmp TEGRA186_RESET_SDMMC1>;
reset-names = "sdhci";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
@@ -366,8 +367,9 @@
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03420000 0x0 0x10000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
- clock-names = "sdhci";
+ clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
+ <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
+ clock-names = "sdhci", "tmclk";
resets = <&bpmp TEGRA186_RESET_SDMMC2>;
reset-names = "sdhci";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
@@ -390,8 +392,9 @@
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03440000 0x0 0x10000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
- clock-names = "sdhci";
+ clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
+ <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
+ clock-names = "sdhci", "tmclk";
resets = <&bpmp TEGRA186_RESET_SDMMC3>;
reset-names = "sdhci";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
@@ -416,8 +419,9 @@
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03460000 0x0 0x10000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
- clock-names = "sdhci";
+ clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
+ <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
+ clock-names = "sdhci", "tmclk";
assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
<&bpmp TEGRA186_CLK_PLLC4_VCO>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v1 5/6] arm64: tegra: Add missing timeout clock to Tegra194 SDMMC nodes
2020-08-03 19:44 [PATCH v1 0/6] Fix timeout clock used by hardware data timeout Sowjanya Komatineni
` (3 preceding siblings ...)
2020-08-03 19:44 ` [PATCH v1 4/6] arm64: tegra: Add missing timeout clock to Tegra186 SDMMC nodes Sowjanya Komatineni
@ 2020-08-03 19:44 ` Sowjanya Komatineni
2020-08-03 19:44 ` [PATCH v1 6/6] sdhci: tegra: Add missing TMCLK for data timeout Sowjanya Komatineni
5 siblings, 0 replies; 8+ messages in thread
From: Sowjanya Komatineni @ 2020-08-03 19:44 UTC (permalink / raw)
To: adrian.hunter, ulf.hansson, thierry.reding, jonathanh, robh+dt
Cc: skomatineni, devicetree, linux-tegra, linux-kernel, linux-mmc
commit 5425fb15d8ee ("arm64: tegra: Add Tegra194 chip device tree")
Tegra194 uses separate SDMMC_LEGACY_TM clock for data timeout and
this clock is not enabled currently which is not recommended.
Tegra194 SDMMC advertises 12Mhz as timeout clock frequency in host
capability register.
So, this clock should be kept enabled by SDMMC driver.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 48160f4..ca5cb6a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -460,8 +460,9 @@
compatible = "nvidia,tegra194-sdhci";
reg = <0x03400000 0x10000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
- clock-names = "sdhci";
+ clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
+ <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
+ clock-names = "sdhci", "tmclk";
resets = <&bpmp TEGRA194_RESET_SDMMC1>;
reset-names = "sdhci";
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
@@ -485,8 +486,9 @@
compatible = "nvidia,tegra194-sdhci";
reg = <0x03440000 0x10000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
- clock-names = "sdhci";
+ clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
+ <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
+ clock-names = "sdhci", "tmclk";
resets = <&bpmp TEGRA194_RESET_SDMMC3>;
reset-names = "sdhci";
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
@@ -511,8 +513,9 @@
compatible = "nvidia,tegra194-sdhci";
reg = <0x03460000 0x10000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
- clock-names = "sdhci";
+ clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
+ <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
+ clock-names = "sdhci", "tmclk";
assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
<&bpmp TEGRA194_CLK_PLLC4>;
assigned-clock-parents =
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v1 6/6] sdhci: tegra: Add missing TMCLK for data timeout
2020-08-03 19:44 [PATCH v1 0/6] Fix timeout clock used by hardware data timeout Sowjanya Komatineni
` (4 preceding siblings ...)
2020-08-03 19:44 ` [PATCH v1 5/6] arm64: tegra: Add missing timeout clock to Tegra194 " Sowjanya Komatineni
@ 2020-08-03 19:44 ` Sowjanya Komatineni
2020-08-04 2:26 ` kernel test robot
5 siblings, 1 reply; 8+ messages in thread
From: Sowjanya Komatineni @ 2020-08-03 19:44 UTC (permalink / raw)
To: adrian.hunter, ulf.hansson, thierry.reding, jonathanh, robh+dt
Cc: skomatineni, devicetree, linux-tegra, linux-kernel, linux-mmc
commit b5a84ecf025a ("mmc: tegra: Add Tegra210 support")
Tegra210 and later has a separate sdmmc_legacy_tm (TMCLK) used by Tegra
SDMMC hawdware for data timeout to achive better timeout than using
SDCLK and using TMCLK is recommended.
USE_TMCLK_FOR_DATA_TIMEOUT bit in Tegra SDMMC register
SDHCI_TEGRA_VENDOR_SYS_SW_CTRL can be used to choose either TMCLK or
SDCLK for data timeout.
Default USE_TMCLK_FOR_DATA_TIMEOUT bit is set to 1 and TMCLK is used
for data timeout by Tegra SDMMC hardware and having TMCLK not enabled
is not recommended.
So, this patch fixes it.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/mmc/host/sdhci-tegra.c | 41 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 31ed321..39e2195 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -140,6 +140,7 @@ struct sdhci_tegra_autocal_offsets {
struct sdhci_tegra {
const struct sdhci_tegra_soc_data *soc_data;
struct gpio_desc *power_gpio;
+ struct clk *tmclk;
bool ddr_signaling;
bool pad_calib_required;
bool pad_control_available;
@@ -1611,6 +1612,44 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
goto err_power_req;
}
+ /*
+ * Tegra210 has a separate SDMMC_LEGACY_TM clock used for host
+ * timeout clock and SW can choose TMCLK or SDCLK for hardware
+ * data timeout through the bit USE_TMCLK_FOR_DATA_TIMEOUT of
+ * the register SDHCI_TEGRA_VENDOR_SYS_SW_CTRL.
+ *
+ * USE_TMCLK_FOR_DATA_TIMEOUT bit default is set to 1 and SDMMC uses
+ * 12Mhz TMCLK which is advertised in host capability register.
+ * With TMCLK of 12Mhz provides maximum data timeout period that can
+ * be achieved is 11s better than using SDCLK for data timeout.
+ *
+ * So, TMCLK is set to 12Mhz and kept enabled all the time on SoC's
+ * supporting SDR104 mode and when not using SDCLK for data timeout.
+ */
+
+ if ((soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) &&
+ (!soc_data->pdata->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
+ clk = devm_clk_get(&pdev->dev, "tmclk");
+ if (IS_ERR(clk)) {
+ rc = PTR_ERR(clk);
+ if (rc == -EPROBE_DEFER)
+ goto err_power_req;
+
+ dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc);
+ clk = NULL;
+ }
+
+ clk_set_rate(clk, 12000000);
+ rc = clk_prepare_enable(clk);
+ if (rc) {
+ dev_err(&pdev->dev,
+ "failed to enable tmclk: %d\n", rc);
+ goto err_power_req;
+ }
+
+ tegra_host->tmclk = clk;
+ }
+
clk = devm_clk_get(mmc_dev(host->mmc), NULL);
if (IS_ERR(clk)) {
rc = PTR_ERR(clk);
@@ -1654,6 +1693,7 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
err_rst_get:
clk_disable_unprepare(pltfm_host->clk);
err_clk_get:
+ clk_disable_unprepare(tegra_host->tmclk);
err_power_req:
err_parse_dt:
sdhci_pltfm_free(pdev);
@@ -1671,6 +1711,7 @@ static int sdhci_tegra_remove(struct platform_device *pdev)
reset_control_assert(tegra_host->rst);
usleep_range(2000, 4000);
clk_disable_unprepare(pltfm_host->clk);
+ clk_disable_unprepare(tegra_host->tmclk);
sdhci_pltfm_free(pdev);
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v1 6/6] sdhci: tegra: Add missing TMCLK for data timeout
2020-08-03 19:44 ` [PATCH v1 6/6] sdhci: tegra: Add missing TMCLK for data timeout Sowjanya Komatineni
@ 2020-08-04 2:26 ` kernel test robot
0 siblings, 0 replies; 8+ messages in thread
From: kernel test robot @ 2020-08-04 2:26 UTC (permalink / raw)
To: Sowjanya Komatineni, adrian.hunter, ulf.hansson, thierry.reding,
jonathanh, robh+dt
Cc: kbuild-all, skomatineni, devicetree, linux-tegra, linux-kernel,
linux-mmc
[-- Attachment #1: Type: text/plain, Size: 6740 bytes --]
Hi Sowjanya,
I love your patch! Perhaps something to improve:
[auto build test WARNING on tegra/for-next]
[also build test WARNING on robh/for-next v5.8 next-20200803]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Sowjanya-Komatineni/Fix-timeout-clock-used-by-hardware-data-timeout/20200804-034552
base: https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git for-next
config: arm-defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
drivers/mmc/host/sdhci-tegra.c: In function 'sdhci_tegra_probe':
>> drivers/mmc/host/sdhci-tegra.c:1622:7: warning: suggest parentheses around operand of '!' or change '&' to '&&' or '!' to '~' [-Wparentheses]
1622 | (!soc_data->pdata->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
| ^~~~~~~~~~~~~~~~~~~~~~~~
vim +1622 drivers/mmc/host/sdhci-tegra.c
1542
1543 static int sdhci_tegra_probe(struct platform_device *pdev)
1544 {
1545 const struct of_device_id *match;
1546 const struct sdhci_tegra_soc_data *soc_data;
1547 struct sdhci_host *host;
1548 struct sdhci_pltfm_host *pltfm_host;
1549 struct sdhci_tegra *tegra_host;
1550 struct clk *clk;
1551 int rc;
1552
1553 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
1554 if (!match)
1555 return -EINVAL;
1556 soc_data = match->data;
1557
1558 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
1559 if (IS_ERR(host))
1560 return PTR_ERR(host);
1561 pltfm_host = sdhci_priv(host);
1562
1563 tegra_host = sdhci_pltfm_priv(pltfm_host);
1564 tegra_host->ddr_signaling = false;
1565 tegra_host->pad_calib_required = false;
1566 tegra_host->pad_control_available = false;
1567 tegra_host->soc_data = soc_data;
1568
1569 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) {
1570 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host);
1571 if (rc == 0)
1572 host->mmc_host_ops.start_signal_voltage_switch =
1573 sdhci_tegra_start_signal_voltage_switch;
1574 }
1575
1576 /* Hook to periodically rerun pad calibration */
1577 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
1578 host->mmc_host_ops.request = tegra_sdhci_request;
1579
1580 host->mmc_host_ops.hs400_enhanced_strobe =
1581 tegra_sdhci_hs400_enhanced_strobe;
1582
1583 if (!host->ops->platform_execute_tuning)
1584 host->mmc_host_ops.execute_tuning =
1585 tegra_sdhci_execute_hw_tuning;
1586
1587 rc = mmc_of_parse(host->mmc);
1588 if (rc)
1589 goto err_parse_dt;
1590
1591 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
1592 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1593
1594 /* HW busy detection is supported, but R1B responses are required. */
1595 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
1596
1597 tegra_sdhci_parse_dt(host);
1598
1599 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
1600 GPIOD_OUT_HIGH);
1601 if (IS_ERR(tegra_host->power_gpio)) {
1602 rc = PTR_ERR(tegra_host->power_gpio);
1603 goto err_power_req;
1604 }
1605
1606 /*
1607 * Tegra210 has a separate SDMMC_LEGACY_TM clock used for host
1608 * timeout clock and SW can choose TMCLK or SDCLK for hardware
1609 * data timeout through the bit USE_TMCLK_FOR_DATA_TIMEOUT of
1610 * the register SDHCI_TEGRA_VENDOR_SYS_SW_CTRL.
1611 *
1612 * USE_TMCLK_FOR_DATA_TIMEOUT bit default is set to 1 and SDMMC uses
1613 * 12Mhz TMCLK which is advertised in host capability register.
1614 * With TMCLK of 12Mhz provides maximum data timeout period that can
1615 * be achieved is 11s better than using SDCLK for data timeout.
1616 *
1617 * So, TMCLK is set to 12Mhz and kept enabled all the time on SoC's
1618 * supporting SDR104 mode and when not using SDCLK for data timeout.
1619 */
1620
1621 if ((soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) &&
> 1622 (!soc_data->pdata->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
1623 clk = devm_clk_get(&pdev->dev, "tmclk");
1624 if (IS_ERR(clk)) {
1625 rc = PTR_ERR(clk);
1626 if (rc == -EPROBE_DEFER)
1627 goto err_power_req;
1628
1629 dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc);
1630 clk = NULL;
1631 }
1632
1633 clk_set_rate(clk, 12000000);
1634 rc = clk_prepare_enable(clk);
1635 if (rc) {
1636 dev_err(&pdev->dev,
1637 "failed to enable tmclk: %d\n", rc);
1638 goto err_power_req;
1639 }
1640
1641 tegra_host->tmclk = clk;
1642 }
1643
1644 clk = devm_clk_get(mmc_dev(host->mmc), NULL);
1645 if (IS_ERR(clk)) {
1646 rc = PTR_ERR(clk);
1647
1648 if (rc != -EPROBE_DEFER)
1649 dev_err(&pdev->dev, "failed to get clock: %d\n", rc);
1650
1651 goto err_clk_get;
1652 }
1653 clk_prepare_enable(clk);
1654 pltfm_host->clk = clk;
1655
1656 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev,
1657 "sdhci");
1658 if (IS_ERR(tegra_host->rst)) {
1659 rc = PTR_ERR(tegra_host->rst);
1660 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc);
1661 goto err_rst_get;
1662 }
1663
1664 rc = reset_control_assert(tegra_host->rst);
1665 if (rc)
1666 goto err_rst_get;
1667
1668 usleep_range(2000, 4000);
1669
1670 rc = reset_control_deassert(tegra_host->rst);
1671 if (rc)
1672 goto err_rst_get;
1673
1674 usleep_range(2000, 4000);
1675
1676 rc = sdhci_tegra_add_host(host);
1677 if (rc)
1678 goto err_add_host;
1679
1680 return 0;
1681
1682 err_add_host:
1683 reset_control_assert(tegra_host->rst);
1684 err_rst_get:
1685 clk_disable_unprepare(pltfm_host->clk);
1686 err_clk_get:
1687 clk_disable_unprepare(tegra_host->tmclk);
1688 err_power_req:
1689 err_parse_dt:
1690 sdhci_pltfm_free(pdev);
1691 return rc;
1692 }
1693
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
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