* [PATCH v2] Add DT bindings and DT nodes for USB in SC7280 @ 2021-04-22 17:35 Sandeep Maheswaram 2021-04-22 17:35 ` [PATCH v2] arm64: dts: qcom: sc7280: Add USB related nodes Sandeep Maheswaram 0 siblings, 1 reply; 4+ messages in thread From: Sandeep Maheswaram @ 2021-04-22 17:35 UTC (permalink / raw) To: Rob Herring, Andy Gross, Bjorn Andersson, Greg Kroah-Hartman, Felipe Balbi, Stephen Boyd, Doug Anderson, Matthias Kaehlcke Cc: devicetree, linux-arm-msm, linux-usb, linux-kernel, Manu Gautam, Sandeep Maheswaram This series includes usb controller and phy binding updates for SC7280 SoC and DT chnages for SC7280 SoC and SC7280 IDP board. changes in v2: Dropped dt bindings patches as they are already merged in linux-next. Addressed comments from Matthias in v1. Sandeep Maheswaram (1): arm64: dts: qcom: sc7280: Add USB related nodes arch/arm64/boot/dts/qcom/sc7280-idp.dts | 40 +++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 150 ++++++++++++++++++++++++++++++++ 2 files changed, 190 insertions(+) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v2] arm64: dts: qcom: sc7280: Add USB related nodes 2021-04-22 17:35 [PATCH v2] Add DT bindings and DT nodes for USB in SC7280 Sandeep Maheswaram @ 2021-04-22 17:35 ` Sandeep Maheswaram 2021-04-22 18:34 ` Matthias Kaehlcke 0 siblings, 1 reply; 4+ messages in thread From: Sandeep Maheswaram @ 2021-04-22 17:35 UTC (permalink / raw) To: Rob Herring, Andy Gross, Bjorn Andersson, Greg Kroah-Hartman, Felipe Balbi, Stephen Boyd, Doug Anderson, Matthias Kaehlcke Cc: devicetree, linux-arm-msm, linux-usb, linux-kernel, Manu Gautam, Sandeep Maheswaram Add nodes for DWC3 USB controller, QMP and HS USB PHYs. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 40 +++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 150 ++++++++++++++++++++++++++++++++ 2 files changed, 190 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 54d2cb3..f1998d8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -242,6 +242,46 @@ status = "okay"; }; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l10c_0p8>; + vdda33-supply = <&vreg_l2b_3p0>; + vdda18-supply = <&vreg_l1c_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p8>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l10c_0p8>; + vdda33-supply = <&vreg_l2b_3p0>; + vdda18-supply = <&vreg_l1c_1p8>; +}; + /* PINCTRL - additions to nodes defined in sc7280.dtsi */ &qup_uart5_default { diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 2cc4785..8323f53 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -805,6 +805,110 @@ }; }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sc7280-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e3000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; + + usb_2_hsphy: phy@88e4000 { + compatible = "qcom,sc7280-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e4000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + }; + + usb_1_qmpphy: phy-wrapper@88e9000 { + compatible = "qcom,sm8250-qmp-usb3-phy"; + reg = <0 0x088e9000 0 0x200>, + <0 0x088e8000 0 0x20>; + reg-names = "reg-base", "dp_com"; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "com_aux"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + usb_1_ssphy: usb3-phy@88e9200 { + reg = <0 0x088e9200 0 0x200>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x400>, + <0 0x088e9600 0 0x200>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x100>; + #phy-cells = <0>; + #clock-cells = <1>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; + }; + + usb_2: usb@8cf8800 { + compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; + reg = <0 0x08cf8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface","mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 13 IRQ_TYPE_EDGE_RISING>, + <&pdc 12 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "hs_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + power-domains = <&gcc GCC_USB30_SEC_GDSC>; + + resets = <&gcc GCC_USB30_SEC_BCR>; + + usb_2_dwc3: dwc3@8c00000 { + compatible = "snps,dwc3"; + reg = <0 0x08c00000 0 0xe000>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0xa0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + }; + }; + system-cache-controller@9200000 { compatible = "qcom,sc7280-llcc"; reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; @@ -812,6 +916,52 @@ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; + usb_1: usb@a6f8800 { + compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + usb_1_dwc3: dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xe000>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0xe0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + maximum-speed = "super-speed"; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v2] arm64: dts: qcom: sc7280: Add USB related nodes 2021-04-22 17:35 ` [PATCH v2] arm64: dts: qcom: sc7280: Add USB related nodes Sandeep Maheswaram @ 2021-04-22 18:34 ` Matthias Kaehlcke 2021-04-22 21:38 ` Doug Anderson 0 siblings, 1 reply; 4+ messages in thread From: Matthias Kaehlcke @ 2021-04-22 18:34 UTC (permalink / raw) To: Sandeep Maheswaram Cc: Rob Herring, Andy Gross, Bjorn Andersson, Greg Kroah-Hartman, Felipe Balbi, Stephen Boyd, Doug Anderson, devicetree, linux-arm-msm, linux-usb, linux-kernel, Manu Gautam On Thu, Apr 22, 2021 at 11:05:31PM +0530, Sandeep Maheswaram wrote: > Add nodes for DWC3 USB controller, QMP and HS USB PHYs. > > Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> > --- What changes with respect to v1? Please always include a change log for versions > 1 > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 40 +++++++++ > arch/arm64/boot/dts/qcom/sc7280.dtsi | 150 ++++++++++++++++++++++++++++++++ > 2 files changed, 190 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > index 54d2cb3..f1998d8 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts I suggest to split this into two patches, one for the SoC and one for the board (IDP). That way it is evident from the subject what each patch does and reverts could be done individually if needed. > @@ -242,6 +242,46 @@ > status = "okay"; > }; > > + don't add a second empty line > +&usb_1 { > + status = "okay"; > +}; > + > +&usb_1_dwc3 { > + dr_mode = "host"; > +}; > + > +&usb_1_hsphy { > + status = "okay"; > + > + vdda-pll-supply = <&vreg_l10c_0p8>; > + vdda33-supply = <&vreg_l2b_3p0>; > + vdda18-supply = <&vreg_l1c_1p8>; > +}; > + > +&usb_1_qmpphy { > + status = "okay"; > + > + vdda-phy-supply = <&vreg_l6b_1p2>; > + vdda-pll-supply = <&vreg_l1b_0p8>; > +}; > + > +&usb_2 { > + status = "okay"; > +}; > + > +&usb_2_dwc3 { > + dr_mode = "peripheral"; > +}; > + > +&usb_2_hsphy { > + status = "okay"; > + > + vdda-pll-supply = <&vreg_l10c_0p8>; > + vdda33-supply = <&vreg_l2b_3p0>; > + vdda18-supply = <&vreg_l1c_1p8>; > +}; > + > /* PINCTRL - additions to nodes defined in sc7280.dtsi */ > > &qup_uart5_default { > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 2cc4785..8323f53 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -805,6 +805,110 @@ > }; > }; > > + usb_1_hsphy: phy@88e3000 { > + compatible = "qcom,sc7280-usb-hs-phy", > + "qcom,usb-snps-hs-7nm-phy"; > + reg = <0 0x088e3000 0 0x400>; > + status = "disabled"; > + #phy-cells = <0>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > + }; > + > + usb_2_hsphy: phy@88e4000 { > + compatible = "qcom,sc7280-usb-hs-phy", > + "qcom,usb-snps-hs-7nm-phy"; > + reg = <0 0x088e4000 0 0x400>; > + status = "disabled"; > + #phy-cells = <0>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; > + }; > + > + usb_1_qmpphy: phy-wrapper@88e9000 { > + compatible = "qcom,sm8250-qmp-usb3-phy"; > + reg = <0 0x088e9000 0 0x200>, > + <0 0x088e8000 0 0x20>; > + reg-names = "reg-base", "dp_com"; > + status = "disabled"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; > + clock-names = "aux", "ref_clk_src", "com_aux"; > + > + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, > + <&gcc GCC_USB3_PHY_PRIM_BCR>; > + reset-names = "phy", "common"; > + > + usb_1_ssphy: usb3-phy@88e9200 { > + reg = <0 0x088e9200 0 0x200>, > + <0 0x088e9400 0 0x200>, > + <0 0x088e9c00 0 0x400>, > + <0 0x088e9600 0 0x200>, > + <0 0x088e9800 0 0x200>, > + <0 0x088e9a00 0 0x100>; > + #phy-cells = <0>; > + #clock-cells = <1>; > + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > + clock-names = "pipe0"; > + clock-output-names = "usb3_phy_pipe_clk_src"; > + }; > + }; > + > + usb_2: usb@8cf8800 { > + compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; > + reg = <0 0x08cf8800 0 0x400>; > + status = "disabled"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + dma-ranges; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, > + <&gcc GCC_USB30_SEC_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, > + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_SEC_SLEEP_CLK>; > + clock-names = "cfg_noc", "core", "iface","mock_utmi", > + "sleep"; > + > + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_SEC_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <200000000>; > + > + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 13 IRQ_TYPE_EDGE_RISING>, > + <&pdc 12 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "hs_phy_irq", > + "dm_hs_phy_irq", "dp_hs_phy_irq"; > + > + power-domains = <&gcc GCC_USB30_SEC_GDSC>; > + > + resets = <&gcc GCC_USB30_SEC_BCR>; > + > + usb_2_dwc3: dwc3@8c00000 { > + compatible = "snps,dwc3"; > + reg = <0 0x08c00000 0 0xe000>; > + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; > + iommus = <&apps_smmu 0xa0 0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + phys = <&usb_2_hsphy>; > + phy-names = "usb2-phy"; > + maximum-speed = "high-speed"; > + }; > + }; > + > system-cache-controller@9200000 { > compatible = "qcom,sc7280-llcc"; > reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; > @@ -812,6 +916,52 @@ > interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; > }; > > + usb_1: usb@a6f8800 { > + compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; > + reg = <0 0x0a6f8800 0 0x400>; > + status = "disabled"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + dma-ranges; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; > + nit: remove empty line (as for 'usb_2' above), 'clocks' and 'clock-names' belong together > + clock-names = "cfg_noc", "core", "iface", "mock_utmi", > + "sleep"; > + > + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <200000000>; > + > + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, > + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, > + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", > + "dm_hs_phy_irq", "ss_phy_irq"; > + > + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; > + > + resets = <&gcc GCC_USB30_PRIM_BCR>; > + > + usb_1_dwc3: dwc3@a600000 { > + compatible = "snps,dwc3"; > + reg = <0 0x0a600000 0 0xe000>; > + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; > + iommus = <&apps_smmu 0xe0 0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; > + phy-names = "usb2-phy", "usb3-phy"; > + maximum-speed = "super-speed"; > + }; > + }; > + > pdc: interrupt-controller@b220000 { > compatible = "qcom,sc7280-pdc", "qcom,pdc"; > reg = <0 0x0b220000 0 0x30000>; ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2] arm64: dts: qcom: sc7280: Add USB related nodes 2021-04-22 18:34 ` Matthias Kaehlcke @ 2021-04-22 21:38 ` Doug Anderson 0 siblings, 0 replies; 4+ messages in thread From: Doug Anderson @ 2021-04-22 21:38 UTC (permalink / raw) To: Matthias Kaehlcke Cc: Sandeep Maheswaram, Rob Herring, Andy Gross, Bjorn Andersson, Greg Kroah-Hartman, Felipe Balbi, Stephen Boyd, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm, Linux USB List, LKML, Manu Gautam Hi, On Thu, Apr 22, 2021 at 11:34 AM Matthias Kaehlcke <mka@chromium.org> wrote: > > On Thu, Apr 22, 2021 at 11:05:31PM +0530, Sandeep Maheswaram wrote: > > Add nodes for DWC3 USB controller, QMP and HS USB PHYs. > > > > Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> > > --- > > What changes with respect to v1? Please always include a change log for > versions > 1 It looks like this was here: https://lore.kernel.org/r/1619112931-2144-1-git-send-email-sanm@codeaurora.org/ ...which I guess is a "cover letter", though it's not really formatted properly (it should usually be listed as "patch 0" in the series) and also cover letters are discouraged for singleton patches like this. Also: even when history is added to a cover letter it's usually friendly to reviewers to also include it after-the-cut in your patch. -Doug ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-04-22 21:38 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-04-22 17:35 [PATCH v2] Add DT bindings and DT nodes for USB in SC7280 Sandeep Maheswaram 2021-04-22 17:35 ` [PATCH v2] arm64: dts: qcom: sc7280: Add USB related nodes Sandeep Maheswaram 2021-04-22 18:34 ` Matthias Kaehlcke 2021-04-22 21:38 ` Doug Anderson
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