* [PATCH 2/2] arm64: dts: rockchip: add pwm nodes for rk3568
2021-07-26 9:03 [PATCH 1/2] dt-bindings: pwm: rockchip: add description for rk3568 Heiko Stuebner
@ 2021-07-26 9:03 ` Heiko Stuebner
2021-07-26 9:08 ` [PATCH 1/2] dt-bindings: pwm: rockchip: add description " Heiko Stübner
2021-09-27 21:47 ` (subset) " Heiko Stuebner
2 siblings, 0 replies; 4+ messages in thread
From: Heiko Stuebner @ 2021-07-26 9:03 UTC (permalink / raw)
To: thierry.reding, lee.jones
Cc: u.kleine-koenig, robh+dt, cl, pgwipeout, xxm, linux-pwm,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel,
Heiko Stuebner
From: Liang Chen <cl@rock-chips.com>
Add the pwm controller nodes to the core rk3568 dtsi.
Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 176 +++++++++++++++++++++++
1 file changed, 176 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 322971318d5a..a424edc81a9e 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -251,6 +251,50 @@ uart0: serial@fdd50000 {
status = "disabled";
};
+ pwm0: pwm@fdd70000 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfdd70000 0x0 0x10>;
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm0m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@fdd70010 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfdd70010 0x0 0x10>;
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm1m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@fdd70020 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfdd70020 0x0 0x10>;
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm2m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@fdd70030 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfdd70030 0x0 0x10>;
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm3_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
pmu: power-management@fdd90000 {
compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
reg = <0x0 0xfdd90000 0x0 0x1000>;
@@ -738,6 +782,138 @@ saradc: saradc@fe720000 {
status = "disabled";
};
+ pwm4: pwm@fe6e0000 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe6e0000 0x0 0x10>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm4_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@fe6e0010 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe6e0010 0x0 0x10>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm5_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@fe6e0020 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe6e0020 0x0 0x10>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm6_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm7: pwm@fe6e0030 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe6e0030 0x0 0x10>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm7_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm8: pwm@fe6f0000 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe6f0000 0x0 0x10>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm8m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm9: pwm@fe6f0010 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe6f0010 0x0 0x10>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm9m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm10: pwm@fe6f0020 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe6f0020 0x0 0x10>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm10m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm11: pwm@fe6f0030 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe6f0030 0x0 0x10>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm11m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm12: pwm@fe700000 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe700000 0x0 0x10>;
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm12m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm13: pwm@fe700010 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe700010 0x0 0x10>;
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm13m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm14: pwm@fe700020 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe700020 0x0 0x10>;
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm14m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm15: pwm@fe700030 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe700030 0x0 0x10>;
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm15m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3568-pinctrl";
rockchip,grf = <&grf>;
--
2.29.2
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH 1/2] dt-bindings: pwm: rockchip: add description for rk3568
2021-07-26 9:03 [PATCH 1/2] dt-bindings: pwm: rockchip: add description for rk3568 Heiko Stuebner
2021-07-26 9:03 ` [PATCH 2/2] arm64: dts: rockchip: add pwm nodes " Heiko Stuebner
@ 2021-07-26 9:08 ` Heiko Stübner
2021-09-27 21:47 ` (subset) " Heiko Stuebner
2 siblings, 0 replies; 4+ messages in thread
From: Heiko Stübner @ 2021-07-26 9:08 UTC (permalink / raw)
To: thierry.reding, lee.jones
Cc: u.kleine-koenig, robh+dt, cl, pgwipeout, xxm, linux-pwm,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel
Am Montag, 26. Juli 2021, 11:03:54 CEST schrieb Heiko Stuebner:
> From: Liang Chen <cl@rock-chips.com>
>
> add "rockchip,rk3568-pwm", "rockchip,rk3328-pwm" for pwm nodes on
> a rk3568 platform to pwm-rockchip.yaml.
>
> Signed-off-by: Liang Chen <cl@rock-chips.com>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Sorry, forgot to read the slightly longer original reply thread.
The binding is already:
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
And I guess the pwm maintainers would be responsible for picking
up the binding addition and I will pick the devicetree addition after that.
Heiko
> ---
> The core rk3568 support was mostly applied, leaving out the pwm
> parts. So I've separated the binding and dtsi patch out
> into its owm series, so it can be better reviewed.
>
> Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml b/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml
> index 5596bee70509..81a54a4e8e3e 100644
> --- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml
> +++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml
> @@ -29,6 +29,7 @@ properties:
> - enum:
> - rockchip,px30-pwm
> - rockchip,rk3308-pwm
> + - rockchip,rk3568-pwm
> - const: rockchip,rk3328-pwm
>
> reg:
>
^ permalink raw reply [flat|nested] 4+ messages in thread