From: Yunus Bas <Y.Bas@phytec.de>
To: "shawnguo@kernel.org" <shawnguo@kernel.org>
Cc: "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
"festevam@gmail.com" <festevam@gmail.com>,
"kernel@pengutronix.de" <kernel@pengutronix.de>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"robh+dt@kernel.org" <robh+dt@kernel.org>
Subject: Re: [PATCH 3/3] ARM: dts: imx6: phytec: Add PEB-WLBT-05 support
Date: Mon, 13 Dec 2021 12:21:09 +0000 [thread overview]
Message-ID: <1c12e44919883c82ead0ac7b07bf62ee863fb0d8.camel@phytec.de> (raw)
In-Reply-To: <20211206025753.GY4216@dragon>
Hi Shawn,
Am Montag, dem 06.12.2021 um 10:57 +0800 schrieb Shawn Guo:
> On Tue, Nov 30, 2021 at 09:53:55AM +0100, Yunus Bas wrote:
> > The PEB-WLBT-05 is equipped with a Sterling-LWB radio module, which
> > is
> > capable of Wi-Fi 802.11 b/g/n and Bluetooth 4.2.
> >
> > Signed-off-by: Yunus Bas <y.bas@phytec.de>
> > ---
> > .../boot/dts/imx6dl-phytec-mira-rdk-nand.dts | 1 +
> > .../boot/dts/imx6q-phytec-mira-rdk-emmc.dts | 1 +
> > .../boot/dts/imx6q-phytec-mira-rdk-nand.dts | 1 +
> > .../dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi | 82
> > +++++++++++++++++
> > .../boot/dts/imx6qp-phytec-mira-rdk-nand.dts | 1 +
> > .../dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 1 +
> > .../dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi | 88
> > +++++++++++++++++++
> > .../dts/imx6ull-phytec-segin-ff-rdk-nand.dts | 1 +
> > .../dts/imx6ull-phytec-segin-lc-rdk-nand.dts | 1 +
> > .../dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi | 19 ++++
> > 10 files changed, 196 insertions(+)
> > create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-
> > 05.dtsi
> > create mode 100644 arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-
> > 05.dtsi
> > create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-peb-
> > wlbt-05.dtsi
> >
> > diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
> > b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
> > index 8165fae2b1d1..d906a7f05aaa 100644
> > --- a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
> > +++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
> > @@ -10,6 +10,7 @@
> > #include "imx6qdl-phytec-mira.dtsi"
> > #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
> > #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
> > +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
> >
> > / {
> > model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board
> > with NAND";
> > diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
> > b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
> > index bbf5097ca974..322f071d972f 100644
> > --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
> > +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
> > @@ -10,6 +10,7 @@
> > #include "imx6qdl-phytec-mira.dtsi"
> > #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
> > #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
> > +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
> >
> > / {
> > model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with
> > eMMC";
> > diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
> > b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
> > index 95051e18324f..3f13726c8058 100644
> > --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
> > +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
> > @@ -10,6 +10,7 @@
> > #include "imx6qdl-phytec-mira.dtsi"
> > #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
> > #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
> > +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
> >
> > / {
> > model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with
> > NAND";
> > diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi
> > b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi
> > new file mode 100644
> > index 000000000000..13d64393b5a5
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi
> > @@ -0,0 +1,82 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright (C) 2021 PHYTEC Messtechnik GmbH
> > + * Author: Yunus Bas <y.bas@phytec.de>
> > + */
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > + reg_wl_en: regulator-wl-en {
> > + compatible = "regulator-fixed";
> > + regulator-name = "wlan_en";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_wl>;
> > + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
> > + startup-delay-us = <100>;
> > + enable-active-high;
>
> Put it right after "gpio" line.
Will do. Thanks.
>
> > + status = "disabled";
> > + };
> > +};
> > +
> > +&uart3 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_uart3_bt>;
> > + uart-has-rtscts;
> > +
> > + bluetooth {
> > + compatible = "brcm,bcm43438-bt";
> > + shutdown-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
> > + device-wakeup-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
> > + host-wakeup-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>;
> > + status = "disabled";
> > + };
> > +};
> > +
> > +&usdhc3 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_usdhc3_wl>;
> > + vmmc-supply = <®_wl_en>;
> > + bus-width = <4>;
> > + non-removable;
> > + no-1-8-v;
> > + status = "disabled";
> > +
> > + brmcf: wifi@1 {
> > + compatible = "brcm,bcm4329-fmac";
>
> Did you run dtbs_check against brcm,bcm4329-fmac.yaml?
>
I did. Everything seems to be correct here. The compatible is also
correct, I double checked it. Is there something I'm missing?
> > + };
> > +};
> > +
> > +&iomuxc {
> > + pinctrl_uart3_bt: uart3grp_bt {
>
> Hyphen is more recommended for node name.
Yes, of course. Sorry I missed that.
Thanks.
Regards
Yunus
>
> Shawn
>
> > + fsl,pins = <
> > + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1
> > b0b1
> > + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1
> > b0b1
> > + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1
> > b0b1
> > + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1
> > b0b1
> > + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0xb
> > 0b1 /* BT ENABLE */
> > + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0xb
> > 0b1 /* DEV WAKEUP */
> > + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0xb
> > 0b1 /* HOST WAKEUP */
> > + >;
> > + };
> > +
> > + pinctrl_usdhc3_wl: usdhc3grp_wl {
> > + fsl,pins = <
> > + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x1
> > 7059
> > + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x1
> > 0059
> > + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x1
> > 7059
> > + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x1
> > 7059
> > + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x1
> > 7059
> > + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x1
> > 7059
> > + >;
> > + };
> > +
> > + pinctrl_wl: wlgrp {
> > + fsl,pins = <
> > + MX6QDL_PAD_EIM_A25__GPIO5_IO02
> > 0xb0b1 /* WLAN ENABLE */
> > + >;
> > + };
> > +};
> > diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
> > b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
> > index 343639cb035c..a18266598d39 100644
> > --- a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
> > +++ b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
> > @@ -10,6 +10,7 @@
> > #include "imx6qdl-phytec-mira.dtsi"
> > #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
> > #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
> > +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
> >
> > / {
> > model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with
> > NAND";
> > diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
> > b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
> > index bff98e676980..607eddc5030f 100644
> > --- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
> > +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
> > @@ -10,6 +10,7 @@
> > #include "imx6ul-phytec-segin.dtsi"
> > #include "imx6ul-phytec-segin-peb-eval-01.dtsi"
> > #include "imx6ul-phytec-segin-peb-av-02.dtsi"
> > +#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi"
> >
> > / {
> > model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full
> > Featured with NAND";
> > diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi
> > b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi
> > new file mode 100644
> > index 000000000000..5312a2a2efe3
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi
> > @@ -0,0 +1,88 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright (C) 2021 PHYTEC Messtechnik GmbH
> > + * Author: Yunus Bas <y.bas@phytec.de>
> > + */
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > + reg_wl_en: regulator-wl-en {
> > + compatible = "regulator-fixed";
> > + regulator-name = "wlan_en";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_wl>;
> > + gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
> > + startup-delay-us = <100>;
> > + enable-active-high;
> > + status = "disabled";
> > + };
> > +};
> > +
> > +&iomuxc {
> > + pinctrl_uart2_bt: uart2grp_bt {
> > + fsl,pins = <
> > + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX
> > 0x17059
> > + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX
> > 0x17059
> > + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS
> > 0x17059
> > + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS
> > 0x17059
> > + >;
> > + };
> > +
> > + pinctrl_bt: btgrp {
> > + fsl,pins = <
> > + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3
> > 031 /* BT ENABLE */
> > + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x3
> > 031 /* HOST WAKEUP */
> > + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x3
> > 031 /* DEV WAKEUP */
> > + >;
> > + };
> > +
> > + pinctrl_usdhc2_wl: usdhc2grp_wl {
> > + fsl,pins = <
> > + MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x10051
> > + MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x10061
> > + MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x10051
> > + MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x10051
> > + MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x10051
> > + MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x10051
> > + >;
> > + };
> > +
> > + pinctrl_wl: wlgrp {
> > + fsl,pins = <
> > + /* WLAN ENABLE */
> > + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031
> > + >;
> > + };
> > +};
> > +
> > +&uart2 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_uart2_bt &pinctrl_bt>;
> > + uart-has-rtscts;
> > + status = "disabled";
> > +
> > + bluetooth {
> > + compatible = "brcm,bcm43438-bt";
> > + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
> > + device-wakeup-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
> > + host-wakeup-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
> > + };
> > +};
> > +
> > +&usdhc2 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_usdhc2_wl>;
> > + vmmc-supply = <®_wl_en>;
> > + bus-width = <4>;
> > + non-removable;
> > + no-1-8-v;
> > + status = "disabled";
> > +
> > + brmcf: wifi@1 {
> > + compatible = "brcm,bcm4329-fmac";
> > + };
> > +};
> > diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
> > b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
> > index c8d3eff9ed4b..1d7362b5ac91 100644
> > --- a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
> > +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
> > @@ -10,6 +10,7 @@
> > #include "imx6ull-phytec-segin.dtsi"
> > #include "imx6ull-phytec-segin-peb-eval-01.dtsi"
> > #include "imx6ull-phytec-segin-peb-av-02.dtsi"
> > +#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi"
> >
> > / {
> > model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with
> > NAND";
> > diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
> > b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
> > index e168494e0a6d..4bcbae024d8d 100644
> > --- a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
> > +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
> > @@ -9,6 +9,7 @@
> > #include "imx6ull-phytec-phycore-som.dtsi"
> > #include "imx6ull-phytec-segin.dtsi"
> > #include "imx6ull-phytec-segin-peb-eval-01.dtsi"
> > +#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi"
> >
> > / {
> > model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with
> > NAND";
> > diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-
> > 05.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi
> > new file mode 100644
> > index 000000000000..df25814a3371
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi
> > @@ -0,0 +1,19 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright (C) 2021 PHYTEC Messtechnik GmbH
> > + * Author: Yunus Bas <y.bas@phytec.de>
> > + */
> > +
> > +#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi"
> > +
> > +&iomuxc {
> > + /delete-node/ wlgrp;
> > +};
> > +
> > +&iomuxc_snvs {
> > + pinctrl_wl: wlgrp {
> > + fsl,pins = <
> > + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3
> > 031
> > + >;
> > + };
> > +};
> > --
> > 2.25.1
> >
next prev parent reply other threads:[~2021-12-13 12:21 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-30 8:53 [PATCH 1/3] ARM: dts: imx6qdl: phytec: Add support for optional PEB-EVAL-01 board Yunus Bas
2021-11-30 8:53 ` [PATCH 2/3] ARM: dts: imx6qdl: phytec: Add support for optional PEB-AV-02 LCD adapter Yunus Bas
2021-12-06 2:49 ` Shawn Guo
2021-12-13 11:40 ` Yunus Bas
2021-11-30 8:53 ` [PATCH 3/3] ARM: dts: imx6: phytec: Add PEB-WLBT-05 support Yunus Bas
2021-12-06 2:57 ` Shawn Guo
2021-12-13 12:21 ` Yunus Bas [this message]
2021-12-06 2:44 ` [PATCH 1/3] ARM: dts: imx6qdl: phytec: Add support for optional PEB-EVAL-01 board Shawn Guo
2021-12-13 11:34 ` Yunus Bas
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