[PATCH 0/3] ARM: dts: BCM5310x switch support

[PATCH 0/3] ARM: dts: BCM5310x switch support

[Florian Fainelli]

Hi all,

This patch series adds the Device Tree changes needed to enable the
Switch Register Access Block found on Broadcom BCM5301x SoCs.

First patch adds the SRAB block and the GMAC as child nodes of the BCMA
bus so we get proper device_node/struct device parenting. The second patch
defines the SRAB interrupts, and the last one defines the switch ports layouts
according to the new DSA binding accepted in net-next:

https://git.kernel.org/cgit/linux/kernel/git/davem/net-next.git/commit/?id=8c5ad1d6179df31eea1b736c88296db6e3ffd25d

The B53 driver binding is defined here:

https://git.kernel.org/cgit/linux/kernel/git/davem/net-next.git/diff/Documentation/devicetree/bindings/net/dsa/b53.txt?id=967dd82ffc52e9d8ea0defde094f9a39a3f4eeed

Florian Fainelli (3):
  ARM: dts: Enable SRAB switch and GMACs on 5301x DTS
  ARM: dts: BCM5301X: Add SRAB interrupts
  ARM: dts: BCM5310x: Enable switch ports on SmartRG SR400AC

 arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 40 +++++++++++++++++++++++++
 arch/arm/boot/dts/bcm5301x.dtsi               | 42 +++++++++++++++++++++++++++
 2 files changed, 82 insertions(+)

-- 
2.7.4

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[PATCH 1/3] ARM: dts: Enable SRAB switch and GMACs on 5301x DTS

[Florian Fainelli]

Add the Switch Register Access Block which is a special piece of
hardware allowing us to perform indirect read/writes towards the
integrated BCM5301X Ethernet switch.

We also add the 4 Gigabit MAC Device Tree nodes within the brcm,bus-axi
bus node to get proper binding between the BCMA instantiated core and
the Device Tree nodes. We will need that to be able to reference
Ethernet Device Tree nodes in a future patch adding the switch ports
layout.

Signed-off-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/bcm5301x.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 7d4d29bf0ed3..9fb565841004 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -239,6 +239,22 @@
 				status = "disabled";
 			};
 		};
+
+		gmac0: ethernet@24000 {
+			reg = <0x24000 0x800>;
+		};
+
+		gmac1: ethernet@25000 {
+			reg = <0x25000 0x800>;
+		};
+
+		gmac2: ethernet@26000 {
+			reg = <0x26000 0x800>;
+		};
+
+		gmac3: ethernet@27000 {
+			reg = <0x27000 0x800>;
+		};
 	};
 
 	lcpll0: lcpll0@1800c100 {
@@ -260,6 +276,17 @@
 				     "sata2";
 	};
 
+	srab: srab@18007000 {
+		compatible = "brcm,bcm5301x-srab";
+		reg = <0x18007000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		/* ports are defined in board DTS */
+	};
+
 	nand: nand@18028000 {
 		compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
 		reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
-- 
2.7.4

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[PATCH 2/3] ARM: dts: BCM5301X: Add SRAB interrupts

[Florian Fainelli]

Add interrupt mapping for the Switch Register Access Block. Only 12
interrupts are usable at the moment even though up to 32 are dedicated
to the SRAB.

Signed-off-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/bcm5301x.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 9fb565841004..a20ebd2ac9a2 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -153,6 +153,21 @@
 			/* ChipCommon */
 			<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 
+			/* Switch Register Access Block */
+			<0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+			<0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+
 			/* PCIe Controller 0 */
 			<0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 			<0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
-- 
2.7.4

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[PATCH 3/3] ARM: dts: BCM5310x: Enable switch ports on SmartRG SR400AC

[Florian Fainelli]

Define the port mapping for the SmartRG SR400ACE device.

Signed-off-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 40 +++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
index 8b0c440b2e71..c219d33496cc 100644
--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
+++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
@@ -126,3 +126,43 @@
 &spi_nor {
 	status = "okay";
 };
+
+&srab {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		switch0port0: port@0 {
+			reg = <0>;
+			label = "lan4";
+		};
+
+		switch0port1: port@1 {
+			reg = <1>;
+			label = "lan3";
+		};
+
+		switch0port2: port@2 {
+			reg = <2>;
+			label = "lan2";
+		};
+
+		switch0port3: port@3 {
+			reg = <3>;
+			label = "lan1";
+		};
+
+		switch0port4: port@4 {
+			reg = <4>;
+			label = "wan";
+		};
+
+		switch0port5: port@5 {
+			reg = <5>;
+			label = "cpu";
+			ethernet = <&gmac0>;
+		};
+	};
+};
-- 
2.7.4

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Re: [PATCH 3/3] ARM: dts: BCM5310x: Enable switch ports on SmartRG SR400AC

[Andrew Lunn]

On Fri, Jun 10, 2016 at 11:35:56AM -0700, Florian Fainelli wrote:
> Define the port mapping for the SmartRG SR400ACE device.
> 
> Signed-off-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 40 +++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
> index 8b0c440b2e71..c219d33496cc 100644
> --- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
> +++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
> @@ -126,3 +126,43 @@
>  &spi_nor {
>  	status = "okay";
>  };
> +
> +&srab {
> +	status = "okay";
> +
> +	ports {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		switch0port0: port@0 {

Hi Florian

You don't need the labels, since you don't have any phandles pointing
at them.

Other than that, great to see a board using the new switch driver.

Reviewed-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>

    Andrew
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Re: [PATCH 0/3] ARM: dts: BCM5310x switch support

[Florian Fainelli]

On 06/10/2016 11:35 AM, Florian Fainelli wrote:
> Hi all,
> 
> This patch series adds the Device Tree changes needed to enable the
> Switch Register Access Block found on Broadcom BCM5301x SoCs.
> 
> First patch adds the SRAB block and the GMAC as child nodes of the BCMA
> bus so we get proper device_node/struct device parenting. The second patch
> defines the SRAB interrupts, and the last one defines the switch ports layouts
> according to the new DSA binding accepted in net-next:
> 
> https://git.kernel.org/cgit/linux/kernel/git/davem/net-next.git/commit/?id=8c5ad1d6179df31eea1b736c88296db6e3ffd25d
> 
> The B53 driver binding is defined here:
> 
> https://git.kernel.org/cgit/linux/kernel/git/davem/net-next.git/diff/Documentation/devicetree/bindings/net/dsa/b53.txt?id=967dd82ffc52e9d8ea0defde094f9a39a3f4eeed
> 
> Florian Fainelli (3):
>   ARM: dts: Enable SRAB switch and GMACs on 5301x DTS
>   ARM: dts: BCM5301X: Add SRAB interrupts
>   ARM: dts: BCM5310x: Enable switch ports on SmartRG SR400AC

Applied with Andrew's Reviewed-by tag and removed the labels in patch 3,
thanks
-- 
Florian