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From: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Po Liu <po.liu-3arQi8VN3Tc@public.gmane.org>
Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Roy Zang <roy.zang-3arQi8VN3Tc@public.gmane.org>,
	Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>,
	Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>,
	Stuart Yoder <stuart.yoder-3arQi8VN3Tc@public.gmane.org>,
	Yang-Leo Li <leoyang.li-3arQi8VN3Tc@public.gmane.org>,
	Minghuan Lian <minghuan.lian-3arQi8VN3Tc@public.gmane.org>,
	Murali Karicheri <m-karicheri2-l0cyMroinI0@public.gmane.org>,
	Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>,
	Mingkai Hu <mingkai.hu-3arQi8VN3Tc@public.gmane.org>
Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode
Date: Sun, 18 Sep 2016 08:52:12 +0800	[thread overview]
Message-ID: <20160918005212.GF15478@tiger> (raw)
In-Reply-To: <1473741659-17618-3-git-send-email-po.liu-3arQi8VN3Tc@public.gmane.org>

On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote:
> On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> maybe there is interrupt line for aer pme etc. Search the interrupt
> number in the fdt file. Then fixup the dev->irq with it.
> 
> Signed-off-by: Po Liu <po.liu-3arQi8VN3Tc@public.gmane.org>

Will the new kernel work with existing/old DTB?  I'm trying to
understand the dependency between driver and DTS changes.

Shawn

> ---
> changes for v5:
> 	- Add clear 'aer' interrup-names description
> 
>  .../devicetree/bindings/pci/layerscape-pci.txt     | 11 +++++---
>  drivers/pci/pcie/portdrv_core.c                    | 31 +++++++++++++++++++---
>  2 files changed, 35 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index 41e9f55..101d0a7 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -18,8 +18,10 @@ Required properties:
>  - reg: base addresses and lengths of the PCIe controller
>  - interrupts: A list of interrupt outputs of the controller. Must contain an
>    entry for each entry in the interrupt-names property.
> -- interrupt-names: Must include the following entries:
> -  "intr": The interrupt that is asserted for controller interrupts
> +- interrupt-names: It may be include the following entries:
> +  "aer": The interrupt that is asserted for aer interrupt
> +  "pme": The interrupt that is asserted for pme interrupt
> +  ......
>  - fsl,pcie-scfg: Must include two entries.
>    The first entry must be a link to the SCFG device node
>    The second entry must be '0' or '1' based on physical PCIe controller index.
> @@ -35,8 +37,9 @@ Example:
>  		reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
>  		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
>  		reg-names = "regs", "config";
> -		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> -		interrupt-names = "intr";
> +		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, /* aer interrupt */
> +			<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* pme interrupt */
> +		interrupt-names = "aer", "pme";
>  		fsl,pcie-scfg = <&scfg 0>;
>  		#address-cells = <3>;
>  		#size-cells = <2>;
> diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
> index e9270b4..7c4943d 100644
> --- a/drivers/pci/pcie/portdrv_core.c
> +++ b/drivers/pci/pcie/portdrv_core.c
> @@ -16,6 +16,7 @@
>  #include <linux/slab.h>
>  #include <linux/pcieport_if.h>
>  #include <linux/aer.h>
> +#include <linux/of_irq.h>
>  
>  #include "../pci.h"
>  #include "portdrv.h"
> @@ -200,6 +201,28 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
>  static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
>  {
>  	int i, irq = -1;
> +	int ret;
> +	struct device_node *np = NULL;
> +
> +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> +		irqs[i] = 0;
> +
> +	if (dev->bus->dev.of_node)
> +		np = dev->bus->dev.of_node;
> +
> +	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> +	 * request irq for aer
> +	 */
> +	if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
> +			(mask & PCIE_PORT_SERVICE_PME)) {
> +		ret = of_irq_get_byname(np, "aer");
> +		if (ret > 0) {
> +			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
> +			if (dev->irq)
> +				irq = dev->irq;
> +			goto no_msi;
> +		}
> +	}
>  
>  	/*
>  	 * If MSI cannot be used for PCIe PME or hotplug, we have to use
> @@ -225,11 +248,13 @@ static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
>  		irq = dev->irq;
>  
>   no_msi:
> -	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> -		irqs[i] = irq;
> +	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
> +		if (!irqs[i])
> +			irqs[i] = irq;
> +	}
>  	irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
>  
> -	if (irq < 0)
> +	if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
>  		return -ENODEV;
>  	return 0;
>  }
> -- 
> 2.1.0.27.g96db324
> 
> 
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  parent reply	other threads:[~2016-09-18  0:52 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-26  6:00 [PATCH 2/2] aer: add support aer interrupt with none MSI/MSI-X/INTx mode Po Liu
2016-06-02  3:48 ` Bjorn Helgaas
2016-06-02  5:01   ` Po Liu
2016-06-02 13:55     ` Bjorn Helgaas
2016-06-02 15:37       ` Murali Karicheri
2016-06-03  4:09         ` Bjorn Helgaas
2016-06-03 17:31           ` Murali Karicheri
2016-06-04  3:48             ` Bjorn Helgaas
2016-06-06  7:32               ` Po Liu
2016-06-06 14:01                 ` Murali Karicheri
2016-06-06 18:10                   ` Bjorn Helgaas
2016-06-07 10:07                     ` Po Liu
2016-06-07 22:46                       ` Bjorn Helgaas
2016-06-08  4:56                         ` Po Liu
2016-06-14  6:12 ` [PATCH v2 1/2] nxp/dts: add pcie aer interrupt-name property in the dts Po Liu
2016-06-14  6:12   ` [PATCH v2 2/2] pci/aer: interrupt fixup in the quirk Po Liu
2016-06-16 13:54     ` Bjorn Helgaas
2016-06-17  3:30       ` Po Liu
2016-07-01  8:46       ` Po Liu
2016-06-14  8:24 ` [PATCH v3 1/2] nxp/dts: add pcie aer interrupt-name property in the dts Po Liu
2016-06-14  8:24   ` [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk Po Liu
2016-06-23  5:43     ` Dongdong Liu
2016-07-01  8:40       ` Po Liu
2016-07-04  8:44     ` Dongdong Liu
2016-07-05  3:03       ` Po Liu
2016-07-06  8:38         ` Dongdong Liu
     [not found]     ` <1465892645-32381-2-git-send-email-po.liu-3arQi8VN3Tc@public.gmane.org>
2016-07-29 22:41       ` Bjorn Helgaas
2016-08-22 10:09         ` Po Liu
2016-09-20 20:47           ` Bjorn Helgaas
2016-09-21  6:51             ` Po Liu
2016-09-21 21:53               ` Bjorn Helgaas
2016-08-31  6:37     ` [PATCH v4 1/2] nxp/dts: add pcie aer interrupt-name property in the dts Po Liu
2016-08-31  6:37       ` [PATCH v4 2/2] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode Po Liu
2016-09-02 15:17         ` Rob Herring
2016-09-05  6:05           ` Po Liu
2016-09-13  4:40         ` [PATCH v5 1/3] arm/dts: add pcie aer interrupt-name property in the dts Po Liu
2016-09-13  4:40           ` [PATCH v5 2/3] arm64/dts: " Po Liu
2016-09-13  4:40           ` [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode Po Liu
     [not found]             ` <1473741659-17618-3-git-send-email-po.liu-3arQi8VN3Tc@public.gmane.org>
2016-09-18  0:52               ` Shawn Guo [this message]
2016-09-18  3:37                 ` Po Liu
     [not found]                   ` <VI1PR0401MB1709F91B0C1EB6C80D741E4492F50-9IDQY6o3qQhWumToEB7uiI3W/0Ik+aLCnBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2016-09-20 12:39                     ` Shawn Guo
2016-09-21  6:54                       ` Po Liu
2016-09-30 22:13                         ` Shawn Guo
2016-09-23 13:06                   ` Rob Herring
2016-09-26  8:25                     ` Po Liu
2016-09-21 22:37               ` Bjorn Helgaas
2016-09-22  2:53                 ` Po Liu
2016-09-30  9:11               ` [PATCH v6 1/3] arm/dts-ls1021: add pcie aer/pme interrupt-name property in the dts Po Liu
2016-09-30  9:11                 ` [PATCH v6 2/3] arm64/dts-ls1043-ls2080: " Po Liu
2016-09-30  9:11                 ` [PATCH v6 3/3] pci:add support aer/pme interrupts with none MSI/MSI-X/INTx mode Po Liu
     [not found]                   ` <1475226697-7709-3-git-send-email-po.liu-3arQi8VN3Tc@public.gmane.org>
2016-10-08 20:49                     ` Rob Herring
2016-10-09  2:47                       ` Po Liu
2016-09-05  2:25       ` [PATCH v4 1/2] nxp/dts: add pcie aer interrupt-name property in the dts Shawn Guo
     [not found]       ` <1472625442-23309-1-git-send-email-po.liu-3arQi8VN3Tc@public.gmane.org>
2016-09-12 22:13         ` Bjorn Helgaas
2016-09-13  3:02           ` Po Liu
2016-06-16  0:36   ` [PATCH v3 " Shawn Guo
2016-06-16 10:50     ` Po Liu
2016-06-16 22:19   ` Rob Herring

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