[PATCH v3 0/4] Add CPU Frequency scaling support on Armada 37xx

[PATCH v3 0/4] Add CPU Frequency scaling support on Armada 37xx

[Gregory CLEMENT]

Hi,

This is the third version of a series adding the CPU Frequency support
on Armada 37xx using DVFS. It is based on the initial work of Evan
Wang and Victor Gu.

As requested all the patches not directly related to the Armada 37xx
support had been sent in separate series.

The only other changes is replacing tab by space in the define as it
should have be already done in the v2.

The last patch is for arm-soc the arm-soc subsystem through mvebu and
update the device tree to support the CPU frequency scaling.

An update on the CPU clock driver is needed in order to take into
account the DVFS setting. It's the purpose of an other series already
sent, but is no dependencies between the series (for building or at
runtime).

Thanks,

Gregory

Changelog:

v1 -> v2:

 - using syscon instead of nb_pm for the binding of the North bridge
   power management unit: reported by Rob Herring

 - fix sorting inside the big LITTLE section for the Kconfig: reported
   by Viresh Kumar

 - fix the bogus freq calculation in armada37xx_cpufreq_driver_init,
   bug reported by Andre Heider

 - use dev_pm_opp_remove() on the previous opp if dev_pm_opp_add()
   failed, reported by Viresh Kumar

 - add the Tested-by flag from Andre Heider on "cpufreq: Add DVFS
   support for Armada 37xx" patch

v2 -> v3:

 - move patches "cpufreq: ARM: sort the Kconfig menu", " cpufreq:
   sort the drivers in ARM part", "cpufreq: mvebu: Use
   dev_pm_opp_remove()" in separate series

- add reviewed-by and acked-by flags on the commits

- use space instead of tab in the #define in the armada-37xx-cpufreq.c file.

Gregory CLEMENT (4):
  dt-bindings: marvell: Add documentation for the North Bridge PM on
    Armada 37xx
  MAINTAINERS: add new entries for Armada 37xx cpufreq driver
  cpufreq: Add DVFS support for Armada 37xx
  arm64: dts: marvell: armada-37xx: add nodes allowing cpufreq support

 .../bindings/arm/marvell/armada-37xx.txt           |  19 ++
 MAINTAINERS                                        |   1 +
 arch/arm64/boot/dts/marvell/armada-372x.dtsi       |   1 +
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi       |   7 +
 drivers/cpufreq/Kconfig.arm                        |   7 +
 drivers/cpufreq/Makefile                           |   1 +
 drivers/cpufreq/armada-37xx-cpufreq.c              | 241 +++++++++++++++++++++
 7 files changed, 277 insertions(+)
 create mode 100644 drivers/cpufreq/armada-37xx-cpufreq.c

-- 
2.15.1

[PATCH v3 1/4] dt-bindings: marvell: Add documentation for the North Bridge PM on Armada 37xx

[Gregory CLEMENT]

Extend the documentation of the Armada 37xx SoC with the the North
Bridge Power Management component.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 .../devicetree/bindings/arm/marvell/armada-37xx.txt   | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
index 51336e5fc761..35c3c3460d17 100644
--- a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
@@ -14,3 +14,22 @@ following property before the previous one:
 Example:
 
 compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710";
+
+
+Power management
+----------------
+
+For power management (particularly DVFS and AVS), the North Bridge
+Power Management component is needed:
+
+Required properties:
+- compatible     : should contain "marvell,armada-3700-nb-pm", "syscon";
+- reg            : the register start and length for the North Bridge
+		    Power Management
+
+Example:
+
+nb_pm: syscon@14000 {
+	compatible = "marvell,armada-3700-nb-pm", "syscon";
+	reg = <0x14000 0x60>;
+}
-- 
2.15.1

[PATCH v3 2/4] MAINTAINERS: add new entries for Armada 37xx cpufreq driver

[Gregory CLEMENT]

This new driver belongs to the mvebu family, update the MAINTAINER file
to document it.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index aa71ab52fd76..98dcee849481 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1582,6 +1582,7 @@ F:	arch/arm/boot/dts/kirkwood*
 F:	arch/arm/configs/mvebu_*_defconfig
 F:	arch/arm/mach-mvebu/
 F:	arch/arm64/boot/dts/marvell/armada*
+F:	drivers/cpufreq/armada-37xx-cpufreq.c
 F:	drivers/cpufreq/mvebu-cpufreq.c
 F:	drivers/irqchip/irq-armada-370-xp.c
 F:	drivers/irqchip/irq-mvebu-*
-- 
2.15.1

[PATCH v3 3/4] cpufreq: Add DVFS support for Armada 37xx

[Gregory CLEMENT]

This patch adds DVFS support for the Armada 37xx SoCs

There are up to four CPU frequency loads for Armada 37xx controlled by
the hardware.

This driver associates the CPU load level to a frequency, then the
hardware will switch while selecting a load level.

The hardware also can associate a voltage for each level (AVS support)
but it is not yet supported

Tested-by: Andre Heider <a.heider@gmail.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/cpufreq/Kconfig.arm           |   7 +
 drivers/cpufreq/Makefile              |   1 +
 drivers/cpufreq/armada-37xx-cpufreq.c | 241 ++++++++++++++++++++++++++++++++++
 3 files changed, 249 insertions(+)
 create mode 100644 drivers/cpufreq/armada-37xx-cpufreq.c

diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index beb8826afbb1..3a88e33b0cfe 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -18,6 +18,13 @@ config ACPI_CPPC_CPUFREQ
 
 	  If in doubt, say N.
 
+config ARM_ARMADA_37XX_CPUFREQ
+	tristate "Armada 37xx CPUFreq support"
+	depends on ARCH_MVEBU
+	help
+	  This adds the CPUFreq driver support for Marvell Armada 37xx SoCs.
+	  The Armada 37xx PMU supports 4 frequency and VDD levels.
+
 # big LITTLE core layer and glue drivers
 config ARM_BIG_LITTLE_CPUFREQ
 	tristate "Generic ARM big LITTLE CPUfreq driver"
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index d762e76887e7..e07715ce8844 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_ARM_BIG_LITTLE_CPUFREQ)	+= arm_big_little.o
 # LITTLE drivers, so that it is probed last.
 obj-$(CONFIG_ARM_DT_BL_CPUFREQ)		+= arm_big_little_dt.o
 
+obj-$(CONFIG_ARM_ARMADA_37XX_CPUFREQ)	+= armada-37xx-cpufreq.o
 obj-$(CONFIG_ARM_BRCMSTB_AVS_CPUFREQ)	+= brcmstb-avs-cpufreq.o
 obj-$(CONFIG_ACPI_CPPC_CPUFREQ)		+= cppc_cpufreq.o
 obj-$(CONFIG_ARCH_DAVINCI)		+= davinci-cpufreq.o
diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
new file mode 100644
index 000000000000..b819e5159a4b
--- /dev/null
+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * CPU frequency scaling support for Armada 37xx platform.
+ *
+ * Copyright (C) 2017 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/cpu.h>
+#include <linux/cpufreq.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+/* Power management in North Bridge register set */
+#define ARMADA_37XX_NB_L0L1	0x18
+#define ARMADA_37XX_NB_L2L3	0x1C
+#define  ARMADA_37XX_NB_TBG_DIV_OFF	13
+#define  ARMADA_37XX_NB_TBG_DIV_MASK	0x7
+#define  ARMADA_37XX_NB_CLK_SEL_OFF	11
+#define  ARMADA_37XX_NB_CLK_SEL_MASK	0x1
+#define  ARMADA_37XX_NB_CLK_SEL_TBG      0x1
+#define  ARMADA_37XX_NB_TBG_SEL_OFF	9
+#define  ARMADA_37XX_NB_TBG_SEL_MASK	0x3
+#define  ARMADA_37XX_NB_VDD_SEL_OFF	6
+#define  ARMADA_37XX_NB_VDD_SEL_MASK	0x3
+#define  ARMADA_37XX_NB_CONFIG_SHIFT	16
+#define ARMADA_37XX_NB_DYN_MOD	0x24
+#define  ARMADA_37XX_NB_CLK_SEL_EN	BIT(26)
+#define  ARMADA_37XX_NB_TBG_EN		BIT(28)
+#define  ARMADA_37XX_NB_DIV_EN		BIT(29)
+#define  ARMADA_37XX_NB_VDD_EN		BIT(30)
+#define  ARMADA_37XX_NB_DFS_EN		BIT(31)
+#define ARMADA_37XX_NB_CPU_LOAD 0x30
+#define  ARMADA_37XX_NB_CPU_LOAD_MASK	0x3
+#define  ARMADA_37XX_DVFS_LOAD_0	0
+#define  ARMADA_37XX_DVFS_LOAD_1	1
+#define  ARMADA_37XX_DVFS_LOAD_2	2
+#define  ARMADA_37XX_DVFS_LOAD_3	3
+
+/*
+ * On Armada 37xx the Power management manages 4 level of CPU load,
+ * each level can be associated with a CPU clock source, a CPU
+ * divider, a VDD level, etc...
+ */
+#define LOAD_LEVEL_NR	4
+
+struct armada_37xx_dvfs {
+	u32 cpu_freq_max;
+	u8 divider[LOAD_LEVEL_NR];
+};
+
+static struct armada_37xx_dvfs armada_37xx_dvfs[] = {
+	{.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} },
+	{.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
+	{.cpu_freq_max = 800*1000*1000,  .divider = {1, 2, 3, 4} },
+	{.cpu_freq_max = 600*1000*1000,  .divider = {2, 4, 5, 6} },
+};
+
+static struct armada_37xx_dvfs *armada_37xx_cpu_freq_info_get(u32 freq)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(armada_37xx_dvfs); i++) {
+		if (freq == armada_37xx_dvfs[i].cpu_freq_max)
+			return &armada_37xx_dvfs[i];
+	}
+
+	pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000);
+	return NULL;
+}
+
+/*
+ * Setup the four level managed by the hardware. Once the four level
+ * will be configured then the DVFS will be enabled.
+ */
+static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
+						 struct clk *clk, u8 *divider)
+{
+	int load_lvl;
+	struct clk *parent;
+
+	for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
+		unsigned int reg, mask,  val, offset = 0;
+
+		if (load_lvl <= ARMADA_37XX_DVFS_LOAD_1)
+			reg = ARMADA_37XX_NB_L0L1;
+		else
+			reg = ARMADA_37XX_NB_L2L3;
+
+		if (load_lvl ==  ARMADA_37XX_DVFS_LOAD_0 ||
+		    load_lvl ==  ARMADA_37XX_DVFS_LOAD_2)
+			offset += ARMADA_37XX_NB_CONFIG_SHIFT;
+
+		/* Set cpu clock source, for all the level we use TBG */
+		val = ARMADA_37XX_NB_CLK_SEL_TBG << ARMADA_37XX_NB_CLK_SEL_OFF;
+		mask = (ARMADA_37XX_NB_CLK_SEL_MASK
+			<< ARMADA_37XX_NB_CLK_SEL_OFF);
+
+		/*
+		 * Set cpu divider based on the pre-computed array in
+		 * order to have balanced step.
+		 */
+		val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF;
+		mask |= (ARMADA_37XX_NB_TBG_DIV_MASK
+			<< ARMADA_37XX_NB_TBG_DIV_OFF);
+
+		/* Set VDD divider which is actually the load level. */
+		val |= load_lvl << ARMADA_37XX_NB_VDD_SEL_OFF;
+		mask |= (ARMADA_37XX_NB_VDD_SEL_MASK
+			<< ARMADA_37XX_NB_VDD_SEL_OFF);
+
+		val <<= offset;
+		mask <<= offset;
+
+		regmap_update_bits(base, reg, mask, val);
+	}
+
+	/*
+	 * Set cpu clock source, for all the level we keep the same
+	 * clock source that the one already configured. For this one
+	 * we need to use the clock framework
+	 */
+	parent = clk_get_parent(clk);
+	clk_set_parent(clk, parent);
+}
+
+static void __init armada37xx_cpufreq_disable_dvfs(struct regmap *base)
+{
+	unsigned int reg = ARMADA_37XX_NB_DYN_MOD,
+		mask = ARMADA_37XX_NB_DFS_EN;
+
+	regmap_update_bits(base, reg, mask, 0);
+}
+
+static void __init armada37xx_cpufreq_enable_dvfs(struct regmap *base)
+{
+	unsigned int val, reg = ARMADA_37XX_NB_CPU_LOAD,
+		mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
+
+	/* Start with the highest load (0) */
+	val = ARMADA_37XX_DVFS_LOAD_0;
+	regmap_update_bits(base, reg, mask, val);
+
+	/* Now enable DVFS for the CPUs */
+	reg = ARMADA_37XX_NB_DYN_MOD;
+	mask =	ARMADA_37XX_NB_CLK_SEL_EN | ARMADA_37XX_NB_TBG_EN |
+		ARMADA_37XX_NB_DIV_EN | ARMADA_37XX_NB_VDD_EN |
+		ARMADA_37XX_NB_DFS_EN;
+
+	regmap_update_bits(base, reg, mask, mask);
+}
+
+static int __init armada37xx_cpufreq_driver_init(void)
+{
+	struct armada_37xx_dvfs *dvfs;
+	struct platform_device *pdev;
+	unsigned int cur_frequency;
+	struct regmap *nb_pm_base;
+	struct device *cpu_dev;
+	int load_lvl, ret;
+	struct clk *clk;
+
+	nb_pm_base =
+		syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
+
+	if (IS_ERR(nb_pm_base))
+		return -ENODEV;
+
+	/* Before doing any configuration on the DVFS first, disable it */
+	armada37xx_cpufreq_disable_dvfs(nb_pm_base);
+
+	/*
+	 * On CPU 0 register the operating points supported (which are
+	 * the nominal CPU frequency and full integer divisions of
+	 * it).
+	 */
+	cpu_dev = get_cpu_device(0);
+	if (!cpu_dev) {
+		dev_err(cpu_dev, "Cannot get CPU\n");
+		return -ENODEV;
+	}
+
+	clk = clk_get(cpu_dev, 0);
+	if (IS_ERR(clk)) {
+		dev_err(cpu_dev, "Cannot get clock for CPU0\n");
+		return PTR_ERR(clk);
+	}
+
+	/* Get nominal (current) CPU frequency */
+	cur_frequency = clk_get_rate(clk);
+	if (!cur_frequency) {
+		dev_err(cpu_dev, "Failed to get clock rate for CPU\n");
+		return -EINVAL;
+	}
+
+	dvfs = armada_37xx_cpu_freq_info_get(cur_frequency);
+	if (!dvfs)
+		return -EINVAL;
+
+	armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider);
+
+	for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
+	     load_lvl++) {
+		unsigned long freq = cur_frequency / dvfs->divider[load_lvl];
+
+		ret = dev_pm_opp_add(cpu_dev, freq, 0);
+		if (ret) {
+			/*  clean-up the already added opp before leaving */
+			while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) {
+				freq = cur_frequency / dvfs->divider[load_lvl];
+				dev_pm_opp_remove(cpu_dev, freq);
+			}
+			return ret;
+		}
+	}
+
+	/* Now that everything is setup, enable the DVFS at hardware level */
+	armada37xx_cpufreq_enable_dvfs(nb_pm_base);
+
+	pdev = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
+
+	return PTR_ERR_OR_ZERO(pdev);
+}
+/* late_initcall, to guarantee the driver is loaded after A37xx clock driver */
+late_initcall(armada37xx_cpufreq_driver_init);
+
+MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
+MODULE_DESCRIPTION("Armada 37xx cpufreq driver");
+MODULE_LICENSE("GPL");
-- 
2.15.1

[PATCH v3 4/4] arm64: dts: marvell: armada-37xx: add nodes allowing cpufreq support

[Gregory CLEMENT]

In order to be able to use cpu freq, we need to associate a clock to each
CPU and to expose the power management registers.

Signed-off-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 arch/arm64/boot/dts/marvell/armada-372x.dtsi | 1 +
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 7 +++++++
 2 files changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-372x.dtsi b/arch/arm64/boot/dts/marvell/armada-372x.dtsi
index 59d7557d3b1b..2554e0baea6b 100644
--- a/arch/arm64/boot/dts/marvell/armada-372x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-372x.dtsi
@@ -56,6 +56,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a53","arm,armv8";
 			reg = <0x1>;
+			clocks = <&nb_periph_clk 16>;
 			enable-method = "psci";
 		};
 	};
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index 90c26d616a54..3056d7168e0b 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -65,6 +65,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0>;
+			clocks = <&nb_periph_clk 16>;
 			enable-method = "psci";
 		};
 	};
@@ -234,6 +235,12 @@
 				};
 			};
 
+			nb_pm: syscon@14000 {
+				compatible = "marvell,armada-3700-nb-pm",
+					     "syscon";
+				reg = <0x14000 0x60>;
+			};
+
 			pinctrl_sb: pinctrl@18800 {
 				compatible = "marvell,armada3710-sb-pinctrl",
 					     "syscon", "simple-mfd";
-- 
2.15.1

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Re: [PATCH v3 3/4] cpufreq: Add DVFS support for Armada 37xx

[Viresh Kumar]

I just searched for tabs and spaces in this patch and here are the observations.

On 13-12-17, 18:51, Gregory CLEMENT wrote:
> +/* Power management in North Bridge register set */
> +#define ARMADA_37XX_NB_L0L1	0x18

There is a single space after #define here, which is good.

> +#define ARMADA_37XX_NB_L2L3	0x1C
> +#define  ARMADA_37XX_NB_TBG_DIV_OFF	13

But here and at many places below you have two spaces after #define, which isn't
bad but isn't consistent as well.

> +#define  ARMADA_37XX_NB_TBG_DIV_MASK	0x7
> +#define  ARMADA_37XX_NB_CLK_SEL_OFF	11
> +#define  ARMADA_37XX_NB_CLK_SEL_MASK	0x1
> +#define  ARMADA_37XX_NB_CLK_SEL_TBG      0x1

You have used space instead of TAB after ARMADA_37XX_NB_CLK_SEL_TBG here, while
everywhere else we have tabs. Maybe its better to be consistent ?

> +#define  ARMADA_37XX_NB_TBG_SEL_OFF	9
> +#define  ARMADA_37XX_NB_TBG_SEL_MASK	0x3
> +#define  ARMADA_37XX_NB_VDD_SEL_OFF	6
> +#define  ARMADA_37XX_NB_VDD_SEL_MASK	0x3
> +#define  ARMADA_37XX_NB_CONFIG_SHIFT	16
> +#define ARMADA_37XX_NB_DYN_MOD	0x24
> +#define  ARMADA_37XX_NB_CLK_SEL_EN	BIT(26)
> +#define  ARMADA_37XX_NB_TBG_EN		BIT(28)
> +#define  ARMADA_37XX_NB_DIV_EN		BIT(29)
> +#define  ARMADA_37XX_NB_VDD_EN		BIT(30)
> +#define  ARMADA_37XX_NB_DFS_EN		BIT(31)
> +#define ARMADA_37XX_NB_CPU_LOAD 0x30
> +#define  ARMADA_37XX_NB_CPU_LOAD_MASK	0x3
> +#define  ARMADA_37XX_DVFS_LOAD_0	0
> +#define  ARMADA_37XX_DVFS_LOAD_1	1
> +#define  ARMADA_37XX_DVFS_LOAD_2	2
> +#define  ARMADA_37XX_DVFS_LOAD_3	3
> +
> +/*
> + * On Armada 37xx the Power management manages 4 level of CPU load,
> + * each level can be associated with a CPU clock source, a CPU
> + * divider, a VDD level, etc...
> + */
> +#define LOAD_LEVEL_NR	4
> +
> +struct armada_37xx_dvfs {
> +	u32 cpu_freq_max;
> +	u8 divider[LOAD_LEVEL_NR];
> +};
> +
> +static struct armada_37xx_dvfs armada_37xx_dvfs[] = {
> +	{.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} },
> +	{.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
> +	{.cpu_freq_max = 800*1000*1000,  .divider = {1, 2, 3, 4} },
> +	{.cpu_freq_max = 600*1000*1000,  .divider = {2, 4, 5, 6} },
> +};
> +
> +static struct armada_37xx_dvfs *armada_37xx_cpu_freq_info_get(u32 freq)
> +{
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(armada_37xx_dvfs); i++) {
> +		if (freq == armada_37xx_dvfs[i].cpu_freq_max)
> +			return &armada_37xx_dvfs[i];
> +	}
> +
> +	pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000);
> +	return NULL;
> +}
> +
> +/*
> + * Setup the four level managed by the hardware. Once the four level
> + * will be configured then the DVFS will be enabled.
> + */
> +static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
> +						 struct clk *clk, u8 *divider)
> +{
> +	int load_lvl;
> +	struct clk *parent;
> +
> +	for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
> +		unsigned int reg, mask,  val, offset = 0;

double space before "val".

> +
> +		if (load_lvl <= ARMADA_37XX_DVFS_LOAD_1)
> +			reg = ARMADA_37XX_NB_L0L1;
> +		else
> +			reg = ARMADA_37XX_NB_L2L3;
> +
> +		if (load_lvl ==  ARMADA_37XX_DVFS_LOAD_0 ||
> +		    load_lvl ==  ARMADA_37XX_DVFS_LOAD_2)

double spaces after ==

> +			offset += ARMADA_37XX_NB_CONFIG_SHIFT;
> +
> +		/* Set cpu clock source, for all the level we use TBG */
> +		val = ARMADA_37XX_NB_CLK_SEL_TBG << ARMADA_37XX_NB_CLK_SEL_OFF;
> +		mask = (ARMADA_37XX_NB_CLK_SEL_MASK
> +			<< ARMADA_37XX_NB_CLK_SEL_OFF);
> +
> +		/*
> +		 * Set cpu divider based on the pre-computed array in
> +		 * order to have balanced step.
> +		 */
> +		val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF;
> +		mask |= (ARMADA_37XX_NB_TBG_DIV_MASK
> +			<< ARMADA_37XX_NB_TBG_DIV_OFF);
> +
> +		/* Set VDD divider which is actually the load level. */
> +		val |= load_lvl << ARMADA_37XX_NB_VDD_SEL_OFF;
> +		mask |= (ARMADA_37XX_NB_VDD_SEL_MASK
> +			<< ARMADA_37XX_NB_VDD_SEL_OFF);
> +
> +		val <<= offset;
> +		mask <<= offset;
> +
> +		regmap_update_bits(base, reg, mask, val);
> +	}
> +
> +	/*
> +	 * Set cpu clock source, for all the level we keep the same
> +	 * clock source that the one already configured. For this one
> +	 * we need to use the clock framework
> +	 */
> +	parent = clk_get_parent(clk);
> +	clk_set_parent(clk, parent);
> +}
> +
> +static void __init armada37xx_cpufreq_disable_dvfs(struct regmap *base)
> +{
> +	unsigned int reg = ARMADA_37XX_NB_DYN_MOD,
> +		mask = ARMADA_37XX_NB_DFS_EN;
> +
> +	regmap_update_bits(base, reg, mask, 0);
> +}
> +
> +static void __init armada37xx_cpufreq_enable_dvfs(struct regmap *base)
> +{
> +	unsigned int val, reg = ARMADA_37XX_NB_CPU_LOAD,
> +		mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
> +
> +	/* Start with the highest load (0) */
> +	val = ARMADA_37XX_DVFS_LOAD_0;
> +	regmap_update_bits(base, reg, mask, val);
> +
> +	/* Now enable DVFS for the CPUs */
> +	reg = ARMADA_37XX_NB_DYN_MOD;
> +	mask =	ARMADA_37XX_NB_CLK_SEL_EN | ARMADA_37XX_NB_TBG_EN |
> +		ARMADA_37XX_NB_DIV_EN | ARMADA_37XX_NB_VDD_EN |
> +		ARMADA_37XX_NB_DFS_EN;
> +
> +	regmap_update_bits(base, reg, mask, mask);
> +}
> +
> +static int __init armada37xx_cpufreq_driver_init(void)
> +{
> +	struct armada_37xx_dvfs *dvfs;
> +	struct platform_device *pdev;
> +	unsigned int cur_frequency;
> +	struct regmap *nb_pm_base;
> +	struct device *cpu_dev;
> +	int load_lvl, ret;
> +	struct clk *clk;
> +
> +	nb_pm_base =
> +		syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
> +
> +	if (IS_ERR(nb_pm_base))
> +		return -ENODEV;
> +
> +	/* Before doing any configuration on the DVFS first, disable it */
> +	armada37xx_cpufreq_disable_dvfs(nb_pm_base);
> +
> +	/*
> +	 * On CPU 0 register the operating points supported (which are
> +	 * the nominal CPU frequency and full integer divisions of
> +	 * it).
> +	 */
> +	cpu_dev = get_cpu_device(0);
> +	if (!cpu_dev) {
> +		dev_err(cpu_dev, "Cannot get CPU\n");
> +		return -ENODEV;
> +	}
> +
> +	clk = clk_get(cpu_dev, 0);
> +	if (IS_ERR(clk)) {
> +		dev_err(cpu_dev, "Cannot get clock for CPU0\n");
> +		return PTR_ERR(clk);
> +	}
> +
> +	/* Get nominal (current) CPU frequency */
> +	cur_frequency = clk_get_rate(clk);
> +	if (!cur_frequency) {
> +		dev_err(cpu_dev, "Failed to get clock rate for CPU\n");
> +		return -EINVAL;
> +	}
> +
> +	dvfs = armada_37xx_cpu_freq_info_get(cur_frequency);
> +	if (!dvfs)
> +		return -EINVAL;
> +
> +	armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider);
> +
> +	for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
> +	     load_lvl++) {
> +		unsigned long freq = cur_frequency / dvfs->divider[load_lvl];
> +
> +		ret = dev_pm_opp_add(cpu_dev, freq, 0);
> +		if (ret) {
> +			/*  clean-up the already added opp before leaving */

Double space after /*

> +			while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) {
> +				freq = cur_frequency / dvfs->divider[load_lvl];
> +				dev_pm_opp_remove(cpu_dev, freq);
> +			}
> +			return ret;
> +		}
> +	}
> +
> +	/* Now that everything is setup, enable the DVFS at hardware level */
> +	armada37xx_cpufreq_enable_dvfs(nb_pm_base);
> +
> +	pdev = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
> +
> +	return PTR_ERR_OR_ZERO(pdev);
> +}
> +/* late_initcall, to guarantee the driver is loaded after A37xx clock driver */
> +late_initcall(armada37xx_cpufreq_driver_init);
> +
> +MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
> +MODULE_DESCRIPTION("Armada 37xx cpufreq driver");
> +MODULE_LICENSE("GPL");

I am not objecting to using double spaces at all these locations, its fine. Just
that I wanted to point it out in case it is not intentional.

-- 
viresh

Re: [PATCH v3 3/4] cpufreq: Add DVFS support for Armada 37xx

[Gregory CLEMENT]

Hi Viresh,
 
 On jeu., déc. 14 2017, Viresh Kumar <viresh.kumar@linaro.org> wrote:

> I just searched for tabs and spaces in this patch and here are the observations.
>
> On 13-12-17, 18:51, Gregory CLEMENT wrote:
>> +/* Power management in North Bridge register set */
>> +#define ARMADA_37XX_NB_L0L1	0x18
>
> There is a single space after #define here, which is good.
>
>> +#define ARMADA_37XX_NB_L2L3	0x1C
>> +#define  ARMADA_37XX_NB_TBG_DIV_OFF	13
>
> But here and at many places below you have two spaces after #define, which isn't
> bad but isn't consistent as well.

Actually from the beginning the idea was to make difference between the
define for the offset of the register and then the define for the value
related to this register.

Initially I used tab for this distinction, but then I though you
suggested to only use space to have a more compact view, so I used double
space.

I don't mind using double space or tab, but for me making distinction
between offset of the register and content of the register helps the
readability of the code.

>
>> +#define  ARMADA_37XX_NB_TBG_DIV_MASK	0x7
>> +#define  ARMADA_37XX_NB_CLK_SEL_OFF	11
>> +#define  ARMADA_37XX_NB_CLK_SEL_MASK	0x1
>> +#define  ARMADA_37XX_NB_CLK_SEL_TBG      0x1
>
> You have used space instead of TAB after ARMADA_37XX_NB_CLK_SEL_TBG here, while
> everywhere else we have tabs. Maybe its better to be consistent ?

It was a typo.

>
>> +#define  ARMADA_37XX_NB_TBG_SEL_OFF	9
>> +#define  ARMADA_37XX_NB_TBG_SEL_MASK	0x3
>> +#define  ARMADA_37XX_NB_VDD_SEL_OFF	6
>> +#define  ARMADA_37XX_NB_VDD_SEL_MASK	0x3
>> +#define  ARMADA_37XX_NB_CONFIG_SHIFT	16
>> +#define ARMADA_37XX_NB_DYN_MOD	0x24
>> +#define  ARMADA_37XX_NB_CLK_SEL_EN	BIT(26)
>> +#define  ARMADA_37XX_NB_TBG_EN		BIT(28)
>> +#define  ARMADA_37XX_NB_DIV_EN		BIT(29)
>> +#define  ARMADA_37XX_NB_VDD_EN		BIT(30)
>> +#define  ARMADA_37XX_NB_DFS_EN		BIT(31)
>> +#define ARMADA_37XX_NB_CPU_LOAD 0x30
>> +#define  ARMADA_37XX_NB_CPU_LOAD_MASK	0x3
>> +#define  ARMADA_37XX_DVFS_LOAD_0	0
>> +#define  ARMADA_37XX_DVFS_LOAD_1	1
>> +#define  ARMADA_37XX_DVFS_LOAD_2	2
>> +#define  ARMADA_37XX_DVFS_LOAD_3	3
>> +
>> +/*
>> + * On Armada 37xx the Power management manages 4 level of CPU load,
>> + * each level can be associated with a CPU clock source, a CPU
>> + * divider, a VDD level, etc...
>> + */
>> +#define LOAD_LEVEL_NR	4
>> +
>> +struct armada_37xx_dvfs {
>> +	u32 cpu_freq_max;
>> +	u8 divider[LOAD_LEVEL_NR];
>> +};
>> +
>> +static struct armada_37xx_dvfs armada_37xx_dvfs[] = {
>> +	{.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} },
>> +	{.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
>> +	{.cpu_freq_max = 800*1000*1000,  .divider = {1, 2, 3, 4} },
>> +	{.cpu_freq_max = 600*1000*1000,  .divider = {2, 4, 5, 6} },
>> +};
>> +
>> +static struct armada_37xx_dvfs *armada_37xx_cpu_freq_info_get(u32 freq)
>> +{
>> +	int i;
>> +
>> +	for (i = 0; i < ARRAY_SIZE(armada_37xx_dvfs); i++) {
>> +		if (freq == armada_37xx_dvfs[i].cpu_freq_max)
>> +			return &armada_37xx_dvfs[i];
>> +	}
>> +
>> +	pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000);
>> +	return NULL;
>> +}
>> +
>> +/*
>> + * Setup the four level managed by the hardware. Once the four level
>> + * will be configured then the DVFS will be enabled.
>> + */
>> +static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
>> +						 struct clk *clk, u8 *divider)
>> +{
>> +	int load_lvl;
>> +	struct clk *parent;
>> +
>> +	for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
>> +		unsigned int reg, mask,  val, offset = 0;
>
> double space before "val".
>

Typo

>> +
>> +		if (load_lvl <= ARMADA_37XX_DVFS_LOAD_1)
>> +			reg = ARMADA_37XX_NB_L0L1;
>> +		else
>> +			reg = ARMADA_37XX_NB_L2L3;
>> +
>> +		if (load_lvl ==  ARMADA_37XX_DVFS_LOAD_0 ||
>> +		    load_lvl ==  ARMADA_37XX_DVFS_LOAD_2)
>
> double spaces after ==

Typo

>
>> +			offset += ARMADA_37XX_NB_CONFIG_SHIFT;
>> +
>> +		/* Set cpu clock source, for all the level we use TBG */
>> +		val = ARMADA_37XX_NB_CLK_SEL_TBG << ARMADA_37XX_NB_CLK_SEL_OFF;
>> +		mask = (ARMADA_37XX_NB_CLK_SEL_MASK
>> +			<< ARMADA_37XX_NB_CLK_SEL_OFF);
>> +
>> +		/*
>> +		 * Set cpu divider based on the pre-computed array in
>> +		 * order to have balanced step.
>> +		 */
>> +		val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF;
>> +		mask |= (ARMADA_37XX_NB_TBG_DIV_MASK
>> +			<< ARMADA_37XX_NB_TBG_DIV_OFF);
>> +
>> +		/* Set VDD divider which is actually the load level. */
>> +		val |= load_lvl << ARMADA_37XX_NB_VDD_SEL_OFF;
>> +		mask |= (ARMADA_37XX_NB_VDD_SEL_MASK
>> +			<< ARMADA_37XX_NB_VDD_SEL_OFF);
>> +
>> +		val <<= offset;
>> +		mask <<= offset;
>> +
>> +		regmap_update_bits(base, reg, mask, val);
>> +	}
>> +
>> +	/*
>> +	 * Set cpu clock source, for all the level we keep the same
>> +	 * clock source that the one already configured. For this one
>> +	 * we need to use the clock framework
>> +	 */
>> +	parent = clk_get_parent(clk);
>> +	clk_set_parent(clk, parent);
>> +}
>> +
>> +static void __init armada37xx_cpufreq_disable_dvfs(struct regmap *base)
>> +{
>> +	unsigned int reg = ARMADA_37XX_NB_DYN_MOD,
>> +		mask = ARMADA_37XX_NB_DFS_EN;
>> +
>> +	regmap_update_bits(base, reg, mask, 0);
>> +}
>> +
>> +static void __init armada37xx_cpufreq_enable_dvfs(struct regmap *base)
>> +{
>> +	unsigned int val, reg = ARMADA_37XX_NB_CPU_LOAD,
>> +		mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
>> +
>> +	/* Start with the highest load (0) */
>> +	val = ARMADA_37XX_DVFS_LOAD_0;
>> +	regmap_update_bits(base, reg, mask, val);
>> +
>> +	/* Now enable DVFS for the CPUs */
>> +	reg = ARMADA_37XX_NB_DYN_MOD;
>> +	mask =	ARMADA_37XX_NB_CLK_SEL_EN | ARMADA_37XX_NB_TBG_EN |
>> +		ARMADA_37XX_NB_DIV_EN | ARMADA_37XX_NB_VDD_EN |
>> +		ARMADA_37XX_NB_DFS_EN;
>> +
>> +	regmap_update_bits(base, reg, mask, mask);
>> +}
>> +
>> +static int __init armada37xx_cpufreq_driver_init(void)
>> +{
>> +	struct armada_37xx_dvfs *dvfs;
>> +	struct platform_device *pdev;
>> +	unsigned int cur_frequency;
>> +	struct regmap *nb_pm_base;
>> +	struct device *cpu_dev;
>> +	int load_lvl, ret;
>> +	struct clk *clk;
>> +
>> +	nb_pm_base =
>> +		syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
>> +
>> +	if (IS_ERR(nb_pm_base))
>> +		return -ENODEV;
>> +
>> +	/* Before doing any configuration on the DVFS first, disable it */
>> +	armada37xx_cpufreq_disable_dvfs(nb_pm_base);
>> +
>> +	/*
>> +	 * On CPU 0 register the operating points supported (which are
>> +	 * the nominal CPU frequency and full integer divisions of
>> +	 * it).
>> +	 */
>> +	cpu_dev = get_cpu_device(0);
>> +	if (!cpu_dev) {
>> +		dev_err(cpu_dev, "Cannot get CPU\n");
>> +		return -ENODEV;
>> +	}
>> +
>> +	clk = clk_get(cpu_dev, 0);
>> +	if (IS_ERR(clk)) {
>> +		dev_err(cpu_dev, "Cannot get clock for CPU0\n");
>> +		return PTR_ERR(clk);
>> +	}
>> +
>> +	/* Get nominal (current) CPU frequency */
>> +	cur_frequency = clk_get_rate(clk);
>> +	if (!cur_frequency) {
>> +		dev_err(cpu_dev, "Failed to get clock rate for CPU\n");
>> +		return -EINVAL;
>> +	}
>> +
>> +	dvfs = armada_37xx_cpu_freq_info_get(cur_frequency);
>> +	if (!dvfs)
>> +		return -EINVAL;
>> +
>> +	armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider);
>> +
>> +	for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
>> +	     load_lvl++) {
>> +		unsigned long freq = cur_frequency / dvfs->divider[load_lvl];
>> +
>> +		ret = dev_pm_opp_add(cpu_dev, freq, 0);
>> +		if (ret) {
>> +			/*  clean-up the already added opp before leaving */
>
> Double space after /*

Typo

>
>> +			while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) {
>> +				freq = cur_frequency / dvfs->divider[load_lvl];
>> +				dev_pm_opp_remove(cpu_dev, freq);
>> +			}
>> +			return ret;
>> +		}
>> +	}
>> +
>> +	/* Now that everything is setup, enable the DVFS at hardware level */
>> +	armada37xx_cpufreq_enable_dvfs(nb_pm_base);
>> +
>> +	pdev = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
>> +
>> +	return PTR_ERR_OR_ZERO(pdev);
>> +}
>> +/* late_initcall, to guarantee the driver is loaded after A37xx clock driver */
>> +late_initcall(armada37xx_cpufreq_driver_init);
>> +
>> +MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
>> +MODULE_DESCRIPTION("Armada 37xx cpufreq driver");
>> +MODULE_LICENSE("GPL");
>
> I am not objecting to using double spaces at all these locations, its fine. Just
> that I wanted to point it out in case it is not intentional.

I will send a new version fixing the last typo you find, however unless
your are strongly against it I would like to keep the  distinction
between register and their content.

Thanks,

Gregory


>
> -- 
> viresh

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH v3 3/4] cpufreq: Add DVFS support for Armada 37xx

[Viresh Kumar]

On 14-12-17, 10:35, Gregory CLEMENT wrote:
> Actually from the beginning the idea was to make difference between the
> define for the offset of the register and then the define for the value
> related to this register.
> 
> Initially I used tab for this distinction, but then I though you
> suggested to only use space to have a more compact view, so I used double
> space.
> 
> I don't mind using double space or tab, but for me making distinction
> between offset of the register and content of the register helps the
> readability of the code.

Sure, this looks fine to me.

-- 
viresh
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