[PATCH v6 00/18] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support

[PATCH v6 00/18] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support

[Niklas Cassel]

This is a series that adds:
- PCI endpoint mode support in the ARTPEC-6 driver.
- ARTPEC-7 SoC support in the ARTPEC-6 driver (the SoCs are very similar).
- Small fixes for MSI in designware-ep and designware-host,
  needed to get endpoint mode support working for ARTPEC-6.
- Cleanups in pci-dra7xx to better prepare for endpoint mode in other
  DWC based PCIe drivers.

Changes since V5:
-Dropped GFP_DMA32 from "PCI: dwc: Use the DMA-API to get the MSI address"
 so that we use the exact same GFP flags as before.
-Rewrote commit message for "PCI: dwc: Make cpu_addr_fixup take struct
dw_pcie as argument" to be more detailed.

Niklas Cassel (18):
  PCI: dwc: Use the DMA-API to get the MSI address
  PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits
  PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be
    writable
  PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init
  PCI: designware-ep: Remove static keyword from dw_pcie_ep_reset_bar()
  PCI: designware-ep: Add generic function for raising MSI irq
  PCI: dwc: dra7xx: Refactor Kconfig and Makefile handling for host/ep
    mode
  PCI: dwc: dra7xx: Assign pp->ops in dra7xx_add_pcie_port() rather than
    in probe
  PCI: dwc: dra7xx: Help compiler to remove unused code
  PCI: dwc: artpec6: Remove unused defines
  PCI: dwc: artpec6: Use BIT and GENMASK macros
  PCI: dwc: artpec6: Split artpec6_pcie_establish_link() into smaller
    functions
  bindings: PCI: artpec: Add support for endpoint mode
  PCI: dwc: artpec6: Add support for endpoint mode
  PCI: dwc: Make cpu_addr_fixup take struct dw_pcie as argument
  PCI: dwc: artpec6: Deassert the core before waiting for PHY
  bindings: PCI: artpec: Add support for the ARTPEC-7 SoC
  PCI: dwc: artpec6: Add support for the ARTPEC-7 SoC

 .../devicetree/bindings/pci/axis,artpec6-pcie.txt  |   5 +-
 drivers/pci/dwc/Kconfig                            |  68 +--
 drivers/pci/dwc/Makefile                           |   4 +-
 drivers/pci/dwc/pci-dra7xx.c                       |  27 +-
 drivers/pci/dwc/pcie-artpec6.c                     | 470 ++++++++++++++++++---
 drivers/pci/dwc/pcie-designware-ep.c               |  59 ++-
 drivers/pci/dwc/pcie-designware-host.c             |  15 +-
 drivers/pci/dwc/pcie-designware.c                  |   2 +-
 drivers/pci/dwc/pcie-designware.h                  |  22 +-
 9 files changed, 554 insertions(+), 118 deletions(-)

-- 
2.14.2

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[PATCH v6 13/18] bindings: PCI: artpec: Add support for endpoint mode

[Niklas Cassel]

The PCIe controller integrated in ARTPEC-6 SoCs is capable of operating in
endpoint mode. Add endpoint mode support to the artpec6 driver.

Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
index 4e4aee4439ea..33eef7ae5a23 100644
--- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
@@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsys DesignWare PCIe IP
 and thus inherits all the common properties defined in designware-pcie.txt.
 
 Required properties:
-- compatible: "axis,artpec6-pcie", "snps,dw-pcie"
+- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
+	      "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
 - reg: base addresses and lengths of the PCIe controller (DBI),
 	the PHY controller, and configuration address space.
 - reg-names: Must include the following entries:
-- 
2.14.2

[PATCH v6 17/18] bindings: PCI: artpec: Add support for the ARTPEC-7 SoC

[Niklas Cassel]

Add support for the ARTPEC-7 SoC in the artpec6 driver.
The ARTPEC-6 SoC and the ARTPEC-7 SoC are very similar.
Unfortunately, some fields in the PCIECFG and PCIESTAT
register have changed.

Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
index 33eef7ae5a23..979dc7b6cfe8 100644
--- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
@@ -6,6 +6,8 @@ and thus inherits all the common properties defined in designware-pcie.txt.
 Required properties:
 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
 	      "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
+	      "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
+	      "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
 - reg: base addresses and lengths of the PCIe controller (DBI),
 	the PHY controller, and configuration address space.
 - reg-names: Must include the following entries:
-- 
2.14.2

Re: [PATCH v6 00/18] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support

[Lorenzo Pieralisi]

On Wed, Dec 20, 2017 at 12:29:21AM +0100, Niklas Cassel wrote:
> This is a series that adds:
> - PCI endpoint mode support in the ARTPEC-6 driver.
> - ARTPEC-7 SoC support in the ARTPEC-6 driver (the SoCs are very similar).
> - Small fixes for MSI in designware-ep and designware-host,
>   needed to get endpoint mode support working for ARTPEC-6.
> - Cleanups in pci-dra7xx to better prepare for endpoint mode in other
>   DWC based PCIe drivers.

Joao, Jingoo,

Gustavo tested the series and Kishon ACK'ed the relevant patches,
I need your ACKs on designware patches to queue this series for
v4.16.

I am away from tomorrow (noon) till beginning of January which means
that either I queue this series tomorrow or at -rc6, please do
chime in if you can.

Thanks,
Lorenzo

> Changes since V5:
> -Dropped GFP_DMA32 from "PCI: dwc: Use the DMA-API to get the MSI address"
>  so that we use the exact same GFP flags as before.
> -Rewrote commit message for "PCI: dwc: Make cpu_addr_fixup take struct
> dw_pcie as argument" to be more detailed.
> 
> Niklas Cassel (18):
>   PCI: dwc: Use the DMA-API to get the MSI address
>   PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits
>   PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be
>     writable
>   PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init
>   PCI: designware-ep: Remove static keyword from dw_pcie_ep_reset_bar()
>   PCI: designware-ep: Add generic function for raising MSI irq
>   PCI: dwc: dra7xx: Refactor Kconfig and Makefile handling for host/ep
>     mode
>   PCI: dwc: dra7xx: Assign pp->ops in dra7xx_add_pcie_port() rather than
>     in probe
>   PCI: dwc: dra7xx: Help compiler to remove unused code
>   PCI: dwc: artpec6: Remove unused defines
>   PCI: dwc: artpec6: Use BIT and GENMASK macros
>   PCI: dwc: artpec6: Split artpec6_pcie_establish_link() into smaller
>     functions
>   bindings: PCI: artpec: Add support for endpoint mode
>   PCI: dwc: artpec6: Add support for endpoint mode
>   PCI: dwc: Make cpu_addr_fixup take struct dw_pcie as argument
>   PCI: dwc: artpec6: Deassert the core before waiting for PHY
>   bindings: PCI: artpec: Add support for the ARTPEC-7 SoC
>   PCI: dwc: artpec6: Add support for the ARTPEC-7 SoC
> 
>  .../devicetree/bindings/pci/axis,artpec6-pcie.txt  |   5 +-
>  drivers/pci/dwc/Kconfig                            |  68 +--
>  drivers/pci/dwc/Makefile                           |   4 +-
>  drivers/pci/dwc/pci-dra7xx.c                       |  27 +-
>  drivers/pci/dwc/pcie-artpec6.c                     | 470 ++++++++++++++++++---
>  drivers/pci/dwc/pcie-designware-ep.c               |  59 ++-
>  drivers/pci/dwc/pcie-designware-host.c             |  15 +-
>  drivers/pci/dwc/pcie-designware.c                  |   2 +-
>  drivers/pci/dwc/pcie-designware.h                  |  22 +-
>  9 files changed, 554 insertions(+), 118 deletions(-)
> 
> -- 
> 2.14.2
> 

Re: [PATCH v6 00/18] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support

[Joao Pinto]

Hello to all,

Às 5:34 PM de 12/20/2017, Lorenzo Pieralisi escreveu:
> On Wed, Dec 20, 2017 at 12:29:21AM +0100, Niklas Cassel wrote:
>> This is a series that adds:
>> - PCI endpoint mode support in the ARTPEC-6 driver.
>> - ARTPEC-7 SoC support in the ARTPEC-6 driver (the SoCs are very similar).
>> - Small fixes for MSI in designware-ep and designware-host,
>>   needed to get endpoint mode support working for ARTPEC-6.
>> - Cleanups in pci-dra7xx to better prepare for endpoint mode in other
>>   DWC based PCIe drivers.
> 
> Joao, Jingoo,
> 
> Gustavo tested the series and Kishon ACK'ed the relevant patches,
> I need your ACKs on designware patches to queue this series for
> v4.16.
> 
> I am away from tomorrow (noon) till beginning of January which means
> that either I queue this series tomorrow or at -rc6, please do
> chime in if you can.

Sorry, I have been a bit tied up! Already checked each patch related to DWC.
Could anyone from artpec finish the revision, since there are some patches
related to that SoC?

Thanks,
Joao

> 
> Thanks,
> Lorenzo
> 
>> Changes since V5:
>> -Dropped GFP_DMA32 from "PCI: dwc: Use the DMA-API to get the MSI address"
>>  so that we use the exact same GFP flags as before.
>> -Rewrote commit message for "PCI: dwc: Make cpu_addr_fixup take struct
>> dw_pcie as argument" to be more detailed.
>>
>> Niklas Cassel (18):
>>   PCI: dwc: Use the DMA-API to get the MSI address
>>   PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits
>>   PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be
>>     writable
>>   PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init
>>   PCI: designware-ep: Remove static keyword from dw_pcie_ep_reset_bar()
>>   PCI: designware-ep: Add generic function for raising MSI irq
>>   PCI: dwc: dra7xx: Refactor Kconfig and Makefile handling for host/ep
>>     mode
>>   PCI: dwc: dra7xx: Assign pp->ops in dra7xx_add_pcie_port() rather than
>>     in probe
>>   PCI: dwc: dra7xx: Help compiler to remove unused code
>>   PCI: dwc: artpec6: Remove unused defines
>>   PCI: dwc: artpec6: Use BIT and GENMASK macros
>>   PCI: dwc: artpec6: Split artpec6_pcie_establish_link() into smaller
>>     functions
>>   bindings: PCI: artpec: Add support for endpoint mode
>>   PCI: dwc: artpec6: Add support for endpoint mode
>>   PCI: dwc: Make cpu_addr_fixup take struct dw_pcie as argument
>>   PCI: dwc: artpec6: Deassert the core before waiting for PHY
>>   bindings: PCI: artpec: Add support for the ARTPEC-7 SoC
>>   PCI: dwc: artpec6: Add support for the ARTPEC-7 SoC
>>
>>  .../devicetree/bindings/pci/axis,artpec6-pcie.txt  |   5 +-
>>  drivers/pci/dwc/Kconfig                            |  68 +--
>>  drivers/pci/dwc/Makefile                           |   4 +-
>>  drivers/pci/dwc/pci-dra7xx.c                       |  27 +-
>>  drivers/pci/dwc/pcie-artpec6.c                     | 470 ++++++++++++++++++---
>>  drivers/pci/dwc/pcie-designware-ep.c               |  59 ++-
>>  drivers/pci/dwc/pcie-designware-host.c             |  15 +-
>>  drivers/pci/dwc/pcie-designware.c                  |   2 +-
>>  drivers/pci/dwc/pcie-designware.h                  |  22 +-
>>  9 files changed, 554 insertions(+), 118 deletions(-)
>>
>> -- 
>> 2.14.2
>>

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Re: [PATCH v6 00/18] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support

[Niklas Cassel]

On Wed, Dec 20, 2017 at 07:47:41PM +0000, Joao Pinto wrote:
> 
> Hello to all,
> 
> Às 5:34 PM de 12/20/2017, Lorenzo Pieralisi escreveu:
> > On Wed, Dec 20, 2017 at 12:29:21AM +0100, Niklas Cassel wrote:
> >> This is a series that adds:
> >> - PCI endpoint mode support in the ARTPEC-6 driver.
> >> - ARTPEC-7 SoC support in the ARTPEC-6 driver (the SoCs are very similar).
> >> - Small fixes for MSI in designware-ep and designware-host,
> >>   needed to get endpoint mode support working for ARTPEC-6.
> >> - Cleanups in pci-dra7xx to better prepare for endpoint mode in other
> >>   DWC based PCIe drivers.
> > 
> > Joao, Jingoo,
> > 
> > Gustavo tested the series and Kishon ACK'ed the relevant patches,
> > I need your ACKs on designware patches to queue this series for
> > v4.16.
> > 
> > I am away from tomorrow (noon) till beginning of January which means
> > that either I queue this series tomorrow or at -rc6, please do
> > chime in if you can.
> 
> Sorry, I have been a bit tied up! Already checked each patch related to DWC.
> Could anyone from artpec finish the revision, since there are some patches
> related to that SoC?

Thanks for looking at the patches.

Thanks to everyone that has helped in any way.

Since I am the maintainer for pcie-artpec6.c
(at least according to MAINTAINERS ;)),
I'm supposing that my sign-off will suffice.

Regards,
Niklas

Re: [PATCH v6 00/18] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support

[Joao Pinto]

Hi Niklas,

Às 11:22 PM de 12/20/2017, Niklas Cassel escreveu:
> On Wed, Dec 20, 2017 at 07:47:41PM +0000, Joao Pinto wrote:
>>
>> Hello to all,
>>
>> Às 5:34 PM de 12/20/2017, Lorenzo Pieralisi escreveu:
>>> On Wed, Dec 20, 2017 at 12:29:21AM +0100, Niklas Cassel wrote:
>>>> This is a series that adds:
>>>> - PCI endpoint mode support in the ARTPEC-6 driver.
>>>> - ARTPEC-7 SoC support in the ARTPEC-6 driver (the SoCs are very similar).
>>>> - Small fixes for MSI in designware-ep and designware-host,
>>>>   needed to get endpoint mode support working for ARTPEC-6.
>>>> - Cleanups in pci-dra7xx to better prepare for endpoint mode in other
>>>>   DWC based PCIe drivers.
>>>
>>> Joao, Jingoo,
>>>
>>> Gustavo tested the series and Kishon ACK'ed the relevant patches,
>>> I need your ACKs on designware patches to queue this series for
>>> v4.16.
>>>
>>> I am away from tomorrow (noon) till beginning of January which means
>>> that either I queue this series tomorrow or at -rc6, please do
>>> chime in if you can.
>>
>> Sorry, I have been a bit tied up! Already checked each patch related to DWC.
>> Could anyone from artpec finish the revision, since there are some patches
>> related to that SoC?
> 
> Thanks for looking at the patches.
> 
> Thanks to everyone that has helped in any way.
> 
> Since I am the maintainer for pcie-artpec6.c
> (at least according to MAINTAINERS ;)),
> I'm supposing that my sign-off will suffice.

You're right :), I didn't remember you were the maintainer.
Have a Merry Christmas.

Thanks,
Joao

> 
> Regards,
> Niklas
> 

Re: [PATCH v6 00/18] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support

[Lorenzo Pieralisi]

On Wed, Dec 20, 2017 at 12:29:21AM +0100, Niklas Cassel wrote:
> This is a series that adds:
> - PCI endpoint mode support in the ARTPEC-6 driver.
> - ARTPEC-7 SoC support in the ARTPEC-6 driver (the SoCs are very similar).
> - Small fixes for MSI in designware-ep and designware-host,
>   needed to get endpoint mode support working for ARTPEC-6.
> - Cleanups in pci-dra7xx to better prepare for endpoint mode in other
>   DWC based PCIe drivers.
> 
> Changes since V5:
> -Dropped GFP_DMA32 from "PCI: dwc: Use the DMA-API to get the MSI address"
>  so that we use the exact same GFP flags as before.
> -Rewrote commit message for "PCI: dwc: Make cpu_addr_fixup take struct
> dw_pcie as argument" to be more detailed.
> 
> Niklas Cassel (18):
>   PCI: dwc: Use the DMA-API to get the MSI address
>   PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits
>   PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be
>     writable
>   PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init
>   PCI: designware-ep: Remove static keyword from dw_pcie_ep_reset_bar()
>   PCI: designware-ep: Add generic function for raising MSI irq
>   PCI: dwc: dra7xx: Refactor Kconfig and Makefile handling for host/ep
>     mode
>   PCI: dwc: dra7xx: Assign pp->ops in dra7xx_add_pcie_port() rather than
>     in probe
>   PCI: dwc: dra7xx: Help compiler to remove unused code
>   PCI: dwc: artpec6: Remove unused defines
>   PCI: dwc: artpec6: Use BIT and GENMASK macros
>   PCI: dwc: artpec6: Split artpec6_pcie_establish_link() into smaller
>     functions
>   bindings: PCI: artpec: Add support for endpoint mode
>   PCI: dwc: artpec6: Add support for endpoint mode
>   PCI: dwc: Make cpu_addr_fixup take struct dw_pcie as argument
>   PCI: dwc: artpec6: Deassert the core before waiting for PHY
>   bindings: PCI: artpec: Add support for the ARTPEC-7 SoC
>   PCI: dwc: artpec6: Add support for the ARTPEC-7 SoC
> 
>  .../devicetree/bindings/pci/axis,artpec6-pcie.txt  |   5 +-
>  drivers/pci/dwc/Kconfig                            |  68 +--
>  drivers/pci/dwc/Makefile                           |   4 +-
>  drivers/pci/dwc/pci-dra7xx.c                       |  27 +-
>  drivers/pci/dwc/pcie-artpec6.c                     | 470 ++++++++++++++++++---
>  drivers/pci/dwc/pcie-designware-ep.c               |  59 ++-
>  drivers/pci/dwc/pcie-designware-host.c             |  15 +-
>  drivers/pci/dwc/pcie-designware.c                  |   2 +-
>  drivers/pci/dwc/pcie-designware.h                  |  22 +-
>  9 files changed, 554 insertions(+), 118 deletions(-)

Applied to pci/dwc for v4.16.

Thanks,
Lorenzo
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