[PATCH 0/3] DWC3 support for Amlogic Meson AXG and GXL SoCs

[PATCH 0/3] DWC3 support for Amlogic Meson AXG and GXL SoCs

[Martin Blumenstingl]

Amlogic Meson AXG and GXL SoCs can use the dwc3-of-simple with little
modifications. These SoCs use:
- a gate clock for the USB components (DWC3, USB PHYs)
- a reset line which is shared across all USB components (DWC3, USB2 and
  USB3 PHYs, OTG detection logic inside the USB3 PHY registers)
- a reset pulse to trigger the reset
- depending on the SoC two or more PHYs (AXG: 1x USB2 and 1x USB3 PHY,
  GXL: 2x USB2 and 1x USB3 PHY)

This extends the dwc3-of-simple so it supports (depending on the
platform) shared and level resets. Additionally it adds new bindings
for the Amlogic Meson AXG and GXL SoCs, along with the documentation
(dt-bindings).

NOTE: for full support on Amlogic Meson GXL SoCs my other series called
"initialize (multiple) PHYs for a HCD" (see [0] for v8 of that series)
is required. However, there is no direct dependency on that series.
Especially since Meson AXG doesn't need it (since it only has one USB2
and one USB3 PHY, which is already supported by the current dwc3 driver,
unlike the 2x USB2 and 1x USB3 PHYs on Meson GXL).
So I believe that this series can still be merged, even if the other
patchset is not ready yet.


[0] http://lists.infradead.org/pipermail/linux-amlogic/2018-January/006274.html


Martin Blumenstingl (3):
  dt-bindings: usb: add support for dwc3 controller on Amlogic Meson GX
  usb: dwc3: of-simple: add support for shared and pulsed reset lines
  usb: dwc3: of-simple: add support for the Amlogic Meson GXL and AXG
    SoCs

 .../devicetree/bindings/usb/amlogic,dwc3.txt       | 42 ++++++++++++
 drivers/usb/dwc3/dwc3-of-simple.c                  | 78 +++++++++++++++++++---
 2 files changed, 109 insertions(+), 11 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/amlogic,dwc3.txt

-- 
2.16.1

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[PATCH 1/3] dt-bindings: usb: add support for dwc3 controller on Amlogic Meson GX

[Martin Blumenstingl]

Amlogic Meson GX SoCs (GXL and AXG) come with a (host-only) dwc3 USB
controller. This requires a clock to be enabled and a reset line to be
pulsed to get the hardware into a known state.
Add the documentation for this IP block, similar to "qcom,dwc3.txt".

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 .../devicetree/bindings/usb/amlogic,dwc3.txt       | 42 ++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/amlogic,dwc3.txt

diff --git a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt
new file mode 100644
index 000000000000..9a8b631904fd
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt
@@ -0,0 +1,42 @@
+Amlogic Meson GX DWC3 USB SoC controller
+
+Required properties:
+- compatible:	depending on the SoC this should contain one of:
+			* amlogic,meson-axg-dwc3
+			* amlogic,meson-gxl-dwc3
+- clocks:	a handle for the "USB general" clock
+- clock-names:	must be "usb_general"
+- resets:	a handle for the shared "USB OTG" reset line
+- reset-names:	must be "usb_otg"
+
+Required child node:
+A child node must exist to represent the core DWC3 IP block. The name of
+the node is not important. The content of the node is defined in dwc3.txt.
+
+PHY documentation is provided in the following places:
+- Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
+- Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt
+
+Example device nodes:
+		usb0: usb@ff500000 {
+			compatible = "amlogic,meson-axg-dwc3";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			clocks = <&clkc CLKID_USB>;
+			clock-names = "usb_general";
+			resets = <&reset RESET_USB_OTG>;
+			reset-names = "usb_otg";
+
+			dwc3: dwc3@ff500000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0xff500000 0x0 0x100000>;
+				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+				dr_mode = "host";
+				maximum-speed = "high-speed";
+				snps,dis_u2_susphy_quirk;
+				phys = <&usb3_phy>, <&usb2_phy0>;
+				phy-names = "usb2-phy", "usb3-phy";
+			};
+		};
-- 
2.16.1

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[PATCH 2/3] usb: dwc3: of-simple: add support for shared and pulsed reset lines

[Martin Blumenstingl]

Some SoCs (such as Amlogic Meson GXL for example) share the reset line
with other components (in case of the Meson GXL example there's a shared
reset line between the USB2 PHYs, USB3 PHYs and the dwc3 controller).
Additionally SoC implementations may prefer a reset pulse over level
resets.

Add an internal per-of_device_id struct which can be used to configure
whether the reset lines are shared and whether they use level or pulse
resets.

For now this falls back to the old defaults, which are:
- reset lines are exclusive
- level resets are being used

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 drivers/usb/dwc3/dwc3-of-simple.c | 65 ++++++++++++++++++++++++++++++++-------
 1 file changed, 54 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
index 7ae0eefc7cc7..ceb9f0cd822a 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
@@ -22,11 +22,22 @@
 #include <linux/pm_runtime.h>
 #include <linux/reset.h>
 
+/**
+ * struct dwc3_of_simple_params - hardware specific parameters
+ * @shared_resets: indicates that the resets are shared or exclusive
+ * @pulse_resets: use a reset pulse instead of level based resets
+ */
+struct dwc3_of_simple_params {
+	bool			shared_resets;
+	bool			pulse_resets;
+};
+
 struct dwc3_of_simple {
 	struct device		*dev;
 	struct clk		**clks;
 	int			num_clocks;
 	struct reset_control	*resets;
+	const struct dwc3_of_simple_params	*params;
 };
 
 static int dwc3_of_simple_clk_init(struct dwc3_of_simple *simple, int count)
@@ -90,17 +101,26 @@ static int dwc3_of_simple_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, simple);
 	simple->dev = dev;
+	simple->params = of_device_get_match_data(dev);
 
-	simple->resets = of_reset_control_array_get_optional_exclusive(np);
+	simple->resets = of_reset_control_array_get(np,
+						simple->params->shared_resets,
+						true);
 	if (IS_ERR(simple->resets)) {
 		ret = PTR_ERR(simple->resets);
 		dev_err(dev, "failed to get device resets, err=%d\n", ret);
 		return ret;
 	}
 
-	ret = reset_control_deassert(simple->resets);
-	if (ret)
-		goto err_resetc_put;
+	if (simple->params->pulse_resets) {
+		ret = reset_control_reset(simple->resets);
+		if (ret)
+			goto err_resetc_put;
+	} else {
+		ret = reset_control_deassert(simple->resets);
+		if (ret)
+			goto err_resetc_put;
+	}
 
 	ret = dwc3_of_simple_clk_init(simple, of_count_phandle_with_args(np,
 						"clocks", "#clock-cells"));
@@ -124,7 +144,8 @@ static int dwc3_of_simple_probe(struct platform_device *pdev)
 	return 0;
 
 err_resetc_assert:
-	reset_control_assert(simple->resets);
+	if (!simple->params->pulse_resets)
+		reset_control_assert(simple->resets);
 
 err_resetc_put:
 	reset_control_put(simple->resets);
@@ -144,7 +165,9 @@ static int dwc3_of_simple_remove(struct platform_device *pdev)
 		clk_put(simple->clks[i]);
 	}
 
-	reset_control_assert(simple->resets);
+	if (!simple->params->pulse_resets)
+		reset_control_assert(simple->resets);
+
 	reset_control_put(simple->resets);
 
 	pm_runtime_put_sync(dev);
@@ -189,12 +212,32 @@ static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = {
 			dwc3_of_simple_runtime_resume, NULL)
 };
 
+static const struct dwc3_of_simple_params dwc3_of_simple_default_params = {
+	.shared_resets = false,
+	.pulse_resets = false,
+};
+
 static const struct of_device_id of_dwc3_simple_match[] = {
-	{ .compatible = "qcom,dwc3" },
-	{ .compatible = "rockchip,rk3399-dwc3" },
-	{ .compatible = "xlnx,zynqmp-dwc3" },
-	{ .compatible = "cavium,octeon-7130-usb-uctl" },
-	{ .compatible = "sprd,sc9860-dwc3" },
+	{
+		.compatible = "qcom,dwc3",
+		.data = &dwc3_of_simple_default_params
+	},
+	{
+		.compatible = "rockchip,rk3399-dwc3",
+		.data = &dwc3_of_simple_default_params
+	},
+	{
+		.compatible = "xlnx,zynqmp-dwc3",
+		.data = &dwc3_of_simple_default_params
+	},
+	{
+		.compatible = "cavium,octeon-7130-usb-uctl",
+		.data = &dwc3_of_simple_default_params
+	},
+	{
+		.compatible = "sprd,sc9860-dwc3",
+		.data = &dwc3_of_simple_default_params
+	},
 	{ /* Sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, of_dwc3_simple_match);
-- 
2.16.1

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[PATCH 3/3] usb: dwc3: of-simple: add support for the Amlogic Meson GXL and AXG SoCs

[Martin Blumenstingl]

Amlogic Meson GXL and AXG SoCs come with a (host-only) dwc3 USB
controller. To use this controller a clock has to be enabled and a reset
line has to be pulsed.
Enabling the clock works identical to other SoCs. However, the reset
line has to be pulsed (using reset_control_reset) instead of using a
level reset (reset_control_{assert,deassert}).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 drivers/usb/dwc3/dwc3-of-simple.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
index ceb9f0cd822a..d9e4b8b09eaf 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
@@ -217,6 +217,11 @@ static const struct dwc3_of_simple_params dwc3_of_simple_default_params = {
 	.pulse_resets = false,
 };
 
+static const struct dwc3_of_simple_params dwc3_of_simple_amlogic_params = {
+	.shared_resets = true,
+	.pulse_resets = true,
+};
+
 static const struct of_device_id of_dwc3_simple_match[] = {
 	{
 		.compatible = "qcom,dwc3",
@@ -238,6 +243,14 @@ static const struct of_device_id of_dwc3_simple_match[] = {
 		.compatible = "sprd,sc9860-dwc3",
 		.data = &dwc3_of_simple_default_params
 	},
+	{
+		.compatible = "amlogic,meson-axg-dwc3",
+		.data = &dwc3_of_simple_amlogic_params
+	},
+	{
+		.compatible = "amlogic,meson-gxl-dwc3",
+		.data = &dwc3_of_simple_amlogic_params
+	},
 	{ /* Sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, of_dwc3_simple_match);
-- 
2.16.1

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Re: [PATCH 2/3] usb: dwc3: of-simple: add support for shared and pulsed reset lines

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 2709 bytes --]


Hi,

Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> writes:
> Some SoCs (such as Amlogic Meson GXL for example) share the reset line
> with other components (in case of the Meson GXL example there's a shared
> reset line between the USB2 PHYs, USB3 PHYs and the dwc3 controller).
> Additionally SoC implementations may prefer a reset pulse over level
> resets.
>
> Add an internal per-of_device_id struct which can be used to configure
> whether the reset lines are shared and whether they use level or pulse
> resets.
>
> For now this falls back to the old defaults, which are:
> - reset lines are exclusive
> - level resets are being used
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  drivers/usb/dwc3/dwc3-of-simple.c | 65 ++++++++++++++++++++++++++++++++-------
>  1 file changed, 54 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
> index 7ae0eefc7cc7..ceb9f0cd822a 100644
> --- a/drivers/usb/dwc3/dwc3-of-simple.c
> +++ b/drivers/usb/dwc3/dwc3-of-simple.c
> @@ -22,11 +22,22 @@
>  #include <linux/pm_runtime.h>
>  #include <linux/reset.h>
>  
> +/**
> + * struct dwc3_of_simple_params - hardware specific parameters
> + * @shared_resets: indicates that the resets are shared or exclusive
> + * @pulse_resets: use a reset pulse instead of level based resets
> + */
> +struct dwc3_of_simple_params {
> +	bool			shared_resets;
> +	bool			pulse_resets;
> +};
> +
>  struct dwc3_of_simple {
>  	struct device		*dev;
>  	struct clk		**clks;
>  	int			num_clocks;
>  	struct reset_control	*resets;
> +	const struct dwc3_of_simple_params	*params;

instead, you can add these two fields here:

	bool shared_resets;
        bool pulse_resets;

and ...

> @@ -90,17 +101,26 @@ static int dwc3_of_simple_probe(struct platform_device *pdev)
>  
>  	platform_set_drvdata(pdev, simple);
>  	simple->dev = dev;
> +	simple->params = of_device_get_match_data(dev);
>  
> -	simple->resets = of_reset_control_array_get_optional_exclusive(np);
> +	simple->resets = of_reset_control_array_get(np,
> +						simple->params->shared_resets,
> +						true);

wrap this with a of_device_is_compatible() check:

	if (of_device_is_compatible(dev->of_node, "foobar")) {
        	simple->shared_resets = true;
		simple->pulse_resets = true;
	}

or something like that. Then we don't need to add a new
dwc3_of_simple_params for everybody.

Also, the why isn't the reset type (pulse vs level) handled by reset
framework itself? Why does dwc3-of-simple need to know about it?

-- 
balbi

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Re: [PATCH 2/3] usb: dwc3: of-simple: add support for shared and pulsed reset lines

[Martin Blumenstingl]

Hi Felipe,

On Mon, Jan 29, 2018 at 9:18 AM, Felipe Balbi <balbi-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
>
> Hi,
>
> Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> writes:
>> Some SoCs (such as Amlogic Meson GXL for example) share the reset line
>> with other components (in case of the Meson GXL example there's a shared
>> reset line between the USB2 PHYs, USB3 PHYs and the dwc3 controller).
>> Additionally SoC implementations may prefer a reset pulse over level
>> resets.
>>
>> Add an internal per-of_device_id struct which can be used to configure
>> whether the reset lines are shared and whether they use level or pulse
>> resets.
>>
>> For now this falls back to the old defaults, which are:
>> - reset lines are exclusive
>> - level resets are being used
>>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>> ---
>>  drivers/usb/dwc3/dwc3-of-simple.c | 65 ++++++++++++++++++++++++++++++++-------
>>  1 file changed, 54 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
>> index 7ae0eefc7cc7..ceb9f0cd822a 100644
>> --- a/drivers/usb/dwc3/dwc3-of-simple.c
>> +++ b/drivers/usb/dwc3/dwc3-of-simple.c
>> @@ -22,11 +22,22 @@
>>  #include <linux/pm_runtime.h>
>>  #include <linux/reset.h>
>>
>> +/**
>> + * struct dwc3_of_simple_params - hardware specific parameters
>> + * @shared_resets: indicates that the resets are shared or exclusive
>> + * @pulse_resets: use a reset pulse instead of level based resets
>> + */
>> +struct dwc3_of_simple_params {
>> +     bool                    shared_resets;
>> +     bool                    pulse_resets;
>> +};
>> +
>>  struct dwc3_of_simple {
>>       struct device           *dev;
>>       struct clk              **clks;
>>       int                     num_clocks;
>>       struct reset_control    *resets;
>> +     const struct dwc3_of_simple_params      *params;
>
> instead, you can add these two fields here:
>
>         bool shared_resets;
>         bool pulse_resets;
>
> and ...
>
>> @@ -90,17 +101,26 @@ static int dwc3_of_simple_probe(struct platform_device *pdev)
>>
>>       platform_set_drvdata(pdev, simple);
>>       simple->dev = dev;
>> +     simple->params = of_device_get_match_data(dev);
>>
>> -     simple->resets = of_reset_control_array_get_optional_exclusive(np);
>> +     simple->resets = of_reset_control_array_get(np,
>> +                                             simple->params->shared_resets,
>> +                                             true);
>
> wrap this with a of_device_is_compatible() check:
>
>         if (of_device_is_compatible(dev->of_node, "foobar")) {
>                 simple->shared_resets = true;
>                 simple->pulse_resets = true;
>         }
>
> or something like that. Then we don't need to add a new
> dwc3_of_simple_params for everybody.
sure, I can do this if that fits the coding style in the dwc3 driver better
in that case, do you still want me to keep patches #2 and #3 separate?

> Also, the why isn't the reset type (pulse vs level) handled by reset
> framework itself? Why does dwc3-of-simple need to know about it?
the Amlogic reset driver supports both, level resets and reset pulses
unfortunately the reset line is de-asserted by default, so to reset it
we would have to:
- assert it first
- then de-assert it again

however, the reset framework does not allow this for shared resets
(see reset_control_assert: it triggers a WARN_ON if we try to assert a
shared reset which has not been de-asserted yet)
together with the fact that there are reset controller hardware
implementations out there which don't support level resets I decided
to implement it as reset pulse


Regards
Martin
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Re: [PATCH 1/3] dt-bindings: usb: add support for dwc3 controller on Amlogic Meson GX

[Rob Herring]

On Sun, Jan 28, 2018 at 09:03:31PM +0100, Martin Blumenstingl wrote:
> Amlogic Meson GX SoCs (GXL and AXG) come with a (host-only) dwc3 USB
> controller. This requires a clock to be enabled and a reset line to be
> pulsed to get the hardware into a known state.
> Add the documentation for this IP block, similar to "qcom,dwc3.txt".
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  .../devicetree/bindings/usb/amlogic,dwc3.txt       | 42 ++++++++++++++++++++++
>  1 file changed, 42 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/usb/amlogic,dwc3.txt

Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

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