* [PATCH 1/3] ARM: dts: omap4-droid4: Fix USB PHY port naming
@ 2018-03-01 4:01 Tony Lindgren
2018-03-01 4:01 ` [PATCH 2/3] ARM: dts: omap4-droid4: Configure MDM6600 USB PHY Tony Lindgren
2018-03-01 4:01 ` [PATCH 3/3] ARM: dts: omap4-droid4: Configure uart1 pins Tony Lindgren
0 siblings, 2 replies; 3+ messages in thread
From: Tony Lindgren @ 2018-03-01 4:01 UTC (permalink / raw)
To: linux-omap
Cc: Benoît Cousson, devicetree, Marcel Partap, Michael Scott,
Rob Herring, Sebastian Reichel
We have a USB OCHI PHY on port 1 for mdm6600. Port 2 is using transceiverless
logic (TLL) for USB EHCI for w3glte modem.
Let's also fix the node name to use usb-phy while at it.
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/omap4-droid4-xt894.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts
--- a/arch/arm/boot/dts/omap4-droid4-xt894.dts
+++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts
@@ -71,8 +71,8 @@
regulator-always-on;
};
- /* HS USB Host PHY on PORT 1 */
- hsusb1_phy: hsusb1_phy {
+ /* HS USB host TLL nop-phy on port 2 for w3glte */
+ hsusb2_phy: usb-phy@2 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
@@ -584,7 +584,7 @@
};
&usbhsehci {
- phys = <&hsusb1_phy>;
+ phys = <&hsusb2_phy>;
};
&usbhshost {
--
2.16.2
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 2/3] ARM: dts: omap4-droid4: Configure MDM6600 USB PHY
2018-03-01 4:01 [PATCH 1/3] ARM: dts: omap4-droid4: Fix USB PHY port naming Tony Lindgren
@ 2018-03-01 4:01 ` Tony Lindgren
2018-03-01 4:01 ` [PATCH 3/3] ARM: dts: omap4-droid4: Configure uart1 pins Tony Lindgren
1 sibling, 0 replies; 3+ messages in thread
From: Tony Lindgren @ 2018-03-01 4:01 UTC (permalink / raw)
To: linux-omap
Cc: Benoît Cousson, devicetree, Marcel Partap, Michael Scott,
Sebastian Reichel
Configure MDM6600 USB PHY.
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Cc: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/omap4-droid4-xt894.dts | 64 ++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts
--- a/arch/arm/boot/dts/omap4-droid4-xt894.dts
+++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts
@@ -71,6 +71,28 @@
regulator-always-on;
};
+ /* FS USB Host PHY on port 1 for mdm6600 */
+ fsusb1_phy: usb-phy@1 {
+ compatible = "motorola,mapphone-mdm6600";
+ pinctrl-0 = <&usb_mdm6600_pins>;
+ pinctrl-names = "default";
+ enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; /* gpio_95 */
+ power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54 */
+ reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; /* gpio_49 */
+ /* mode: gpio_148 gpio_149 */
+ motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
+ <&gpio5 21 GPIO_ACTIVE_HIGH>;
+ /* cmd: gpio_103 gpio_104 gpio_142 */
+ motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
+ <&gpio4 8 GPIO_ACTIVE_HIGH>,
+ <&gpio5 14 GPIO_ACTIVE_HIGH>;
+ /* status: gpio_52 gpio_53 gpio_55 */
+ motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
+ <&gpio2 21 GPIO_ACTIVE_HIGH>,
+ <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ #phy-cells = <0>;
+ };
+
/* HS USB host TLL nop-phy on port 2 for w3glte */
hsusb2_phy: usb-phy@2 {
compatible = "usb-nop-xceiv";
@@ -459,6 +481,43 @@
>;
};
+ usb_mdm6600_pins: pinmux_usb_mdm6600_pins {
+ pinctrl-single,pins = <
+ /* enable 0x4a1000d8 usbb1_ulpitll_dat7.gpio_95 ag16 */
+ OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3)
+
+ /* power 0x4a10007c gpmc_nwp.gpio_54 c25 */
+ OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3)
+
+ /* reset 0x4a100072 gpmc_a25.gpio_49 d20 */
+ OMAP4_IOPAD(0x072, PIN_OUTPUT | MUX_MODE3)
+
+ /* mode0/bpwake 0x4a10014e sdmmc5_dat1.gpio_148 af4 */
+ OMAP4_IOPAD(0x14e, PIN_OUTPUT | MUX_MODE3)
+
+ /* mode1/apwake 0x4a100150 sdmmc5_dat2.gpio_149 ag3 */
+ OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW | PIN_INPUT | MUX_MODE3)
+
+ /* status0 0x4a10007e gpmc_clk.gpio_55 b22 */
+ OMAP4_IOPAD(0x07e, PIN_INPUT | MUX_MODE3)
+
+ /* status1 0x4a10007a gpmc_ncs3.gpio_53 c22 */
+ OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3)
+
+ /* status2 0x4a100078 gpmc_ncs2.gpio_52 d21 */
+ OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3)
+
+ /* cmd0 0x4a100094 gpmc_ncs6.gpio_103 c24 */
+ OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3)
+
+ /* cmd1 0x4a100096 gpmc_ncs7.gpio_104 d24 */
+ OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3)
+
+ /* cmd2 0x4a100142 uart3_rts_sd.gpio_142 f28 */
+ OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3)
+ >;
+ };
+
usb_ulpi_pins: pinmux_usb_ulpi_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x196, MUX_MODE7)
@@ -583,6 +642,11 @@
};
};
+&usbhsohci {
+ phys = <&fsusb1_phy>;
+ phy-names = "usb";
+};
+
&usbhsehci {
phys = <&hsusb2_phy>;
};
--
2.16.2
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 3/3] ARM: dts: omap4-droid4: Configure uart1 pins
2018-03-01 4:01 [PATCH 1/3] ARM: dts: omap4-droid4: Fix USB PHY port naming Tony Lindgren
2018-03-01 4:01 ` [PATCH 2/3] ARM: dts: omap4-droid4: Configure MDM6600 USB PHY Tony Lindgren
@ 2018-03-01 4:01 ` Tony Lindgren
1 sibling, 0 replies; 3+ messages in thread
From: Tony Lindgren @ 2018-03-01 4:01 UTC (permalink / raw)
To: linux-omap; +Cc: Benoît Cousson, devicetree
These are needed to use the n_gsm driver for TS 27.010 UART
multiplexing. Note that support for the OOB wake gpio is still
missing so the UART is not yet usable for n_gsm.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/omap4-droid4-xt894.dts | 33 ++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts
--- a/arch/arm/boot/dts/omap4-droid4-xt894.dts
+++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts
@@ -557,6 +557,28 @@
>;
};
+ /*
+ * Note that the v3.0.8 stock userspace dynamically remuxes uart1
+ * rts pin probably for PM purposes to PIN_INPUT_PULLUP | MUX_MODE7
+ * when not used. If needed, we can add rts pin remux later based
+ * on power measurements.
+ */
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ /* 0x4a10013c mcspi1_cs2.uart1_cts ag23 */
+ OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1)
+
+ /* 0x4a10013e mcspi1_cs3.uart1_rts ah23 */
+ OMAP4_IOPAD(0x13e, MUX_MODE1)
+
+ /* 0x4a100140 uart3_cts_rctx.uart1_tx f27 */
+ OMAP4_IOPAD(0x140, PIN_OUTPUT | MUX_MODE1)
+
+ /* 0x4a1001ca dpm_emu14.uart1_rx aa3 */
+ OMAP4_IOPAD(0x1ca, PIN_INPUT_PULLUP | MUX_MODE2)
+ >;
+ };
+
/* uart3_tx_irtx and uart3_rx_irrx */
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
@@ -626,6 +648,17 @@
};
};
+/*
+ * As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for
+ * uart1 wakeirq.
+ */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core 0xfc>;
+};
+
&uart3 {
interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core 0x17c>;
--
2.16.2
^ permalink raw reply [flat|nested] 3+ messages in thread
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2018-03-01 4:01 [PATCH 1/3] ARM: dts: omap4-droid4: Fix USB PHY port naming Tony Lindgren
2018-03-01 4:01 ` [PATCH 2/3] ARM: dts: omap4-droid4: Configure MDM6600 USB PHY Tony Lindgren
2018-03-01 4:01 ` [PATCH 3/3] ARM: dts: omap4-droid4: Configure uart1 pins Tony Lindgren
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