* [PATCH v3 0/4] Qcom smmu-500 wait-for-safe handling for sdm845 @ 2019-06-12 7:15 Vivek Gautam 2019-06-12 7:15 ` [PATCH v3 1/4] firmware: qcom_scm-64: Add atomic version of qcom_scm_call Vivek Gautam ` (3 more replies) 0 siblings, 4 replies; 25+ messages in thread From: Vivek Gautam @ 2019-06-12 7:15 UTC (permalink / raw) To: agross, robh+dt, will.deacon, robin.murphy, joro, bjorn.andersson, linux-arm-msm, devicetree, iommu Cc: linux-kernel, david.brown, Vivek Gautam Subject changed, older subject was - Qcom smmu-500 TLB invalidation errata for sdm845. Previous version of the patches are at [1]: Qcom's implementation of smmu-500 on sdm845 adds a hardware logic called wait-for-safe. This logic helps in meeting the invalidation requirements from 'real-time clients', such as display and camera. This wait-for-safe logic ensures that the invalidations happen after getting an ack from these devices. In this patch-series we are disabling this wait-for-safe logic from the arm-smmu driver's probe as with this enabled the hardware tries to throttle invalidations from 'non-real-time clients', such as USB and UFS. For detailed information please refer to patch [3/4] in this series. I have included the device tree patch too in this series for someone who would like to test out this. Here's a branch [2] that gets display on MTP SDM845 device. This patch series is inspired from downstream work to handle under-performance issues on real-time clients on sdm845. In downstream we add separate page table ops to handle TLB maintenance and toggle wait-for-safe in tlb_sync call so that achieve required performance for display and camera [3, 4]. Changes since v2: * Dropped the patch to add atomic io_read/write scm API. * Removed support for any separate page table ops to handle wait-for-safe. Currently just disabling this wait-for-safe logic from arm_smmu_device_probe() to achieve performance on USB/UFS on sdm845. * Added a device tree patch to add smmu option for fw-implemented support for SCM call to take care of SAFE toggling. Changes since v1: * Addressed Will and Robin's comments: - Dropped the patch[4] that forked out __arm_smmu_tlb_inv_range_nosync(), and __arm_smmu_tlb_sync(). - Cleaned up the errata patch further to use downstream polling mechanism for tlb sync. * No change in SCM call patches - patches 1 to 3. [1] https://lore.kernel.org/patchwork/cover/983913/ [2] https://github.com/vivekgautam1/linux/tree/v5.2-rc4/sdm845-display-working [3] https://source.codeaurora.org/quic/la/kernel/msm-4.9/commit/drivers/iommu/arm-smmu.c?h=CogSystems-msm-49/msm-4.9&id=da765c6c75266b38191b38ef086274943f353ea7 [4] https://source.codeaurora.org/quic/la/kernel/msm-4.9/commit/drivers/iommu/arm-smmu.c?h=CogSystems-msm-49/msm-4.9&id=8696005aaaf745de68f57793c1a534a34345c30a Vivek Gautam (4): firmware: qcom_scm-64: Add atomic version of qcom_scm_call firmware/qcom_scm: Add scm call to handle smmu errata iommu/arm-smmu: Add support to handle Qcom's wait-for-safe logic arm64: dts/sdm845: Enable FW implemented safe sequence handler on MTP arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + drivers/firmware/qcom_scm-32.c | 5 ++ drivers/firmware/qcom_scm-64.c | 149 ++++++++++++++++++++++++----------- drivers/firmware/qcom_scm.c | 6 ++ drivers/firmware/qcom_scm.h | 5 ++ drivers/iommu/arm-smmu.c | 16 ++++ include/linux/qcom_scm.h | 2 + 7 files changed, 140 insertions(+), 44 deletions(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 1/4] firmware: qcom_scm-64: Add atomic version of qcom_scm_call 2019-06-12 7:15 [PATCH v3 0/4] Qcom smmu-500 wait-for-safe handling for sdm845 Vivek Gautam @ 2019-06-12 7:15 ` Vivek Gautam 2019-06-18 17:55 ` Will Deacon 2019-06-12 7:15 ` [PATCH v3 2/4] firmware/qcom_scm: Add scm call to handle smmu errata Vivek Gautam ` (2 subsequent siblings) 3 siblings, 1 reply; 25+ messages in thread From: Vivek Gautam @ 2019-06-12 7:15 UTC (permalink / raw) To: agross, robh+dt, will.deacon, robin.murphy, joro, bjorn.andersson, linux-arm-msm, devicetree, iommu Cc: linux-kernel, david.brown, Vivek Gautam There are scnenarios where drivers are required to make a scm call in atomic context, such as in one of the qcom's arm-smmu-500 errata [1]. [1] ("https://source.codeaurora.org/quic/la/kernel/msm-4.9/commit/ drivers/iommu/arm-smmu.c?h=CogSystems-msm-49/ msm-4.9&id=da765c6c75266b38191b38ef086274943f353ea7") Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- drivers/firmware/qcom_scm-64.c | 136 ++++++++++++++++++++++++++++------------- 1 file changed, 92 insertions(+), 44 deletions(-) diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index 91d5ad7cf58b..b6dca32c5ac4 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -62,32 +62,71 @@ static DEFINE_MUTEX(qcom_scm_lock); #define FIRST_EXT_ARG_IDX 3 #define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1) -/** - * qcom_scm_call() - Invoke a syscall in the secure world - * @dev: device - * @svc_id: service identifier - * @cmd_id: command identifier - * @desc: Descriptor structure containing arguments and return values - * - * Sends a command to the SCM and waits for the command to finish processing. - * This should *only* be called in pre-emptible context. -*/ -static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, - const struct qcom_scm_desc *desc, - struct arm_smccc_res *res) +static void __qcom_scm_call_do(const struct qcom_scm_desc *desc, + struct arm_smccc_res *res, u32 fn_id, + u64 x5, u32 type) +{ + u64 cmd; + struct arm_smccc_quirk quirk = {.id = ARM_SMCCC_QUIRK_QCOM_A6}; + + cmd = ARM_SMCCC_CALL_VAL(type, qcom_smccc_convention, + ARM_SMCCC_OWNER_SIP, fn_id); + + quirk.state.a6 = 0; + + do { + arm_smccc_smc_quirk(cmd, desc->arginfo, desc->args[0], + desc->args[1], desc->args[2], x5, + quirk.state.a6, 0, res, &quirk); + + if (res->a0 == QCOM_SCM_INTERRUPTED) + cmd = res->a0; + + } while (res->a0 == QCOM_SCM_INTERRUPTED); +} + +static void qcom_scm_call_do(const struct qcom_scm_desc *desc, + struct arm_smccc_res *res, u32 fn_id, + u64 x5, bool atomic) +{ + int retry_count = 0; + + if (!atomic) { + do { + mutex_lock(&qcom_scm_lock); + + __qcom_scm_call_do(desc, res, fn_id, x5, + ARM_SMCCC_STD_CALL); + + mutex_unlock(&qcom_scm_lock); + + if (res->a0 == QCOM_SCM_V2_EBUSY) { + if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY) + break; + msleep(QCOM_SCM_EBUSY_WAIT_MS); + } + } while (res->a0 == QCOM_SCM_V2_EBUSY); + } else { + __qcom_scm_call_do(desc, res, fn_id, x5, ARM_SMCCC_FAST_CALL); + } +} + +static int ___qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, + const struct qcom_scm_desc *desc, + struct arm_smccc_res *res, bool atomic) { int arglen = desc->arginfo & 0xf; - int retry_count = 0, i; + int i; u32 fn_id = QCOM_SCM_FNID(svc_id, cmd_id); - u64 cmd, x5 = desc->args[FIRST_EXT_ARG_IDX]; + u64 x5 = desc->args[FIRST_EXT_ARG_IDX]; dma_addr_t args_phys = 0; void *args_virt = NULL; size_t alloc_len; - struct arm_smccc_quirk quirk = {.id = ARM_SMCCC_QUIRK_QCOM_A6}; + gfp_t flag = atomic ? GFP_ATOMIC : GFP_KERNEL; if (unlikely(arglen > N_REGISTER_ARGS)) { alloc_len = N_EXT_QCOM_SCM_ARGS * sizeof(u64); - args_virt = kzalloc(PAGE_ALIGN(alloc_len), GFP_KERNEL); + args_virt = kzalloc(PAGE_ALIGN(alloc_len), flag); if (!args_virt) return -ENOMEM; @@ -117,33 +156,7 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, x5 = args_phys; } - do { - mutex_lock(&qcom_scm_lock); - - cmd = ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, - qcom_smccc_convention, - ARM_SMCCC_OWNER_SIP, fn_id); - - quirk.state.a6 = 0; - - do { - arm_smccc_smc_quirk(cmd, desc->arginfo, desc->args[0], - desc->args[1], desc->args[2], x5, - quirk.state.a6, 0, res, &quirk); - - if (res->a0 == QCOM_SCM_INTERRUPTED) - cmd = res->a0; - - } while (res->a0 == QCOM_SCM_INTERRUPTED); - - mutex_unlock(&qcom_scm_lock); - - if (res->a0 == QCOM_SCM_V2_EBUSY) { - if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY) - break; - msleep(QCOM_SCM_EBUSY_WAIT_MS); - } - } while (res->a0 == QCOM_SCM_V2_EBUSY); + qcom_scm_call_do(desc, res, fn_id, x5, atomic); if (args_virt) { dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE); @@ -156,6 +169,41 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, return 0; } +/** + * qcom_scm_call() - Invoke a syscall in the secure world + * @dev: device + * @svc_id: service identifier + * @cmd_id: command identifier + * @desc: Descriptor structure containing arguments and return values + * + * Sends a command to the SCM and waits for the command to finish processing. + * This should *only* be called in pre-emptible context. + */ +static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, + const struct qcom_scm_desc *desc, + struct arm_smccc_res *res) +{ + return ___qcom_scm_call(dev, svc_id, cmd_id, desc, res, false); +} + +/** + * qcom_scm_call_atomic() - atomic variation of qcom_scm_call() + * @dev: device + * @svc_id: service identifier + * @cmd_id: command identifier + * @desc: Descriptor structure containing arguments and return values + * @res: Structure containing results from SMC/HVC call + * + * Sends a command to the SCM and waits for the command to finish processing. + * This should be called in atomic context only. + */ +static int qcom_scm_call_atomic(struct device *dev, u32 svc_id, u32 cmd_id, + const struct qcom_scm_desc *desc, + struct arm_smccc_res *res) +{ + return ___qcom_scm_call(dev, svc_id, cmd_id, desc, res, true); +} + /** * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus * @entry: Entry point function for the cpus -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v3 1/4] firmware: qcom_scm-64: Add atomic version of qcom_scm_call 2019-06-12 7:15 ` [PATCH v3 1/4] firmware: qcom_scm-64: Add atomic version of qcom_scm_call Vivek Gautam @ 2019-06-18 17:55 ` Will Deacon [not found] ` <20190618175536.GI4270-UDVVEH7NWB15pKCnmE3YQBJ8xKzm50AiAL8bYrjMMd8@public.gmane.org> 0 siblings, 1 reply; 25+ messages in thread From: Will Deacon @ 2019-06-18 17:55 UTC (permalink / raw) To: Vivek Gautam Cc: agross, robh+dt, robin.murphy, joro, bjorn.andersson, linux-arm-msm, devicetree, iommu, linux-kernel, david.brown On Wed, Jun 12, 2019 at 12:45:51PM +0530, Vivek Gautam wrote: > There are scnenarios where drivers are required to make a > scm call in atomic context, such as in one of the qcom's > arm-smmu-500 errata [1]. > > [1] ("https://source.codeaurora.org/quic/la/kernel/msm-4.9/commit/ > drivers/iommu/arm-smmu.c?h=CogSystems-msm-49/ > msm-4.9&id=da765c6c75266b38191b38ef086274943f353ea7") > > Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > drivers/firmware/qcom_scm-64.c | 136 ++++++++++++++++++++++++++++------------- > 1 file changed, 92 insertions(+), 44 deletions(-) > > diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c > index 91d5ad7cf58b..b6dca32c5ac4 100644 > --- a/drivers/firmware/qcom_scm-64.c > +++ b/drivers/firmware/qcom_scm-64.c > @@ -62,32 +62,71 @@ static DEFINE_MUTEX(qcom_scm_lock); > #define FIRST_EXT_ARG_IDX 3 > #define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1) > > -/** > - * qcom_scm_call() - Invoke a syscall in the secure world > - * @dev: device > - * @svc_id: service identifier > - * @cmd_id: command identifier > - * @desc: Descriptor structure containing arguments and return values > - * > - * Sends a command to the SCM and waits for the command to finish processing. > - * This should *only* be called in pre-emptible context. > -*/ > -static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, > - const struct qcom_scm_desc *desc, > - struct arm_smccc_res *res) > +static void __qcom_scm_call_do(const struct qcom_scm_desc *desc, > + struct arm_smccc_res *res, u32 fn_id, > + u64 x5, u32 type) > +{ > + u64 cmd; > + struct arm_smccc_quirk quirk = {.id = ARM_SMCCC_QUIRK_QCOM_A6}; > + > + cmd = ARM_SMCCC_CALL_VAL(type, qcom_smccc_convention, > + ARM_SMCCC_OWNER_SIP, fn_id); > + > + quirk.state.a6 = 0; > + > + do { > + arm_smccc_smc_quirk(cmd, desc->arginfo, desc->args[0], > + desc->args[1], desc->args[2], x5, > + quirk.state.a6, 0, res, &quirk); > + > + if (res->a0 == QCOM_SCM_INTERRUPTED) > + cmd = res->a0; > + > + } while (res->a0 == QCOM_SCM_INTERRUPTED); > +} > + > +static void qcom_scm_call_do(const struct qcom_scm_desc *desc, > + struct arm_smccc_res *res, u32 fn_id, > + u64 x5, bool atomic) > +{ Maybe pass in the call type (ARM_SMCCC_FAST_CALL vs ARM_SMCCC_STD_CALL) instead of "bool atomic"? Would certainly make the callsites easier to understand. > + int retry_count = 0; > + > + if (!atomic) { > + do { > + mutex_lock(&qcom_scm_lock); > + > + __qcom_scm_call_do(desc, res, fn_id, x5, > + ARM_SMCCC_STD_CALL); > + > + mutex_unlock(&qcom_scm_lock); > + > + if (res->a0 == QCOM_SCM_V2_EBUSY) { > + if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY) > + break; > + msleep(QCOM_SCM_EBUSY_WAIT_MS); > + } > + } while (res->a0 == QCOM_SCM_V2_EBUSY); > + } else { > + __qcom_scm_call_do(desc, res, fn_id, x5, ARM_SMCCC_FAST_CALL); > + } Is it safe to make concurrent FAST calls? Will ^ permalink raw reply [flat|nested] 25+ messages in thread
[parent not found: <20190618175536.GI4270-UDVVEH7NWB15pKCnmE3YQBJ8xKzm50AiAL8bYrjMMd8@public.gmane.org>]
* Re: [PATCH v3 1/4] firmware: qcom_scm-64: Add atomic version of qcom_scm_call [not found] ` <20190618175536.GI4270-UDVVEH7NWB15pKCnmE3YQBJ8xKzm50AiAL8bYrjMMd8@public.gmane.org> @ 2019-06-19 11:34 ` Vivek Gautam 2019-08-05 22:27 ` Bjorn Andersson 0 siblings, 1 reply; 25+ messages in thread From: Vivek Gautam @ 2019-06-19 11:34 UTC (permalink / raw) To: Will Deacon Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm, open list, Bjorn Andersson, David Brown, list-Y9sIeH5OGRo@public.gmane.org:IOMMU DRIVERS <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>, Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>, , robh+dt, Andy Gross, Robin Murphy On Tue, Jun 18, 2019 at 11:25 PM Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote: > > On Wed, Jun 12, 2019 at 12:45:51PM +0530, Vivek Gautam wrote: > > There are scnenarios where drivers are required to make a > > scm call in atomic context, such as in one of the qcom's > > arm-smmu-500 errata [1]. > > > > [1] ("https://source.codeaurora.org/quic/la/kernel/msm-4.9/commit/ > > drivers/iommu/arm-smmu.c?h=CogSystems-msm-49/ > > msm-4.9&id=da765c6c75266b38191b38ef086274943f353ea7") > > > > Signed-off-by: Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> > > Reviewed-by: Bjorn Andersson <bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > > --- > > drivers/firmware/qcom_scm-64.c | 136 ++++++++++++++++++++++++++++------------- > > 1 file changed, 92 insertions(+), 44 deletions(-) > > > > diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c > > index 91d5ad7cf58b..b6dca32c5ac4 100644 > > --- a/drivers/firmware/qcom_scm-64.c > > +++ b/drivers/firmware/qcom_scm-64.c [snip] > > + > > +static void qcom_scm_call_do(const struct qcom_scm_desc *desc, > > + struct arm_smccc_res *res, u32 fn_id, > > + u64 x5, bool atomic) > > +{ > > Maybe pass in the call type (ARM_SMCCC_FAST_CALL vs ARM_SMCCC_STD_CALL) > instead of "bool atomic"? Would certainly make the callsites easier to > understand. Sure, will do that. > > > + int retry_count = 0; > > + > > + if (!atomic) { > > + do { > > + mutex_lock(&qcom_scm_lock); > > + > > + __qcom_scm_call_do(desc, res, fn_id, x5, > > + ARM_SMCCC_STD_CALL); > > + > > + mutex_unlock(&qcom_scm_lock); > > + > > + if (res->a0 == QCOM_SCM_V2_EBUSY) { > > + if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY) > > + break; > > + msleep(QCOM_SCM_EBUSY_WAIT_MS); > > + } > > + } while (res->a0 == QCOM_SCM_V2_EBUSY); > > + } else { > > + __qcom_scm_call_do(desc, res, fn_id, x5, ARM_SMCCC_FAST_CALL); > > + } > > Is it safe to make concurrent FAST calls? I better add a spinlock here. Thanks & regards Vivek > > Will > _______________________________________________ > iommu mailing list > iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 1/4] firmware: qcom_scm-64: Add atomic version of qcom_scm_call 2019-06-19 11:34 ` Vivek Gautam @ 2019-08-05 22:27 ` Bjorn Andersson 2019-08-08 11:35 ` Vivek Gautam 0 siblings, 1 reply; 25+ messages in thread From: Bjorn Andersson @ 2019-08-05 22:27 UTC (permalink / raw) To: Vivek Gautam Cc: Will Deacon, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm, open list, robh+dt, David Brown, list@263.net:IOMMU DRIVERS <iommu@lists.linux-foundation.org>, Joerg Roedel <joro@8bytes.org>,, Andy Gross, Robin Murphy On Wed 19 Jun 04:34 PDT 2019, Vivek Gautam wrote: > On Tue, Jun 18, 2019 at 11:25 PM Will Deacon <will.deacon@arm.com> wrote: > > > > On Wed, Jun 12, 2019 at 12:45:51PM +0530, Vivek Gautam wrote: > > > There are scnenarios where drivers are required to make a > > > scm call in atomic context, such as in one of the qcom's > > > arm-smmu-500 errata [1]. > > > > > > [1] ("https://source.codeaurora.org/quic/la/kernel/msm-4.9/commit/ > > > drivers/iommu/arm-smmu.c?h=CogSystems-msm-49/ > > > msm-4.9&id=da765c6c75266b38191b38ef086274943f353ea7") > > > > > > Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> > > > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > > --- > > > drivers/firmware/qcom_scm-64.c | 136 ++++++++++++++++++++++++++++------------- > > > 1 file changed, 92 insertions(+), 44 deletions(-) > > > > > > diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c > > > index 91d5ad7cf58b..b6dca32c5ac4 100644 > > > --- a/drivers/firmware/qcom_scm-64.c > > > +++ b/drivers/firmware/qcom_scm-64.c > > [snip] > > > > + > > > +static void qcom_scm_call_do(const struct qcom_scm_desc *desc, > > > + struct arm_smccc_res *res, u32 fn_id, > > > + u64 x5, bool atomic) > > > +{ > > > > Maybe pass in the call type (ARM_SMCCC_FAST_CALL vs ARM_SMCCC_STD_CALL) > > instead of "bool atomic"? Would certainly make the callsites easier to > > understand. > > Sure, will do that. > > > > > > + int retry_count = 0; > > > + > > > + if (!atomic) { > > > + do { > > > + mutex_lock(&qcom_scm_lock); > > > + > > > + __qcom_scm_call_do(desc, res, fn_id, x5, > > > + ARM_SMCCC_STD_CALL); > > > + > > > + mutex_unlock(&qcom_scm_lock); > > > + > > > + if (res->a0 == QCOM_SCM_V2_EBUSY) { > > > + if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY) > > > + break; > > > + msleep(QCOM_SCM_EBUSY_WAIT_MS); > > > + } > > > + } while (res->a0 == QCOM_SCM_V2_EBUSY); > > > + } else { > > > + __qcom_scm_call_do(desc, res, fn_id, x5, ARM_SMCCC_FAST_CALL); > > > + } > > > > Is it safe to make concurrent FAST calls? > > I better add a spinlock here. > Hi Vivek, Would you be able to respin this patch, so that we could unblock the introduction of the display nodes in the various device? Regards, Bjorn ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 1/4] firmware: qcom_scm-64: Add atomic version of qcom_scm_call 2019-08-05 22:27 ` Bjorn Andersson @ 2019-08-08 11:35 ` Vivek Gautam 2019-08-08 16:30 ` Will Deacon 0 siblings, 1 reply; 25+ messages in thread From: Vivek Gautam @ 2019-08-08 11:35 UTC (permalink / raw) To: Bjorn Andersson Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm, Will Deacon, open list, David Brown, list-Y9sIeH5OGRo@public.gmane.org:IOMMU DRIVERS <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>, Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>, , robh+dt, Andy Gross, Robin Murphy On Tue, Aug 6, 2019 at 3:58 AM Bjorn Andersson <bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote: > > On Wed 19 Jun 04:34 PDT 2019, Vivek Gautam wrote: > > > On Tue, Jun 18, 2019 at 11:25 PM Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote: > > > > > > On Wed, Jun 12, 2019 at 12:45:51PM +0530, Vivek Gautam wrote: > > > > There are scnenarios where drivers are required to make a > > > > scm call in atomic context, such as in one of the qcom's > > > > arm-smmu-500 errata [1]. > > > > > > > > [1] ("https://source.codeaurora.org/quic/la/kernel/msm-4.9/commit/ > > > > drivers/iommu/arm-smmu.c?h=CogSystems-msm-49/ > > > > msm-4.9&id=da765c6c75266b38191b38ef086274943f353ea7") > > > > > > > > Signed-off-by: Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> > > > > Reviewed-by: Bjorn Andersson <bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > > > > --- > > > > drivers/firmware/qcom_scm-64.c | 136 ++++++++++++++++++++++++++++------------- > > > > 1 file changed, 92 insertions(+), 44 deletions(-) > > > > > > > > diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c > > > > index 91d5ad7cf58b..b6dca32c5ac4 100644 > > > > --- a/drivers/firmware/qcom_scm-64.c > > > > +++ b/drivers/firmware/qcom_scm-64.c > > > > [snip] > > > > > > + > > > > +static void qcom_scm_call_do(const struct qcom_scm_desc *desc, > > > > + struct arm_smccc_res *res, u32 fn_id, > > > > + u64 x5, bool atomic) > > > > +{ > > > > > > Maybe pass in the call type (ARM_SMCCC_FAST_CALL vs ARM_SMCCC_STD_CALL) > > > instead of "bool atomic"? Would certainly make the callsites easier to > > > understand. > > > > Sure, will do that. > > > > > > > > > + int retry_count = 0; > > > > + > > > > + if (!atomic) { > > > > + do { > > > > + mutex_lock(&qcom_scm_lock); > > > > + > > > > + __qcom_scm_call_do(desc, res, fn_id, x5, > > > > + ARM_SMCCC_STD_CALL); > > > > + > > > > + mutex_unlock(&qcom_scm_lock); > > > > + > > > > + if (res->a0 == QCOM_SCM_V2_EBUSY) { > > > > + if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY) > > > > + break; > > > > + msleep(QCOM_SCM_EBUSY_WAIT_MS); > > > > + } > > > > + } while (res->a0 == QCOM_SCM_V2_EBUSY); > > > > + } else { > > > > + __qcom_scm_call_do(desc, res, fn_id, x5, ARM_SMCCC_FAST_CALL); > > > > + } > > > > > > Is it safe to make concurrent FAST calls? > > > > I better add a spinlock here. > > > > Hi Vivek, > > Would you be able to respin this patch, so that we could unblock the > introduction of the display nodes in the various device? Will pointed [1] to the restructuring of arm-smmu to support implementation specific details. That hasn't been posted yet, and I haven't yet been able to work on that either. I will be happy to respin this series with the comments addressed if Will is okay to pull changes to unblock sdm845 devices. :) [1] https://lore.kernel.org/patchwork/patch/1087457/ Thanks & Regards Vivek > > Regards, > Bjorn > _______________________________________________ > iommu mailing list > iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 1/4] firmware: qcom_scm-64: Add atomic version of qcom_scm_call 2019-08-08 11:35 ` Vivek Gautam @ 2019-08-08 16:30 ` Will Deacon 0 siblings, 0 replies; 25+ messages in thread From: Will Deacon @ 2019-08-08 16:30 UTC (permalink / raw) To: Vivek Gautam Cc: Bjorn Andersson, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm, Will Deacon, open list, David Brown, list@263.net:IOMMU DRIVERS <iommu@lists.linux-foundation.org>, Joerg Roedel <joro@8bytes.org>,, robh+dt, Andy Gross, Robin Murphy On Thu, Aug 08, 2019 at 05:05:21PM +0530, Vivek Gautam wrote: > On Tue, Aug 6, 2019 at 3:58 AM Bjorn Andersson > <bjorn.andersson@linaro.org> wrote: > > Would you be able to respin this patch, so that we could unblock the > > introduction of the display nodes in the various device? > > Will pointed [1] to the restructuring of arm-smmu to support > implementation specific details. > That hasn't been posted yet, and I haven't yet been able to work on that either. > I will be happy to respin this series with the comments addressed if > Will is okay to pull changes to unblock sdm845 devices. :) > > [1] https://lore.kernel.org/patchwork/patch/1087457/ Just checked with Robin, and he's planning to post something tomorrow. Will ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 2/4] firmware/qcom_scm: Add scm call to handle smmu errata 2019-06-12 7:15 [PATCH v3 0/4] Qcom smmu-500 wait-for-safe handling for sdm845 Vivek Gautam 2019-06-12 7:15 ` [PATCH v3 1/4] firmware: qcom_scm-64: Add atomic version of qcom_scm_call Vivek Gautam @ 2019-06-12 7:15 ` Vivek Gautam 2019-06-12 7:15 ` [PATCH v3 3/4] iommu/arm-smmu: Add support to handle Qcom's wait-for-safe logic Vivek Gautam 2019-06-12 7:15 ` [PATCH v3 4/4] arm64: dts/sdm845: Enable FW implemented safe sequence handler on MTP Vivek Gautam 3 siblings, 0 replies; 25+ messages in thread From: Vivek Gautam @ 2019-06-12 7:15 UTC (permalink / raw) To: agross, robh+dt, will.deacon, robin.murphy, joro, bjorn.andersson, linux-arm-msm, devicetree, iommu Cc: linux-kernel, david.brown, Vivek Gautam Qcom's smmu-500 needs to toggle wait-for-safe logic to handle TLB invalidations. Few firmwares allow doing that through SCM interface. Add API to toggle wait for safe from firmware through a SCM call. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- drivers/firmware/qcom_scm-32.c | 5 +++++ drivers/firmware/qcom_scm-64.c | 13 +++++++++++++ drivers/firmware/qcom_scm.c | 6 ++++++ drivers/firmware/qcom_scm.h | 5 +++++ include/linux/qcom_scm.h | 2 ++ 5 files changed, 31 insertions(+) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index 215061c581e1..bee8729525ec 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -614,3 +614,8 @@ int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val) return qcom_scm_call_atomic2(QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE, addr, val); } + +int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool enable) +{ + return -ENODEV; +} diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index b6dca32c5ac4..23de54b75cd7 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -550,3 +550,16 @@ int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val) return qcom_scm_call(dev, QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE, &desc, &res); } + +int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool en) +{ + struct qcom_scm_desc desc = {0}; + struct arm_smccc_res res; + + desc.args[0] = QCOM_SCM_CONFIG_SAFE_EN_CLIENT_ALL; + desc.args[1] = en; + desc.arginfo = QCOM_SCM_ARGS(2); + + return qcom_scm_call_atomic(dev, QCOM_SCM_SVC_SMMU_PROGRAM, + QCOM_SCM_CONFIG_SAFE_EN, &desc, &res); +} diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 2ddc118dba1b..2b3b7a8c4270 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -344,6 +344,12 @@ int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) } EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init); +int qcom_scm_qsmmu500_wait_safe_toggle(bool en) +{ + return __qcom_scm_qsmmu500_wait_safe_toggle(__scm->dev, en); +} +EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle); + int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return __qcom_scm_io_readl(__scm->dev, addr, val); diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 99506bd873c0..0b63ded89b41 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -91,10 +91,15 @@ extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare); #define QCOM_SCM_IOMMU_SECURE_PTBL_SIZE 3 #define QCOM_SCM_IOMMU_SECURE_PTBL_INIT 4 +#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15 +#define QCOM_SCM_CONFIG_SAFE_EN 0x3 +#define QCOM_SCM_CONFIG_SAFE_EN_CLIENT_ALL 0x2 extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare, size_t *size); extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size, u32 spare); +extern int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, + bool enable); #define QCOM_MEM_PROT_ASSIGN_ID 0x16 extern int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, size_t mem_sz, diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index 3f12cc77fb58..aee3d8580d89 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -57,6 +57,7 @@ extern int qcom_scm_set_remote_state(u32 state, u32 id); extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare); extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size); extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare); +extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en); extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); #else @@ -96,6 +97,7 @@ qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; } static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; } static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; } static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; } +static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en) { return -ENODEV; } static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; } static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; } #endif -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 3/4] iommu/arm-smmu: Add support to handle Qcom's wait-for-safe logic 2019-06-12 7:15 [PATCH v3 0/4] Qcom smmu-500 wait-for-safe handling for sdm845 Vivek Gautam 2019-06-12 7:15 ` [PATCH v3 1/4] firmware: qcom_scm-64: Add atomic version of qcom_scm_call Vivek Gautam 2019-06-12 7:15 ` [PATCH v3 2/4] firmware/qcom_scm: Add scm call to handle smmu errata Vivek Gautam @ 2019-06-12 7:15 ` Vivek Gautam [not found] ` <20190612071554.13573-4-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2019-06-12 7:15 ` [PATCH v3 4/4] arm64: dts/sdm845: Enable FW implemented safe sequence handler on MTP Vivek Gautam 3 siblings, 1 reply; 25+ messages in thread From: Vivek Gautam @ 2019-06-12 7:15 UTC (permalink / raw) To: agross, robh+dt, will.deacon, robin.murphy, joro, bjorn.andersson, linux-arm-msm, devicetree, iommu Cc: linux-kernel, david.brown, Vivek Gautam Qcom's implementation of arm,mmu-500 adds a WAIT-FOR-SAFE logic to address under-performance issues in real-time clients, such as Display, and Camera. On receiving an invalidation requests, the SMMU forwards SAFE request to these clients and waits for SAFE ack signal from real-time clients. The SAFE signal from such clients is used to qualify the start of invalidation. This logic is controlled by chicken bits, one for each - MDP (display), IFE0, and IFE1 (camera), that can be accessed only from secure software on sdm845. This configuration, however, degrades the performance of non-real time clients, such as USB, and UFS etc. This happens because, with wait-for-safe logic enabled the hardware tries to throttle non-real time clients while waiting for SAFE ack signals from real-time clients. On MTP sdm845 devices, with wait-for-safe logic enabled at the boot time by the bootloaders we see degraded performance of USB and UFS when kernel enables the smmu stage-1 translations for these clients. Turn off this wait-for-safe logic from the kernel gets us back the perf of USB and UFS devices until we re-visit this when we start seeing perf issues on display/camera on upstream supported SDM845 platforms. Now, different bootloaders with their access control policies allow this register access differently through secure monitor calls - 1) With one we can issue io-read/write secure monitor call (qcom-scm) to update the register, while, 2) With other, such as one on MTP sdm845 we should use the specific qcom-scm command to send request to do the complete register configuration. Adding a separate device tree flag for arm-smmu to identify which firmware configuration of the two mentioned above we use. Not adding code change to allow type-(1) bootloaders to toggle the safe using io-read/write qcom-scm call. This change is inspired by the downstream change from Patrick Daly to address performance issues with display and camera by handling this wait-for-safe within separte io-pagetable ops to do TLB maintenance. So a big thanks to him for the change. Without this change the UFS reads are pretty slow: $ time dd if=/dev/sda of=/dev/zero bs=1048576 count=10 conv=sync 10+0 records in 10+0 records out 10485760 bytes (10.0MB) copied, 22.394903 seconds, 457.2KB/s real 0m 22.39s user 0m 0.00s sys 0m 0.01s With this change they are back to rock! $ time dd if=/dev/sda of=/dev/zero bs=1048576 count=300 conv=sync 300+0 records in 300+0 records out 314572800 bytes (300.0MB) copied, 1.030541 seconds, 291.1MB/s real 0m 1.03s user 0m 0.00s sys 0m 0.54s Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> --- drivers/iommu/arm-smmu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 0ad086da399c..3c3ad43eda97 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -39,6 +39,7 @@ #include <linux/pci.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> +#include <linux/qcom_scm.h> #include <linux/slab.h> #include <linux/spinlock.h> @@ -177,6 +178,7 @@ struct arm_smmu_device { u32 features; #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0) +#define ARM_SMMU_OPT_QCOM_FW_IMPL_SAFE_ERRATA (1 << 1) u32 options; enum arm_smmu_arch_version version; enum arm_smmu_implementation model; @@ -262,6 +264,7 @@ static bool using_legacy_binding, using_generic_binding; static struct arm_smmu_option_prop arm_smmu_options[] = { { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, + { ARM_SMMU_OPT_QCOM_FW_IMPL_SAFE_ERRATA, "qcom,smmu-500-fw-impl-safe-errata" }, { 0, NULL}, }; @@ -2292,6 +2295,19 @@ static int arm_smmu_device_probe(struct platform_device *pdev) arm_smmu_device_reset(smmu); arm_smmu_test_smr_masks(smmu); + /* + * To address performance degradation in non-real time clients, + * such as USB and UFS, turn off wait-for-safe on sdm845 platforms, + * such as MTP, whose firmwares implement corresponding secure monitor + * call handlers. + */ + if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm845-smmu-500") && + smmu->options & ARM_SMMU_OPT_QCOM_FW_IMPL_SAFE_ERRATA) { + err = qcom_scm_qsmmu500_wait_safe_toggle(0); + if (err) + dev_warn(dev, "Failed to turn off SAFE logic\n"); + } + /* * We want to avoid touching dev->power.lock in fastpaths unless * it's really going to do something useful - pm_runtime_enabled() -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 25+ messages in thread
[parent not found: <20190612071554.13573-4-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>]
* Re: [PATCH v3 3/4] iommu/arm-smmu: Add support to handle Qcom's wait-for-safe logic [not found] ` <20190612071554.13573-4-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> @ 2019-06-14 4:05 ` Bjorn Andersson 2019-06-14 9:18 ` Vivek Gautam 0 siblings, 1 reply; 25+ messages in thread From: Bjorn Andersson @ 2019-06-14 4:05 UTC (permalink / raw) To: Vivek Gautam Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA, will.deacon-5wv7dgnIgG8, linux-kernel-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, david.brown-QSEj5FYQhm4dnm+yROfE0A, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, agross-DgEjT+Ai2ygdnm+yROfE0A, robin.murphy-5wv7dgnIgG8 On Wed 12 Jun 00:15 PDT 2019, Vivek Gautam wrote: > Qcom's implementation of arm,mmu-500 adds a WAIT-FOR-SAFE logic > to address under-performance issues in real-time clients, such as > Display, and Camera. > On receiving an invalidation requests, the SMMU forwards SAFE request > to these clients and waits for SAFE ack signal from real-time clients. > The SAFE signal from such clients is used to qualify the start of > invalidation. > This logic is controlled by chicken bits, one for each - MDP (display), > IFE0, and IFE1 (camera), that can be accessed only from secure software > on sdm845. > > This configuration, however, degrades the performance of non-real time > clients, such as USB, and UFS etc. This happens because, with wait-for-safe > logic enabled the hardware tries to throttle non-real time clients while > waiting for SAFE ack signals from real-time clients. > > On MTP sdm845 devices, with wait-for-safe logic enabled at the boot time > by the bootloaders we see degraded performance of USB and UFS when kernel > enables the smmu stage-1 translations for these clients. > Turn off this wait-for-safe logic from the kernel gets us back the perf > of USB and UFS devices until we re-visit this when we start seeing perf > issues on display/camera on upstream supported SDM845 platforms. > > Now, different bootloaders with their access control policies allow this > register access differently through secure monitor calls - > 1) With one we can issue io-read/write secure monitor call (qcom-scm) > to update the register, while, > 2) With other, such as one on MTP sdm845 we should use the specific > qcom-scm command to send request to do the complete register > configuration. > Adding a separate device tree flag for arm-smmu to identify which > firmware configuration of the two mentioned above we use. > Not adding code change to allow type-(1) bootloaders to toggle the > safe using io-read/write qcom-scm call. > > This change is inspired by the downstream change from Patrick Daly > to address performance issues with display and camera by handling > this wait-for-safe within separte io-pagetable ops to do TLB > maintenance. So a big thanks to him for the change. > > Without this change the UFS reads are pretty slow: > $ time dd if=/dev/sda of=/dev/zero bs=1048576 count=10 conv=sync > 10+0 records in > 10+0 records out > 10485760 bytes (10.0MB) copied, 22.394903 seconds, 457.2KB/s > real 0m 22.39s > user 0m 0.00s > sys 0m 0.01s > > With this change they are back to rock! > $ time dd if=/dev/sda of=/dev/zero bs=1048576 count=300 conv=sync > 300+0 records in > 300+0 records out > 314572800 bytes (300.0MB) copied, 1.030541 seconds, 291.1MB/s > real 0m 1.03s > user 0m 0.00s > sys 0m 0.54s > > Signed-off-by: Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> > --- > drivers/iommu/arm-smmu.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > index 0ad086da399c..3c3ad43eda97 100644 > --- a/drivers/iommu/arm-smmu.c > +++ b/drivers/iommu/arm-smmu.c > @@ -39,6 +39,7 @@ > #include <linux/pci.h> > #include <linux/platform_device.h> > #include <linux/pm_runtime.h> > +#include <linux/qcom_scm.h> > #include <linux/slab.h> > #include <linux/spinlock.h> > > @@ -177,6 +178,7 @@ struct arm_smmu_device { > u32 features; > > #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0) > +#define ARM_SMMU_OPT_QCOM_FW_IMPL_SAFE_ERRATA (1 << 1) > u32 options; > enum arm_smmu_arch_version version; > enum arm_smmu_implementation model; > @@ -262,6 +264,7 @@ static bool using_legacy_binding, using_generic_binding; > > static struct arm_smmu_option_prop arm_smmu_options[] = { > { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, > + { ARM_SMMU_OPT_QCOM_FW_IMPL_SAFE_ERRATA, "qcom,smmu-500-fw-impl-safe-errata" }, This should be added to the DT binding as well. > { 0, NULL}, > }; > > @@ -2292,6 +2295,19 @@ static int arm_smmu_device_probe(struct platform_device *pdev) > arm_smmu_device_reset(smmu); > arm_smmu_test_smr_masks(smmu); > > + /* > + * To address performance degradation in non-real time clients, > + * such as USB and UFS, turn off wait-for-safe on sdm845 platforms, > + * such as MTP, whose firmwares implement corresponding secure monitor > + * call handlers. > + */ > + if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm845-smmu-500") && > + smmu->options & ARM_SMMU_OPT_QCOM_FW_IMPL_SAFE_ERRATA) { > + err = qcom_scm_qsmmu500_wait_safe_toggle(0); > + if (err) > + dev_warn(dev, "Failed to turn off SAFE logic\n"); > + } > + This looks good, I presume at some point we can profile things and review if it's worth toggling this on the fly, but given that this is conditioned on smmu->options that should be an implementation detail.. Reviewed-by: Bjorn Andersson <bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> Regards, Bjorn > /* > * We want to avoid touching dev->power.lock in fastpaths unless > * it's really going to do something useful - pm_runtime_enabled() > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation > ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/4] iommu/arm-smmu: Add support to handle Qcom's wait-for-safe logic 2019-06-14 4:05 ` Bjorn Andersson @ 2019-06-14 9:18 ` Vivek Gautam 2019-06-18 17:52 ` Will Deacon 0 siblings, 1 reply; 25+ messages in thread From: Vivek Gautam @ 2019-06-14 9:18 UTC (permalink / raw) To: Bjorn Andersson, will.deacon, robin.murphy Cc: agross, robh+dt, joro, linux-arm-msm, devicetree, iommu, linux-kernel, david.brown On 6/14/2019 9:35 AM, Bjorn Andersson wrote: > On Wed 12 Jun 00:15 PDT 2019, Vivek Gautam wrote: > >> Qcom's implementation of arm,mmu-500 adds a WAIT-FOR-SAFE logic >> to address under-performance issues in real-time clients, such as >> Display, and Camera. >> On receiving an invalidation requests, the SMMU forwards SAFE request >> to these clients and waits for SAFE ack signal from real-time clients. >> The SAFE signal from such clients is used to qualify the start of >> invalidation. >> This logic is controlled by chicken bits, one for each - MDP (display), >> IFE0, and IFE1 (camera), that can be accessed only from secure software >> on sdm845. >> >> This configuration, however, degrades the performance of non-real time >> clients, such as USB, and UFS etc. This happens because, with wait-for-safe >> logic enabled the hardware tries to throttle non-real time clients while >> waiting for SAFE ack signals from real-time clients. >> >> On MTP sdm845 devices, with wait-for-safe logic enabled at the boot time >> by the bootloaders we see degraded performance of USB and UFS when kernel >> enables the smmu stage-1 translations for these clients. >> Turn off this wait-for-safe logic from the kernel gets us back the perf >> of USB and UFS devices until we re-visit this when we start seeing perf >> issues on display/camera on upstream supported SDM845 platforms. >> >> Now, different bootloaders with their access control policies allow this >> register access differently through secure monitor calls - >> 1) With one we can issue io-read/write secure monitor call (qcom-scm) >> to update the register, while, >> 2) With other, such as one on MTP sdm845 we should use the specific >> qcom-scm command to send request to do the complete register >> configuration. >> Adding a separate device tree flag for arm-smmu to identify which >> firmware configuration of the two mentioned above we use. >> Not adding code change to allow type-(1) bootloaders to toggle the >> safe using io-read/write qcom-scm call. >> >> This change is inspired by the downstream change from Patrick Daly >> to address performance issues with display and camera by handling >> this wait-for-safe within separte io-pagetable ops to do TLB >> maintenance. So a big thanks to him for the change. >> >> Without this change the UFS reads are pretty slow: >> $ time dd if=/dev/sda of=/dev/zero bs=1048576 count=10 conv=sync >> 10+0 records in >> 10+0 records out >> 10485760 bytes (10.0MB) copied, 22.394903 seconds, 457.2KB/s >> real 0m 22.39s >> user 0m 0.00s >> sys 0m 0.01s >> >> With this change they are back to rock! >> $ time dd if=/dev/sda of=/dev/zero bs=1048576 count=300 conv=sync >> 300+0 records in >> 300+0 records out >> 314572800 bytes (300.0MB) copied, 1.030541 seconds, 291.1MB/s >> real 0m 1.03s >> user 0m 0.00s >> sys 0m 0.54s >> >> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> >> --- >> drivers/iommu/arm-smmu.c | 16 ++++++++++++++++ >> 1 file changed, 16 insertions(+) >> >> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c >> index 0ad086da399c..3c3ad43eda97 100644 >> --- a/drivers/iommu/arm-smmu.c >> +++ b/drivers/iommu/arm-smmu.c >> @@ -39,6 +39,7 @@ >> #include <linux/pci.h> >> #include <linux/platform_device.h> >> #include <linux/pm_runtime.h> >> +#include <linux/qcom_scm.h> >> #include <linux/slab.h> >> #include <linux/spinlock.h> >> >> @@ -177,6 +178,7 @@ struct arm_smmu_device { >> u32 features; >> >> #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0) >> +#define ARM_SMMU_OPT_QCOM_FW_IMPL_SAFE_ERRATA (1 << 1) >> u32 options; >> enum arm_smmu_arch_version version; >> enum arm_smmu_implementation model; >> @@ -262,6 +264,7 @@ static bool using_legacy_binding, using_generic_binding; >> >> static struct arm_smmu_option_prop arm_smmu_options[] = { >> { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, >> + { ARM_SMMU_OPT_QCOM_FW_IMPL_SAFE_ERRATA, "qcom,smmu-500-fw-impl-safe-errata" }, > This should be added to the DT binding as well. Ah right. I missed that. Will add this and respin unless Robin and Will have concerns with this change. > >> { 0, NULL}, >> }; >> >> @@ -2292,6 +2295,19 @@ static int arm_smmu_device_probe(struct platform_device *pdev) >> arm_smmu_device_reset(smmu); >> arm_smmu_test_smr_masks(smmu); >> >> + /* >> + * To address performance degradation in non-real time clients, >> + * such as USB and UFS, turn off wait-for-safe on sdm845 platforms, >> + * such as MTP, whose firmwares implement corresponding secure monitor >> + * call handlers. >> + */ >> + if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm845-smmu-500") && >> + smmu->options & ARM_SMMU_OPT_QCOM_FW_IMPL_SAFE_ERRATA) { >> + err = qcom_scm_qsmmu500_wait_safe_toggle(0); >> + if (err) >> + dev_warn(dev, "Failed to turn off SAFE logic\n"); >> + } >> + > This looks good, I presume at some point we can profile things and > review if it's worth toggling this on the fly, but given that this is > conditioned on smmu->options that should be an implementation detail.. > > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Thanks Bjorn. Best regards Vivek > Regards, > Bjorn > >> /* >> * We want to avoid touching dev->power.lock in fastpaths unless >> * it's really going to do something useful - pm_runtime_enabled() >> -- >> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member >> of Code Aurora Forum, hosted by The Linux Foundation >> ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/4] iommu/arm-smmu: Add support to handle Qcom's wait-for-safe logic 2019-06-14 9:18 ` Vivek Gautam @ 2019-06-18 17:52 ` Will Deacon [not found] ` <20190618175218.GH4270-UDVVEH7NWB15pKCnmE3YQBJ8xKzm50AiAL8bYrjMMd8@public.gmane.org> 0 siblings, 1 reply; 25+ messages in thread From: Will Deacon @ 2019-06-18 17:52 UTC (permalink / raw) To: Vivek Gautam Cc: Bjorn Andersson, robin.murphy, agross, robh+dt, joro, linux-arm-msm, devicetree, iommu, linux-kernel, david.brown Hi Vivek, On Fri, Jun 14, 2019 at 02:48:07PM +0530, Vivek Gautam wrote: > On 6/14/2019 9:35 AM, Bjorn Andersson wrote: > > On Wed 12 Jun 00:15 PDT 2019, Vivek Gautam wrote: > > > > > Qcom's implementation of arm,mmu-500 adds a WAIT-FOR-SAFE logic > > > to address under-performance issues in real-time clients, such as > > > Display, and Camera. > > > On receiving an invalidation requests, the SMMU forwards SAFE request > > > to these clients and waits for SAFE ack signal from real-time clients. > > > The SAFE signal from such clients is used to qualify the start of > > > invalidation. > > > This logic is controlled by chicken bits, one for each - MDP (display), > > > IFE0, and IFE1 (camera), that can be accessed only from secure software > > > on sdm845. > > > > > > This configuration, however, degrades the performance of non-real time > > > clients, such as USB, and UFS etc. This happens because, with wait-for-safe > > > logic enabled the hardware tries to throttle non-real time clients while > > > waiting for SAFE ack signals from real-time clients. > > > > > > On MTP sdm845 devices, with wait-for-safe logic enabled at the boot time > > > by the bootloaders we see degraded performance of USB and UFS when kernel > > > enables the smmu stage-1 translations for these clients. > > > Turn off this wait-for-safe logic from the kernel gets us back the perf > > > of USB and UFS devices until we re-visit this when we start seeing perf > > > issues on display/camera on upstream supported SDM845 platforms. Re-visit what exactly, and how? > > > Now, different bootloaders with their access control policies allow this > > > register access differently through secure monitor calls - > > > 1) With one we can issue io-read/write secure monitor call (qcom-scm) > > > to update the register, while, > > > 2) With other, such as one on MTP sdm845 we should use the specific > > > qcom-scm command to send request to do the complete register > > > configuration. > > > Adding a separate device tree flag for arm-smmu to identify which > > > firmware configuration of the two mentioned above we use. > > > Not adding code change to allow type-(1) bootloaders to toggle the > > > safe using io-read/write qcom-scm call. > > > > > > This change is inspired by the downstream change from Patrick Daly > > > to address performance issues with display and camera by handling > > > this wait-for-safe within separte io-pagetable ops to do TLB > > > maintenance. So a big thanks to him for the change. > > > > > > Without this change the UFS reads are pretty slow: > > > $ time dd if=/dev/sda of=/dev/zero bs=1048576 count=10 conv=sync > > > 10+0 records in > > > 10+0 records out > > > 10485760 bytes (10.0MB) copied, 22.394903 seconds, 457.2KB/s > > > real 0m 22.39s > > > user 0m 0.00s > > > sys 0m 0.01s > > > > > > With this change they are back to rock! > > > $ time dd if=/dev/sda of=/dev/zero bs=1048576 count=300 conv=sync > > > 300+0 records in > > > 300+0 records out > > > 314572800 bytes (300.0MB) copied, 1.030541 seconds, 291.1MB/s > > > real 0m 1.03s > > > user 0m 0.00s > > > sys 0m 0.54s > > > > > > Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> > > > --- > > > drivers/iommu/arm-smmu.c | 16 ++++++++++++++++ > > > 1 file changed, 16 insertions(+) > > > > > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > > > index 0ad086da399c..3c3ad43eda97 100644 > > > --- a/drivers/iommu/arm-smmu.c > > > +++ b/drivers/iommu/arm-smmu.c > > > @@ -39,6 +39,7 @@ > > > #include <linux/pci.h> > > > #include <linux/platform_device.h> > > > #include <linux/pm_runtime.h> > > > +#include <linux/qcom_scm.h> > > > #include <linux/slab.h> > > > #include <linux/spinlock.h> > > > @@ -177,6 +178,7 @@ struct arm_smmu_device { > > > u32 features; > > > #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0) > > > +#define ARM_SMMU_OPT_QCOM_FW_IMPL_SAFE_ERRATA (1 << 1) > > > u32 options; > > > enum arm_smmu_arch_version version; > > > enum arm_smmu_implementation model; > > > @@ -262,6 +264,7 @@ static bool using_legacy_binding, using_generic_binding; > > > static struct arm_smmu_option_prop arm_smmu_options[] = { > > > { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, > > > + { ARM_SMMU_OPT_QCOM_FW_IMPL_SAFE_ERRATA, "qcom,smmu-500-fw-impl-safe-errata" }, > > This should be added to the DT binding as well. > > Ah right. I missed that. Will add this and respin unless Robin and Will have > concerns with this change. My only concern really is whether it's safe for us to turn this off. It's clear that somebody went to a lot of effort to add this extra goodness to the IP, but your benchmarks suggest they never actually tried it out after they finished building it. Is there some downside I'm not seeing from disabling this stuff? We probably also need some co-ordination with Andy if we're going to merge this, since he maintains the firmware calling code. Will ^ permalink raw reply [flat|nested] 25+ messages in thread
[parent not found: <20190618175218.GH4270-UDVVEH7NWB15pKCnmE3YQBJ8xKzm50AiAL8bYrjMMd8@public.gmane.org>]
* Re: [PATCH v3 3/4] iommu/arm-smmu: Add support to handle Qcom's wait-for-safe logic [not found] ` <20190618175218.GH4270-UDVVEH7NWB15pKCnmE3YQBJ8xKzm50AiAL8bYrjMMd8@public.gmane.org> @ 2019-06-24 10:28 ` Vivek Gautam 2019-06-24 17:03 ` Will Deacon 0 siblings, 1 reply; 25+ messages in thread From: Vivek Gautam @ 2019-06-24 10:28 UTC (permalink / raw) To: Will Deacon Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm, open list, Bjorn Andersson, David Brown, list-Y9sIeH5OGRo@public.gmane.org:IOMMU DRIVERS <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>, Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>, , robh+dt, Andy Gross, Robin Murphy, pratikp-sgV2jX0FEOL9JmXXK+q4OQ Hi Will, On Tue, Jun 18, 2019 at 11:22 PM Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote: > > Hi Vivek, > > On Fri, Jun 14, 2019 at 02:48:07PM +0530, Vivek Gautam wrote: > > On 6/14/2019 9:35 AM, Bjorn Andersson wrote: > > > On Wed 12 Jun 00:15 PDT 2019, Vivek Gautam wrote: > > > > > > > Qcom's implementation of arm,mmu-500 adds a WAIT-FOR-SAFE logic > > > > to address under-performance issues in real-time clients, such as > > > > Display, and Camera. > > > > On receiving an invalidation requests, the SMMU forwards SAFE request > > > > to these clients and waits for SAFE ack signal from real-time clients. > > > > The SAFE signal from such clients is used to qualify the start of > > > > invalidation. > > > > This logic is controlled by chicken bits, one for each - MDP (display), > > > > IFE0, and IFE1 (camera), that can be accessed only from secure software > > > > on sdm845. > > > > > > > > This configuration, however, degrades the performance of non-real time > > > > clients, such as USB, and UFS etc. This happens because, with wait-for-safe > > > > logic enabled the hardware tries to throttle non-real time clients while > > > > waiting for SAFE ack signals from real-time clients. > > > > > > > > On MTP sdm845 devices, with wait-for-safe logic enabled at the boot time > > > > by the bootloaders we see degraded performance of USB and UFS when kernel > > > > enables the smmu stage-1 translations for these clients. > > > > Turn off this wait-for-safe logic from the kernel gets us back the perf > > > > of USB and UFS devices until we re-visit this when we start seeing perf > > > > issues on display/camera on upstream supported SDM845 platforms. > > Re-visit what exactly, and how? > > > > > Now, different bootloaders with their access control policies allow this > > > > register access differently through secure monitor calls - > > > > 1) With one we can issue io-read/write secure monitor call (qcom-scm) > > > > to update the register, while, > > > > 2) With other, such as one on MTP sdm845 we should use the specific > > > > qcom-scm command to send request to do the complete register > > > > configuration. > > > > Adding a separate device tree flag for arm-smmu to identify which > > > > firmware configuration of the two mentioned above we use. > > > > Not adding code change to allow type-(1) bootloaders to toggle the > > > > safe using io-read/write qcom-scm call. > > > > > > > > This change is inspired by the downstream change from Patrick Daly > > > > to address performance issues with display and camera by handling > > > > this wait-for-safe within separte io-pagetable ops to do TLB > > > > maintenance. So a big thanks to him for the change. > > > > > > > > Without this change the UFS reads are pretty slow: > > > > $ time dd if=/dev/sda of=/dev/zero bs=1048576 count=10 conv=sync > > > > 10+0 records in > > > > 10+0 records out > > > > 10485760 bytes (10.0MB) copied, 22.394903 seconds, 457.2KB/s > > > > real 0m 22.39s > > > > user 0m 0.00s > > > > sys 0m 0.01s > > > > > > > > With this change they are back to rock! > > > > $ time dd if=/dev/sda of=/dev/zero bs=1048576 count=300 conv=sync > > > > 300+0 records in > > > > 300+0 records out > > > > 314572800 bytes (300.0MB) copied, 1.030541 seconds, 291.1MB/s > > > > real 0m 1.03s > > > > user 0m 0.00s > > > > sys 0m 0.54s > > > > > > > > Signed-off-by: Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> > > > > --- > > > > drivers/iommu/arm-smmu.c | 16 ++++++++++++++++ > > > > 1 file changed, 16 insertions(+) > > > > > > > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > > > > index 0ad086da399c..3c3ad43eda97 100644 > > > > --- a/drivers/iommu/arm-smmu.c > > > > +++ b/drivers/iommu/arm-smmu.c > > > > @@ -39,6 +39,7 @@ > > > > #include <linux/pci.h> > > > > #include <linux/platform_device.h> > > > > #include <linux/pm_runtime.h> > > > > +#include <linux/qcom_scm.h> > > > > #include <linux/slab.h> > > > > #include <linux/spinlock.h> > > > > @@ -177,6 +178,7 @@ struct arm_smmu_device { > > > > u32 features; > > > > #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0) > > > > +#define ARM_SMMU_OPT_QCOM_FW_IMPL_SAFE_ERRATA (1 << 1) > > > > u32 options; > > > > enum arm_smmu_arch_version version; > > > > enum arm_smmu_implementation model; > > > > @@ -262,6 +264,7 @@ static bool using_legacy_binding, using_generic_binding; > > > > static struct arm_smmu_option_prop arm_smmu_options[] = { > > > > { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, > > > > + { ARM_SMMU_OPT_QCOM_FW_IMPL_SAFE_ERRATA, "qcom,smmu-500-fw-impl-safe-errata" }, > > > This should be added to the DT binding as well. > > > > Ah right. I missed that. Will add this and respin unless Robin and Will have > > concerns with this change. > > My only concern really is whether it's safe for us to turn this off. It's > clear that somebody went to a lot of effort to add this extra goodness to > the IP, but your benchmarks suggest they never actually tried it out after > they finished building it. > > Is there some downside I'm not seeing from disabling this stuff? This wait-for-safe is a TLB invalidation enhancement to help display and camera devices. The SMMU hardware throttles the invalidations so that clients such as display and camera can indicate when to start the invalidation. So the SMMU essentially reduces the rate at which invalidations are serviced from its queue. This also throttles the invalidations from other masters too. On sdm845, the software is expected to serialize the invalidation command loading into SMMU invalidation FIFO using hardware locks (downstream code [2]), and is also expected to throttle non-real time clients while waiting for SAFE==1 (downstream code[2]). We don't do any of these yet, and as per my understanding as this wait-for-safe is enabled by the bootloader in a one time config, this logic reduces performance of devices such as usb and ufs. There's isn't any downside from disabling this logic until we have all the pieces together from downstream in upstream kernels, and until we have sdm845 devices that are running with full display/gfx stack running. That's when we plan to revisit this and enable all the pieces to get display and USB/UFS working with their optimum performance. [1] https://source.codeaurora.org/quic/la/kernel/msm-4.9/tree/drivers/iommu/arm-smmu.c?h=msm-4.9#n5172 [2] https://source.codeaurora.org/quic/la/kernel/msm-4.9/tree/drivers/iommu/arm-smmu.c?h=msm-4.9#n5135 Thanks Vivek > > We probably also need some co-ordination with Andy if we're going to > merge this, since he maintains the firmware calling code. > > Will > _______________________________________________ > iommu mailing list > iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/4] iommu/arm-smmu: Add support to handle Qcom's wait-for-safe logic 2019-06-24 10:28 ` Vivek Gautam @ 2019-06-24 17:03 ` Will Deacon 2019-06-25 7:04 ` Vivek Gautam 0 siblings, 1 reply; 25+ messages in thread From: Will Deacon @ 2019-06-24 17:03 UTC (permalink / raw) To: Vivek Gautam Cc: Will Deacon, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm, open list, robh+dt, Bjorn Andersson, David Brown, list@263.net:IOMMU DRIVERS <iommu@lists.linux-foundation.org>, Joerg Roedel <joro@8bytes.org>,, Andy Gross, Robin Murphy [+Krishna] Hi Vivek, On Mon, Jun 24, 2019 at 03:58:32PM +0530, Vivek Gautam wrote: > On Tue, Jun 18, 2019 at 11:22 PM Will Deacon <will.deacon@arm.com> wrote: > > On Fri, Jun 14, 2019 at 02:48:07PM +0530, Vivek Gautam wrote: > > > On 6/14/2019 9:35 AM, Bjorn Andersson wrote: > > > > On Wed 12 Jun 00:15 PDT 2019, Vivek Gautam wrote: > > > > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > > > > > index 0ad086da399c..3c3ad43eda97 100644 > > > > > --- a/drivers/iommu/arm-smmu.c > > > > > +++ b/drivers/iommu/arm-smmu.c > > > > > @@ -39,6 +39,7 @@ > > > > > #include <linux/pci.h> > > > > > #include <linux/platform_device.h> > > > > > #include <linux/pm_runtime.h> > > > > > +#include <linux/qcom_scm.h> > > > > > #include <linux/slab.h> > > > > > #include <linux/spinlock.h> > > > > > @@ -177,6 +178,7 @@ struct arm_smmu_device { > > > > > u32 features; > > > > > #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0) > > > > > +#define ARM_SMMU_OPT_QCOM_FW_IMPL_SAFE_ERRATA (1 << 1) > > > > > u32 options; > > > > > enum arm_smmu_arch_version version; > > > > > enum arm_smmu_implementation model; > > > > > @@ -262,6 +264,7 @@ static bool using_legacy_binding, using_generic_binding; > > > > > static struct arm_smmu_option_prop arm_smmu_options[] = { > > > > > { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, > > > > > + { ARM_SMMU_OPT_QCOM_FW_IMPL_SAFE_ERRATA, "qcom,smmu-500-fw-impl-safe-errata" }, > > > > This should be added to the DT binding as well. > > > > > > Ah right. I missed that. Will add this and respin unless Robin and Will have > > > concerns with this change. > > > > My only concern really is whether it's safe for us to turn this off. It's > > clear that somebody went to a lot of effort to add this extra goodness to > > the IP, but your benchmarks suggest they never actually tried it out after > > they finished building it. > > > > Is there some downside I'm not seeing from disabling this stuff? > > This wait-for-safe is a TLB invalidation enhancement to help display > and camera devices. > The SMMU hardware throttles the invalidations so that clients such as > display and camera can indicate when to start the invalidation. > So the SMMU essentially reduces the rate at which invalidations are > serviced from its queue. This also throttles the invalidations from > other masters too. > > On sdm845, the software is expected to serialize the invalidation > command loading into SMMU invalidation FIFO using hardware locks > (downstream code [2]), and is also expected to throttle non-real time > clients while waiting for SAFE==1 (downstream code[2]). We don't do > any of these yet, and as per my understanding as this wait-for-safe is > enabled by the bootloader in a one time config, this logic reduces > performance of devices such as usb and ufs. > > There's isn't any downside from disabling this logic until we have all > the pieces together from downstream in upstream kernels, and until we > have sdm845 devices that are running with full display/gfx stack > running. That's when we plan to revisit this and enable all the pieces > to get display and USB/UFS working with their optimum performance. Generally, I'd agree that approaching this incrementally makes sense, but in this case you're adding new device-tree properties ("qcom,smmu-500-fw-impl-safe-errata") in order to do so, which seems questionable if they're only going to be used in the short-term and will be obsolete once Linux knows how to drive the device properly. Instead, I think this needs to be part of a separate file that is maintained by you, which follows on from the work that Krishna is doing for nvidia built on top of Robin's prototype patches: http://linux-arm.org/git?p=linux-rm.git;a=shortlog;h=refs/heads/iommu/smmu-impl Once we have that, you can key this behaviour off the compatible string rather than having to add quirk properties to reflect the transient needs of Linux. Krishna -- how have you been getting on with the branch above? Will ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/4] iommu/arm-smmu: Add support to handle Qcom's wait-for-safe logic 2019-06-24 17:03 ` Will Deacon @ 2019-06-25 7:04 ` Vivek Gautam [not found] ` <CAFp+6iF0TQtAy2JFXk6zjX5GpjeLFesqPZV6ezbDXmc85yvMEA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 25+ messages in thread From: Vivek Gautam @ 2019-06-25 7:04 UTC (permalink / raw) To: Will Deacon Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm, Will Deacon, open list, Bjorn Andersson, David Brown, list@263.net:IOMMU DRIVERS <iommu@lists.linux-foundation.org>, Joerg Roedel <joro@8bytes.org>,, robh+dt, Andy Gross, Robin Murphy Hi Will, On Mon, Jun 24, 2019 at 10:33 PM Will Deacon <will@kernel.org> wrote: > > [+Krishna] > > Hi Vivek, > > On Mon, Jun 24, 2019 at 03:58:32PM +0530, Vivek Gautam wrote: > > On Tue, Jun 18, 2019 at 11:22 PM Will Deacon <will.deacon@arm.com> wrote: > > > On Fri, Jun 14, 2019 at 02:48:07PM +0530, Vivek Gautam wrote: > > > > On 6/14/2019 9:35 AM, Bjorn Andersson wrote: > > > > > On Wed 12 Jun 00:15 PDT 2019, Vivek Gautam wrote: > > > > > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > > > > > > index 0ad086da399c..3c3ad43eda97 100644 > > > > > > --- a/drivers/iommu/arm-smmu.c > > > > > > +++ b/drivers/iommu/arm-smmu.c > > > > > > @@ -39,6 +39,7 @@ > > > > > > #include <linux/pci.h> > > > > > > #include <linux/platform_device.h> > > > > > > #include <linux/pm_runtime.h> > > > > > > +#include <linux/qcom_scm.h> > > > > > > #include <linux/slab.h> > > > > > > #include <linux/spinlock.h> > > > > > > @@ -177,6 +178,7 @@ struct arm_smmu_device { > > > > > > u32 features; > > > > > > #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0) > > > > > > +#define ARM_SMMU_OPT_QCOM_FW_IMPL_SAFE_ERRATA (1 << 1) > > > > > > u32 options; > > > > > > enum arm_smmu_arch_version version; > > > > > > enum arm_smmu_implementation model; > > > > > > @@ -262,6 +264,7 @@ static bool using_legacy_binding, using_generic_binding; > > > > > > static struct arm_smmu_option_prop arm_smmu_options[] = { > > > > > > { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, > > > > > > + { ARM_SMMU_OPT_QCOM_FW_IMPL_SAFE_ERRATA, "qcom,smmu-500-fw-impl-safe-errata" }, > > > > > This should be added to the DT binding as well. > > > > > > > > Ah right. I missed that. Will add this and respin unless Robin and Will have > > > > concerns with this change. > > > > > > My only concern really is whether it's safe for us to turn this off. It's > > > clear that somebody went to a lot of effort to add this extra goodness to > > > the IP, but your benchmarks suggest they never actually tried it out after > > > they finished building it. > > > > > > Is there some downside I'm not seeing from disabling this stuff? > > > > This wait-for-safe is a TLB invalidation enhancement to help display > > and camera devices. > > The SMMU hardware throttles the invalidations so that clients such as > > display and camera can indicate when to start the invalidation. > > So the SMMU essentially reduces the rate at which invalidations are > > serviced from its queue. This also throttles the invalidations from > > other masters too. > > > > On sdm845, the software is expected to serialize the invalidation > > command loading into SMMU invalidation FIFO using hardware locks > > (downstream code [2]), and is also expected to throttle non-real time > > clients while waiting for SAFE==1 (downstream code[2]). We don't do > > any of these yet, and as per my understanding as this wait-for-safe is > > enabled by the bootloader in a one time config, this logic reduces > > performance of devices such as usb and ufs. > > > > There's isn't any downside from disabling this logic until we have all > > the pieces together from downstream in upstream kernels, and until we > > have sdm845 devices that are running with full display/gfx stack > > running. That's when we plan to revisit this and enable all the pieces > > to get display and USB/UFS working with their optimum performance. > > Generally, I'd agree that approaching this incrementally makes sense, but > in this case you're adding new device-tree properties > ("qcom,smmu-500-fw-impl-safe-errata") in order to do so, which seems > questionable if they're only going to be used in the short-term and will > be obsolete once Linux knows how to drive the device properly. This device tree property will still be valid when we handle the wait-for-safe properly for sdm845. ("qcom,smmu-500-fw-impl-safe-errata") property represents just that the firmware has handles to do the entire sequence - * read the secure register * set/reset the bits in the register to enable/disable wait-for-safe for certain devices. And this is valid when firmware masks access to this register from any other EE. So we don't have to do anything that, for example, we were doing for sdm845 based cheza's firmware [1] that implements simple scm handlers to read/write secure registers. And fyi, some of the newer SoCs too have this logic, and kernel can have that extra bit of page-table-ops to handle wait-safe toggling. [1] https://lore.kernel.org/patchwork/patch/983917/ > > Instead, I think this needs to be part of a separate file that is maintained > by you, which follows on from the work that Krishna is doing for nvidia > built on top of Robin's prototype patches: > > http://linux-arm.org/git?p=linux-rm.git;a=shortlog;h=refs/heads/iommu/smmu-impl Looking at this branch quickly, it seem there can be separate implementation level configuration file that can be added. But will this also handle separate page table ops when required in future. Best regards Vivek > > Once we have that, you can key this behaviour off the compatible string > rather than having to add quirk properties to reflect the transient needs of > Linux. > > Krishna -- how have you been getting on with the branch above? > > Will > _______________________________________________ > iommu mailing list > iommu@lists.linux-foundation.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 25+ messages in thread
[parent not found: <CAFp+6iF0TQtAy2JFXk6zjX5GpjeLFesqPZV6ezbDXmc85yvMEA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH v3 3/4] iommu/arm-smmu: Add support to handle Qcom's wait-for-safe logic [not found] ` <CAFp+6iF0TQtAy2JFXk6zjX5GpjeLFesqPZV6ezbDXmc85yvMEA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2019-06-25 13:39 ` Will Deacon 2019-06-26 6:33 ` Vivek Gautam 0 siblings, 1 reply; 25+ messages in thread From: Will Deacon @ 2019-06-25 13:39 UTC (permalink / raw) To: Vivek Gautam Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm, Will Deacon, open list, Bjorn Andersson, David Brown, list-Y9sIeH5OGRo@public.gmane.org:IOMMU DRIVERS <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>, Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>, , robh+dt, Andy Gross, Robin Murphy On Tue, Jun 25, 2019 at 12:34:56PM +0530, Vivek Gautam wrote: > On Mon, Jun 24, 2019 at 10:33 PM Will Deacon <will-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote: > > Instead, I think this needs to be part of a separate file that is maintained > > by you, which follows on from the work that Krishna is doing for nvidia > > built on top of Robin's prototype patches: > > > > http://linux-arm.org/git?p=linux-rm.git;a=shortlog;h=refs/heads/iommu/smmu-impl > > Looking at this branch quickly, it seem there can be separate implementation > level configuration file that can be added. > But will this also handle separate page table ops when required in future. Nothing's set in stone, but having the implementation-specific code constrain the page-table format (especially wrt quirks) sounds reasonable to me. I'm currently waiting for Krishna to respin the nvidia changes [1] on top of this so that we can see how well the abstractions are holding up. I certainly won't merge the stuff until we have a user. Will [1] https://lkml.kernel.org/r/1543887414-18209-1-git-send-email-vdumpa-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/4] iommu/arm-smmu: Add support to handle Qcom's wait-for-safe logic 2019-06-25 13:39 ` Will Deacon @ 2019-06-26 6:33 ` Vivek Gautam 2019-06-26 14:48 ` Will Deacon 0 siblings, 1 reply; 25+ messages in thread From: Vivek Gautam @ 2019-06-26 6:33 UTC (permalink / raw) To: Will Deacon Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm, Will Deacon, open list, Bjorn Andersson, David Brown, list-Y9sIeH5OGRo@public.gmane.org:IOMMU DRIVERS <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>, Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>, , robh+dt, Andy Gross, Robin Murphy On Tue, Jun 25, 2019 at 7:09 PM Will Deacon <will-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote: > > On Tue, Jun 25, 2019 at 12:34:56PM +0530, Vivek Gautam wrote: > > On Mon, Jun 24, 2019 at 10:33 PM Will Deacon <will-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote: > > > Instead, I think this needs to be part of a separate file that is maintained > > > by you, which follows on from the work that Krishna is doing for nvidia > > > built on top of Robin's prototype patches: > > > > > > http://linux-arm.org/git?p=linux-rm.git;a=shortlog;h=refs/heads/iommu/smmu-impl > > > > Looking at this branch quickly, it seem there can be separate implementation > > level configuration file that can be added. > > But will this also handle separate page table ops when required in future. > > Nothing's set in stone, but having the implementation-specific code > constrain the page-table format (especially wrt quirks) sounds reasonable to > me. I'm currently waiting for Krishna to respin the nvidia changes [1] on > top of this so that we can see how well the abstractions are holding up. Sure. Would you want me to try Robin's branch and take out the qualcomm related stuff to its own implementation? Or, would you like me to respin this series so that you can take it in to enable SDM845 boards such as, MTP and dragonboard to have a sane build - debian, etc. so people benefit out of it. Qualcomm stuff is lying in qcom-smmu and arm-smmu and may take some time to stub out the implementation related details. Let me know your take. Thanks & regards Vivek > > I certainly won't merge the stuff until we have a user. > > Will > > [1] https://lkml.kernel.org/r/1543887414-18209-1-git-send-email-vdumpa-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org > _______________________________________________ > iommu mailing list > iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/4] iommu/arm-smmu: Add support to handle Qcom's wait-for-safe logic 2019-06-26 6:33 ` Vivek Gautam @ 2019-06-26 14:48 ` Will Deacon 2019-06-27 7:05 ` Vivek Gautam 0 siblings, 1 reply; 25+ messages in thread From: Will Deacon @ 2019-06-26 14:48 UTC (permalink / raw) To: Vivek Gautam Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm, Will Deacon, open list, Bjorn Andersson, David Brown, list@263.net:IOMMU DRIVERS <iommu@lists.linux-foundation.org>, Joerg Roedel <joro@8bytes.org>,, robh+dt, Andy Gross, Robin Murphy On Wed, Jun 26, 2019 at 12:03:02PM +0530, Vivek Gautam wrote: > On Tue, Jun 25, 2019 at 7:09 PM Will Deacon <will@kernel.org> wrote: > > > > On Tue, Jun 25, 2019 at 12:34:56PM +0530, Vivek Gautam wrote: > > > On Mon, Jun 24, 2019 at 10:33 PM Will Deacon <will@kernel.org> wrote: > > > > Instead, I think this needs to be part of a separate file that is maintained > > > > by you, which follows on from the work that Krishna is doing for nvidia > > > > built on top of Robin's prototype patches: > > > > > > > > http://linux-arm.org/git?p=linux-rm.git;a=shortlog;h=refs/heads/iommu/smmu-impl > > > > > > Looking at this branch quickly, it seem there can be separate implementation > > > level configuration file that can be added. > > > But will this also handle separate page table ops when required in future. > > > > Nothing's set in stone, but having the implementation-specific code > > constrain the page-table format (especially wrt quirks) sounds reasonable to > > me. I'm currently waiting for Krishna to respin the nvidia changes [1] on > > top of this so that we can see how well the abstractions are holding up. > > Sure. Would you want me to try Robin's branch and take out the qualcomm > related stuff to its own implementation? Or, would you like me to respin this > series so that you can take it in to enable SDM845 boards such as, MTP > and dragonboard to have a sane build - debian, etc. so people benefit > out of it. I can't take this series without Acks on the firmware calling changes, and I plan to send my 5.3 patches to Joerg at the end of the week so they get some time in -next. In which case, I think it may be worth you having a play with the branch above so we can get a better idea of any additional smmu_impl hooks you may need. > Qualcomm stuff is lying in qcom-smmu and arm-smmu and may take some > time to stub out the implementation related details. Not sure I follow you here. Are you talking about qcom_iommu.c? Will ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/4] iommu/arm-smmu: Add support to handle Qcom's wait-for-safe logic 2019-06-26 14:48 ` Will Deacon @ 2019-06-27 7:05 ` Vivek Gautam 0 siblings, 0 replies; 25+ messages in thread From: Vivek Gautam @ 2019-06-27 7:05 UTC (permalink / raw) To: Will Deacon Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm, Will Deacon, open list, Bjorn Andersson, David Brown, list@263.net:IOMMU DRIVERS <iommu@lists.linux-foundation.org>, Joerg Roedel <joro@8bytes.org>,, robh+dt, Andy Gross, Robin Murphy, Rob Clark On Wed, Jun 26, 2019 at 8:18 PM Will Deacon <will@kernel.org> wrote: > > On Wed, Jun 26, 2019 at 12:03:02PM +0530, Vivek Gautam wrote: > > On Tue, Jun 25, 2019 at 7:09 PM Will Deacon <will@kernel.org> wrote: > > > > > > On Tue, Jun 25, 2019 at 12:34:56PM +0530, Vivek Gautam wrote: > > > > On Mon, Jun 24, 2019 at 10:33 PM Will Deacon <will@kernel.org> wrote: > > > > > Instead, I think this needs to be part of a separate file that is maintained > > > > > by you, which follows on from the work that Krishna is doing for nvidia > > > > > built on top of Robin's prototype patches: > > > > > > > > > > http://linux-arm.org/git?p=linux-rm.git;a=shortlog;h=refs/heads/iommu/smmu-impl > > > > > > > > Looking at this branch quickly, it seem there can be separate implementation > > > > level configuration file that can be added. > > > > But will this also handle separate page table ops when required in future. > > > > > > Nothing's set in stone, but having the implementation-specific code > > > constrain the page-table format (especially wrt quirks) sounds reasonable to > > > me. I'm currently waiting for Krishna to respin the nvidia changes [1] on > > > top of this so that we can see how well the abstractions are holding up. > > > > Sure. Would you want me to try Robin's branch and take out the qualcomm > > related stuff to its own implementation? Or, would you like me to respin this > > series so that you can take it in to enable SDM845 boards such as, MTP > > and dragonboard to have a sane build - debian, etc. so people benefit > > out of it. > > I can't take this series without Acks on the firmware calling changes, and I > plan to send my 5.3 patches to Joerg at the end of the week so they get some > time in -next. In which case, I think it may be worth you having a play with > the branch above so we can get a better idea of any additional smmu_impl hooks > you may need. Cool. I will play around with it and get something tangible and meaningful. > > > Qualcomm stuff is lying in qcom-smmu and arm-smmu and may take some > > time to stub out the implementation related details. > > Not sure I follow you here. Are you talking about qcom_iommu.c? That's right. The qcom_iommu.c solved a different issue of secure context bank allocations, when Rob forked out this driver and reused some of the arm-smmu.c stuff. We will take a look at that once we start adding the qcom implementation. Thanks Vivek > > Will > _______________________________________________ > iommu mailing list > iommu@lists.linux-foundation.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 4/4] arm64: dts/sdm845: Enable FW implemented safe sequence handler on MTP 2019-06-12 7:15 [PATCH v3 0/4] Qcom smmu-500 wait-for-safe handling for sdm845 Vivek Gautam ` (2 preceding siblings ...) 2019-06-12 7:15 ` [PATCH v3 3/4] iommu/arm-smmu: Add support to handle Qcom's wait-for-safe logic Vivek Gautam @ 2019-06-12 7:15 ` Vivek Gautam [not found] ` <20190612071554.13573-5-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 3 siblings, 1 reply; 25+ messages in thread From: Vivek Gautam @ 2019-06-12 7:15 UTC (permalink / raw) To: agross, robh+dt, will.deacon, robin.murphy, joro, bjorn.andersson, linux-arm-msm, devicetree, iommu Cc: linux-kernel, david.brown, Vivek Gautam Indicate on MTP SDM845 that firmware implements handler to TLB invalidate erratum SCM call where SAFE sequence is toggled to achieve optimum performance on real-time clients, such as display and camera. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 78ec373a2b18..6a73d9744a71 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2368,6 +2368,7 @@ compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x80000>; #iommu-cells = <2>; + qcom,smmu-500-fw-impl-safe-errata; #global-interrupts = <1>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 25+ messages in thread
[parent not found: <20190612071554.13573-5-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>]
* Re: [PATCH v3 4/4] arm64: dts/sdm845: Enable FW implemented safe sequence handler on MTP [not found] ` <20190612071554.13573-5-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> @ 2019-06-14 4:06 ` Bjorn Andersson 2019-06-14 9:01 ` Vivek Gautam 2019-08-05 22:26 ` Bjorn Andersson 1 sibling, 1 reply; 25+ messages in thread From: Bjorn Andersson @ 2019-06-14 4:06 UTC (permalink / raw) To: Vivek Gautam Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA, will.deacon-5wv7dgnIgG8, linux-kernel-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, david.brown-QSEj5FYQhm4dnm+yROfE0A, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, agross-DgEjT+Ai2ygdnm+yROfE0A, robin.murphy-5wv7dgnIgG8 On Wed 12 Jun 00:15 PDT 2019, Vivek Gautam wrote: > Indicate on MTP SDM845 that firmware implements handler to > TLB invalidate erratum SCM call where SAFE sequence is toggled > to achieve optimum performance on real-time clients, such as > display and camera. > > Signed-off-by: Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Reviewed-by: Bjorn Andersson <bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index 78ec373a2b18..6a73d9744a71 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -2368,6 +2368,7 @@ > compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; > reg = <0 0x15000000 0 0x80000>; > #iommu-cells = <2>; > + qcom,smmu-500-fw-impl-safe-errata; > #global-interrupts = <1>; > interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation > ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 4/4] arm64: dts/sdm845: Enable FW implemented safe sequence handler on MTP 2019-06-14 4:06 ` Bjorn Andersson @ 2019-06-14 9:01 ` Vivek Gautam 0 siblings, 0 replies; 25+ messages in thread From: Vivek Gautam @ 2019-06-14 9:01 UTC (permalink / raw) To: Bjorn Andersson Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA, will.deacon-5wv7dgnIgG8, linux-kernel-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, david.brown-QSEj5FYQhm4dnm+yROfE0A, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, agross-DgEjT+Ai2ygdnm+yROfE0A, robin.murphy-5wv7dgnIgG8 On 6/14/2019 9:36 AM, Bjorn Andersson wrote: > On Wed 12 Jun 00:15 PDT 2019, Vivek Gautam wrote: > >> Indicate on MTP SDM845 that firmware implements handler to >> TLB invalidate erratum SCM call where SAFE sequence is toggled >> to achieve optimum performance on real-time clients, such as >> display and camera. >> >> Signed-off-by: Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> > Reviewed-by: Bjorn Andersson <bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> Thanks Bjorn for reviewing this. Best regards Vivek [snip] ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 4/4] arm64: dts/sdm845: Enable FW implemented safe sequence handler on MTP [not found] ` <20190612071554.13573-5-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2019-06-14 4:06 ` Bjorn Andersson @ 2019-08-05 22:26 ` Bjorn Andersson 2019-08-11 16:08 ` Vivek Gautam 1 sibling, 1 reply; 25+ messages in thread From: Bjorn Andersson @ 2019-08-05 22:26 UTC (permalink / raw) To: Vivek Gautam Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA, will.deacon-5wv7dgnIgG8, linux-kernel-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, david.brown-QSEj5FYQhm4dnm+yROfE0A, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, agross-DgEjT+Ai2ygdnm+yROfE0A, robin.murphy-5wv7dgnIgG8 On Wed 12 Jun 00:15 PDT 2019, Vivek Gautam wrote: > Indicate on MTP SDM845 that firmware implements handler to > TLB invalidate erratum SCM call where SAFE sequence is toggled > to achieve optimum performance on real-time clients, such as > display and camera. > > Signed-off-by: Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index 78ec373a2b18..6a73d9744a71 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -2368,6 +2368,7 @@ > compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; > reg = <0 0x15000000 0 0x80000>; > #iommu-cells = <2>; > + qcom,smmu-500-fw-impl-safe-errata; Looked back at this series and started to wonder if there there is a case where this should not be set? I mean we're after all adding this to the top 845 dtsi... How about making it the default in the driver and opt out of the errata once there is a need? Regards, Bjorn > #global-interrupts = <1>; > interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation > ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 4/4] arm64: dts/sdm845: Enable FW implemented safe sequence handler on MTP 2019-08-05 22:26 ` Bjorn Andersson @ 2019-08-11 16:08 ` Vivek Gautam 2019-08-11 19:01 ` Bjorn Andersson 0 siblings, 1 reply; 25+ messages in thread From: Vivek Gautam @ 2019-08-11 16:08 UTC (permalink / raw) To: Bjorn Andersson Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm, Will Deacon, open list, David Brown, list-Y9sIeH5OGRo@public.gmane.org:IOMMU DRIVERS <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>, Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>, , robh+dt, Andy Gross, Robin Murphy On Tue, Aug 6, 2019 at 3:56 AM Bjorn Andersson <bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote: > > On Wed 12 Jun 00:15 PDT 2019, Vivek Gautam wrote: > > > Indicate on MTP SDM845 that firmware implements handler to > > TLB invalidate erratum SCM call where SAFE sequence is toggled > > to achieve optimum performance on real-time clients, such as > > display and camera. > > > > Signed-off-by: Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> > > --- > > arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > index 78ec373a2b18..6a73d9744a71 100644 > > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > @@ -2368,6 +2368,7 @@ > > compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; > > reg = <0 0x15000000 0 0x80000>; > > #iommu-cells = <2>; > > + qcom,smmu-500-fw-impl-safe-errata; > > Looked back at this series and started to wonder if there there is a > case where this should not be set? I mean we're after all adding this to > the top 845 dtsi... My bad. This is not valid in case of cheza. Cheza firmware doesn't implement the safe errata handling hook. On cheza we just have the liberty of accessing the secure registers through scm calls - this is what we were doing in earlier patch series handling this errata. So, a property like this should go to mtp board's dts file. Thanks Vivek > > How about making it the default in the driver and opt out of the errata > once there is a need? > > Regards, > Bjorn > > > #global-interrupts = <1>; > > interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, > > <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, > > -- > > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > > of Code Aurora Forum, hosted by The Linux Foundation > > > _______________________________________________ > iommu mailing list > iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 4/4] arm64: dts/sdm845: Enable FW implemented safe sequence handler on MTP 2019-08-11 16:08 ` Vivek Gautam @ 2019-08-11 19:01 ` Bjorn Andersson 0 siblings, 0 replies; 25+ messages in thread From: Bjorn Andersson @ 2019-08-11 19:01 UTC (permalink / raw) To: Vivek Gautam Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm, Will Deacon, open list, robh+dt, David Brown, list@263.net:IOMMU DRIVERS <iommu@lists.linux-foundation.org>, Joerg Roedel <joro@8bytes.org>,, Andy Gross, Robin Murphy On Sun 11 Aug 09:08 PDT 2019, Vivek Gautam wrote: > On Tue, Aug 6, 2019 at 3:56 AM Bjorn Andersson > <bjorn.andersson@linaro.org> wrote: > > > > On Wed 12 Jun 00:15 PDT 2019, Vivek Gautam wrote: > > > > > Indicate on MTP SDM845 that firmware implements handler to > > > TLB invalidate erratum SCM call where SAFE sequence is toggled > > > to achieve optimum performance on real-time clients, such as > > > display and camera. > > > > > > Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> > > > --- > > > arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + > > > 1 file changed, 1 insertion(+) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > index 78ec373a2b18..6a73d9744a71 100644 > > > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > @@ -2368,6 +2368,7 @@ > > > compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; > > > reg = <0 0x15000000 0 0x80000>; > > > #iommu-cells = <2>; > > > + qcom,smmu-500-fw-impl-safe-errata; > > > > Looked back at this series and started to wonder if there there is a > > case where this should not be set? I mean we're after all adding this to > > the top 845 dtsi... > > My bad. > This is not valid in case of cheza. Cheza firmware doesn't implement > the safe errata handling hook. > On cheza we just have the liberty of accessing the secure registers > through scm calls - this is what > we were doing in earlier patch series handling this errata. > So, a property like this should go to mtp board's dts file. > It would have been nice if the common case was just selected by default, but afaict no safe workaround is needed on Cheza? You mention here that it should (could?) use the scm write based approach instead, would an introduction of that come with another flag? PS. In it's current form it's correct that this should be moved to the device dts files - all but one of them... Regards, Bjorn ^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2019-08-11 19:01 UTC | newest] Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-06-12 7:15 [PATCH v3 0/4] Qcom smmu-500 wait-for-safe handling for sdm845 Vivek Gautam 2019-06-12 7:15 ` [PATCH v3 1/4] firmware: qcom_scm-64: Add atomic version of qcom_scm_call Vivek Gautam 2019-06-18 17:55 ` Will Deacon [not found] ` <20190618175536.GI4270-UDVVEH7NWB15pKCnmE3YQBJ8xKzm50AiAL8bYrjMMd8@public.gmane.org> 2019-06-19 11:34 ` Vivek Gautam 2019-08-05 22:27 ` Bjorn Andersson 2019-08-08 11:35 ` Vivek Gautam 2019-08-08 16:30 ` Will Deacon 2019-06-12 7:15 ` [PATCH v3 2/4] firmware/qcom_scm: Add scm call to handle smmu errata Vivek Gautam 2019-06-12 7:15 ` [PATCH v3 3/4] iommu/arm-smmu: Add support to handle Qcom's wait-for-safe logic Vivek Gautam [not found] ` <20190612071554.13573-4-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2019-06-14 4:05 ` Bjorn Andersson 2019-06-14 9:18 ` Vivek Gautam 2019-06-18 17:52 ` Will Deacon [not found] ` <20190618175218.GH4270-UDVVEH7NWB15pKCnmE3YQBJ8xKzm50AiAL8bYrjMMd8@public.gmane.org> 2019-06-24 10:28 ` Vivek Gautam 2019-06-24 17:03 ` Will Deacon 2019-06-25 7:04 ` Vivek Gautam [not found] ` <CAFp+6iF0TQtAy2JFXk6zjX5GpjeLFesqPZV6ezbDXmc85yvMEA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2019-06-25 13:39 ` Will Deacon 2019-06-26 6:33 ` Vivek Gautam 2019-06-26 14:48 ` Will Deacon 2019-06-27 7:05 ` Vivek Gautam 2019-06-12 7:15 ` [PATCH v3 4/4] arm64: dts/sdm845: Enable FW implemented safe sequence handler on MTP Vivek Gautam [not found] ` <20190612071554.13573-5-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2019-06-14 4:06 ` Bjorn Andersson 2019-06-14 9:01 ` Vivek Gautam 2019-08-05 22:26 ` Bjorn Andersson 2019-08-11 16:08 ` Vivek Gautam 2019-08-11 19:01 ` Bjorn Andersson
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