From: Vidya Sagar <vidyas@nvidia.com>
To: lorenzo.pieralisi@arm.com, bhelgaas@google.com,
robh+dt@kernel.org, mark.rutland@arm.com,
thierry.reding@gmail.com, jonathanh@nvidia.com, kishon@ti.com,
catalin.marinas@arm.com, will.deacon@arm.com,
jingoohan1@gmail.com, gustavo.pimentel@synopsys.com
Cc: digetx@gmail.com, mperttunen@nvidia.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kthota@nvidia.com,
mmaddireddy@nvidia.com, vidyas@nvidia.com, sagar.tv@gmail.com
Subject: [PATCH V11 00/12] Add Tegra194 PCIe support
Date: Mon, 24 Jun 2019 14:44:53 +0530 [thread overview]
Message-ID: <20190624091505.1711-1-vidyas@nvidia.com> (raw)
Tegra194 has six PCIe controllers based on Synopsys DesignWare core.
There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO:
Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively.
Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 uses
UPHY lanes from NVHS brick. Lane mapping in HSIO UPHY brick to each PCIe
controller (0~4) is controlled in XBAR module by BPMP-FW. Since PCIe
core has PIPE interface, a glue module called PIPE-to-UPHY (P2U) is used
to connect each UPHY lane (applicable to both HSIO and NVHS UPHY bricks)
to PCIe controller
This patch series
- Adds support for P2U PHY driver
- Adds support for PCIe host controller
- Adds device tree nodes each PCIe controllers
- Enables nodes applicable to p2972-0000 platform
- Adds helper APIs in Designware core driver to get capability regs offset
- Adds defines for new feature registers of PCIe spec revision 4
- Makes changes in DesignWare core driver to get Tegra194 PCIe working
Testing done on P2972-0000 platform
- Able to get PCIe link up with on-board Marvel eSATA controller
- Able to get PCIe link up with NVMe cards connected to M.2 Key-M slot
- Able to do data transfers with both SATA drives and NVMe cards
Note
- Enabling x8 slot on P2972-0000 platform requires pinmux driver for Tegra194.
It is being worked on currently and hence Controller:5 (i.e. x8 slot) is
disabled in this patch series. A future patch series would enable this.
- This series is based on top of the following series
Jisheng's patches to add support to .remove() in Designware sub-system
https://patchwork.kernel.org/project/linux-pci/list/?series=98559
(Jisheng's patches are now accepted and applied for v5.2)
My patches made on top of Jisheng's patches to export various symbols
http://patchwork.ozlabs.org/project/linux-pci/list/?series=115671
Changes since [v10]:
* Removed device-tree patches from the series as they are applied to relevant
Tegra specific trees by Thierry Reding.
* Included older Tegra chips to extend quirk that disables MSI interrupt being
used for Tegra PCIe root ports.
* Addressed review comments in P2U driver file.
Changes since [v9]:
* Used _relaxed() versions of readl() & writel()
Changes since [v8]:
* Made the drivers dependent on ARCH_TEGRA_194_SOC directly
* Addressed review comments from Dmitry
Changes since [v7]:
* Changed P2U driver file name from pcie-p2u-tegra194.c to phy-tegra194-p2u.c
* Addressed review comments from Thierry and Rob
Changes since [v6]:
* Took care of review comments from Rob
* Added a quirk to disable MSI for root ports
* Removed using pcie_pme_disable_msi() API in host controller driver
Changes since [v5]:
* Removed patch that exports pcie_bus_config symbol
* Took care of review comments from Thierry and Rob
Changes since [v4]:
* Removed redundant APIs in pcie-designware-ep.c file after moving them
to pcie-designware.c file based on Bjorn's review comments
Changes since [v3]:
* Rebased on top of linux-next top of the tree
* Addressed Gustavo's comments and added his Ack for some of the changes.
Changes since [v2]:
* Addressed review comments from Thierry
Changes since [v1]:
* Addressed review comments from Bjorn, Thierry, Jonathan, Rob & Kishon
* Added more patches in v2 series
Vidya Sagar (12):
PCI: Add #defines for some of PCIe spec r4.0 features
PCI: Disable MSI for Tegra root ports
PCI: dwc: Perform dbi regs write lock towards the end
PCI: dwc: Move config space capability search API
PCI: dwc: Add ext config space capability search API
dt-bindings: PCI: designware: Add binding for CDM register check
PCI: dwc: Add support to enable CDM register check
dt-bindings: Add PCIe supports-clkreq property
dt-bindings: PCI: tegra: Add device tree support for Tegra194
dt-bindings: PHY: P2U: Add Tegra194 P2U block
phy: tegra: Add PCIe PIPE2UPHY support
PCI: tegra: Add Tegra194 PCIe support
.../bindings/pci/designware-pcie.txt | 5 +
.../bindings/pci/nvidia,tegra194-pcie.txt | 155 ++
Documentation/devicetree/bindings/pci/pci.txt | 5 +
.../bindings/phy/phy-tegra194-p2u.txt | 28 +
drivers/pci/controller/dwc/Kconfig | 10 +
drivers/pci/controller/dwc/Makefile | 1 +
.../pci/controller/dwc/pcie-designware-ep.c | 37 +-
.../pci/controller/dwc/pcie-designware-host.c | 14 +-
drivers/pci/controller/dwc/pcie-designware.c | 87 +
drivers/pci/controller/dwc/pcie-designware.h | 12 +
drivers/pci/controller/dwc/pcie-tegra194.c | 1635 +++++++++++++++++
drivers/pci/quirks.c | 53 +
drivers/phy/tegra/Kconfig | 7 +
drivers/phy/tegra/Makefile | 1 +
drivers/phy/tegra/phy-tegra194-p2u.c | 120 ++
include/uapi/linux/pci_regs.h | 22 +-
16 files changed, 2150 insertions(+), 42 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
create mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
create mode 100644 drivers/pci/controller/dwc/pcie-tegra194.c
create mode 100644 drivers/phy/tegra/phy-tegra194-p2u.c
--
2.17.1
next reply other threads:[~2019-06-24 9:14 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-24 9:14 Vidya Sagar [this message]
2019-06-24 9:14 ` [PATCH V11 01/12] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-06-27 14:38 ` Lorenzo Pieralisi
2019-07-01 12:42 ` Vidya Sagar
2019-06-24 9:14 ` [PATCH V11 02/12] PCI: Disable MSI for Tegra root ports Vidya Sagar
2019-06-24 9:14 ` [PATCH V11 03/12] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-06-27 14:58 ` Lorenzo Pieralisi
2019-06-27 15:33 ` Vidya Sagar
2019-06-27 15:50 ` Lorenzo Pieralisi
2019-06-27 16:52 ` Vidya Sagar
2019-06-24 9:14 ` [PATCH V11 04/12] PCI: dwc: Move config space capability search API Vidya Sagar
2019-06-24 9:14 ` [PATCH V11 05/12] PCI: dwc: Add ext " Vidya Sagar
2019-06-24 9:14 ` [PATCH V11 06/12] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-06-24 9:15 ` [PATCH V11 07/12] PCI: dwc: Add support to enable " Vidya Sagar
2019-06-24 9:15 ` [PATCH V11 08/12] dt-bindings: Add PCIe supports-clkreq property Vidya Sagar
2019-06-24 9:15 ` [PATCH V11 09/12] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar
2019-06-24 9:15 ` [PATCH V11 10/12] dt-bindings: PHY: P2U: Add Tegra194 P2U block Vidya Sagar
2019-06-24 9:15 ` [PATCH V11 11/12] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-06-24 9:15 ` [PATCH V11 12/12] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
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