From: Vidya Sagar <vidyas@nvidia.com>
To: lorenzo.pieralisi@arm.com, bhelgaas@google.com,
robh+dt@kernel.org, mark.rutland@arm.com,
thierry.reding@gmail.com, jonathanh@nvidia.com, kishon@ti.com,
catalin.marinas@arm.com, will.deacon@arm.com,
jingoohan1@gmail.com, gustavo.pimentel@synopsys.com
Cc: digetx@gmail.com, mperttunen@nvidia.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kthota@nvidia.com,
mmaddireddy@nvidia.com, vidyas@nvidia.com, sagar.tv@gmail.com
Subject: [PATCH V11 03/12] PCI: dwc: Perform dbi regs write lock towards the end
Date: Mon, 24 Jun 2019 14:44:56 +0530 [thread overview]
Message-ID: <20190624091505.1711-4-vidyas@nvidia.com> (raw)
In-Reply-To: <20190624091505.1711-1-vidyas@nvidia.com>
Remove multiple write enable and disable sequences of dbi registers as
Tegra194 implements writes to BAR-0 register (offset: 0x10) controlled by
DBI write-lock enable bit thereby not allowing any further writes to BAR-0
register in config space to take place. Hence enabling write permission at
the start of function and disabling the same only towards the end.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
---
Changes since [v10]:
* None
Changes since [v9]:
* None
Changes since [v8]:
* None
Changes since [v7]:
* None
Changes since [v6]:
* None
Changes since [v5]:
* Moved write enable to the beginning of the API and write disable to the end
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* None
Changes since [v1]:
* None
drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index f93252d0da5b..d3156446ff27 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -628,6 +628,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
u32 val, ctrl, num_ctrls;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ /*
+ * Enable DBI read-only registers for writing/updating configuration.
+ * Write permission gets disabled towards the end of this function.
+ */
+ dw_pcie_dbi_ro_wr_en(pci);
+
dw_pcie_setup(pci);
if (!pp->ops->msi_host_init) {
@@ -650,12 +656,10 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
/* Setup interrupt pins */
- dw_pcie_dbi_ro_wr_en(pci);
val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
val &= 0xffff00ff;
val |= 0x00000100;
dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
- dw_pcie_dbi_ro_wr_dis(pci);
/* Setup bus numbers */
val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
@@ -687,15 +691,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
- /* Enable write permission for the DBI read-only register */
- dw_pcie_dbi_ro_wr_en(pci);
/* Program correct class for RC */
dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
- /* Better disable write permission right after the update */
- dw_pcie_dbi_ro_wr_dis(pci);
dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
val |= PORT_LOGIC_SPEED_CHANGE;
dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
+
+ dw_pcie_dbi_ro_wr_dis(pci);
}
EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
--
2.17.1
next prev parent reply other threads:[~2019-06-24 9:14 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-24 9:14 [PATCH V11 00/12] Add Tegra194 PCIe support Vidya Sagar
2019-06-24 9:14 ` [PATCH V11 01/12] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-06-27 14:38 ` Lorenzo Pieralisi
2019-07-01 12:42 ` Vidya Sagar
2019-06-24 9:14 ` [PATCH V11 02/12] PCI: Disable MSI for Tegra root ports Vidya Sagar
2019-06-24 9:14 ` Vidya Sagar [this message]
2019-06-27 14:58 ` [PATCH V11 03/12] PCI: dwc: Perform dbi regs write lock towards the end Lorenzo Pieralisi
2019-06-27 15:33 ` Vidya Sagar
2019-06-27 15:50 ` Lorenzo Pieralisi
2019-06-27 16:52 ` Vidya Sagar
2019-06-24 9:14 ` [PATCH V11 04/12] PCI: dwc: Move config space capability search API Vidya Sagar
2019-06-24 9:14 ` [PATCH V11 05/12] PCI: dwc: Add ext " Vidya Sagar
2019-06-24 9:14 ` [PATCH V11 06/12] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-06-24 9:15 ` [PATCH V11 07/12] PCI: dwc: Add support to enable " Vidya Sagar
2019-06-24 9:15 ` [PATCH V11 08/12] dt-bindings: Add PCIe supports-clkreq property Vidya Sagar
2019-06-24 9:15 ` [PATCH V11 09/12] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar
2019-06-24 9:15 ` [PATCH V11 10/12] dt-bindings: PHY: P2U: Add Tegra194 P2U block Vidya Sagar
2019-06-24 9:15 ` [PATCH V11 11/12] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-06-24 9:15 ` [PATCH V11 12/12] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
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