* [v1 2/3] dt/bindings: clk: Add DT bindings for LS1028A Display output interface
@ 2019-08-12 10:02 Wen He
2019-08-13 18:30 ` Stephen Boyd
0 siblings, 1 reply; 3+ messages in thread
From: Wen He @ 2019-08-12 10:02 UTC (permalink / raw)
To: Rob Herring, Michael Turquette, Stephen Boyd, Mark Rutland,
Shawn Guo, devicetree, linux-clk, linux-kernel
Cc: leoyang.li, liviu.dudau, Wen He
Add DT bindings documentmation for the Clock of the LS1028A Display
output interface.
Signed-off-by: Wen He <wen.he_1@nxp.com>
---
.../devicetree/bindings/clock/fsl,plldig.txt | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/fsl,plldig.txt
diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.txt b/Documentation/devicetree/bindings/clock/fsl,plldig.txt
new file mode 100644
index 000000000000..29c5a6117809
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fsl,plldig.txt
@@ -0,0 +1,26 @@
+NXP QorIQ Layerscape LS1028A Display output interface Clock
+===========================================================
+
+Required properties:
+ - compatible: shall contain "fsl,ls1028a-plldig"
+ - reg: Physical base address and size of the block registers
+ - #clock-cells: shall contain 1.
+ - clocks: a phandle + clock-specifier pairs, here should be
+ specify the reference clock of the system
+
+
+Example:
+
+/ {
+ ...
+
+ dpclk: clock-controller@f1f0000 {
+ compatible = "fsl,ls1028a-plldig";
+ reg = <0x0 0xf1f0000 0x0 0xffff>;
+ #clock-cells = <1>;
+ clocks = <&osc_27m>;
+ };
+
+ ...
+};
+
--
2.17.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [v1 2/3] dt/bindings: clk: Add DT bindings for LS1028A Display output interface
2019-08-12 10:02 [v1 2/3] dt/bindings: clk: Add DT bindings for LS1028A Display output interface Wen He
@ 2019-08-13 18:30 ` Stephen Boyd
2019-08-14 9:49 ` [EXT] " Wen He
0 siblings, 1 reply; 3+ messages in thread
From: Stephen Boyd @ 2019-08-13 18:30 UTC (permalink / raw)
To: Mark Rutland, Michael Turquette, Rob Herring, Shawn Guo,
devicetree, linux-clk, linux-kernel
Cc: leoyang.li, liviu.dudau, Wen He
Quoting Wen He (2019-08-12 03:02:16)
> diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.txt b/Documentation/devicetree/bindings/clock/fsl,plldig.txt
> new file mode 100644
> index 000000000000..29c5a6117809
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/fsl,plldig.txt
> @@ -0,0 +1,26 @@
> +NXP QorIQ Layerscape LS1028A Display output interface Clock
> +===========================================================
Can you convert this to YAML?
> +
> +Required properties:
> + - compatible: shall contain "fsl,ls1028a-plldig"
> + - reg: Physical base address and size of the block registers
> + - #clock-cells: shall contain 1.
As I said in the previous patch, this should probably be 0. Also, please
order this before the driver in the patch series and thread your
messages please. If you use git-send-email this is done for you pretty
easily.
> + - clocks: a phandle + clock-specifier pairs, here should be
> + specify the reference clock of the system
> +
> +
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [EXT] Re: [v1 2/3] dt/bindings: clk: Add DT bindings for LS1028A Display output interface
2019-08-13 18:30 ` Stephen Boyd
@ 2019-08-14 9:49 ` Wen He
0 siblings, 0 replies; 3+ messages in thread
From: Wen He @ 2019-08-14 9:49 UTC (permalink / raw)
To: Stephen Boyd, Mark Rutland, Michael Turquette, Rob Herring,
Shawn Guo, devicetree, linux-clk, linux-kernel
Cc: Leo Li, liviu.dudau
> -----Original Message-----
> From: Stephen Boyd <sboyd@kernel.org>
> Sent: 2019年8月14日 2:30
> To: Mark Rutland <mark.rutland@arm.com>; Michael Turquette
> <mturquette@baylibre.com>; Rob Herring <robh+dt@kernel.org>; Shawn Guo
> <shawnguo@kernel.org>; Wen He <wen.he_1@nxp.com>;
> devicetree@vger.kernel.org; linux-clk@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Cc: Leo Li <leoyang.li@nxp.com>; liviu.dudau@arm.com; Wen He
> <wen.he_1@nxp.com>
> Subject: [EXT] Re: [v1 2/3] dt/bindings: clk: Add DT bindings for LS1028A
> Display output interface
>
> Caution: EXT Email
>
> Quoting Wen He (2019-08-12 03:02:16)
> > diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.txt
> > b/Documentation/devicetree/bindings/clock/fsl,plldig.txt
> > new file mode 100644
> > index 000000000000..29c5a6117809
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/fsl,plldig.txt
> > @@ -0,0 +1,26 @@
> > +NXP QorIQ Layerscape LS1028A Display output interface Clock
> > +===========================================================
>
> Can you convert this to YAML?
Sure, no problem.
>
> > +
> > +Required properties:
> > + - compatible: shall contain "fsl,ls1028a-plldig"
> > + - reg: Physical base address and size of the block registers
> > + - #clock-cells: shall contain 1.
>
> As I said in the previous patch, this should probably be 0. Also, please order
> this before the driver in the patch series and thread your messages please. If
> you use git-send-email this is done for you pretty easily.
Understand, Will prepare and send next version patch.
Best Regards,
Wen
>
> > + - clocks: a phandle + clock-specifier pairs, here should be
> > + specify the reference clock of the system
> > +
> > +
^ permalink raw reply [flat|nested] 3+ messages in thread
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2019-08-12 10:02 [v1 2/3] dt/bindings: clk: Add DT bindings for LS1028A Display output interface Wen He
2019-08-13 18:30 ` Stephen Boyd
2019-08-14 9:49 ` [EXT] " Wen He
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