[PATCH 0/3] arm/arm64: dts: allwinner: Add PMU nodes

[PATCH 0/3] arm/arm64: dts: allwinner: Add PMU nodes

[Andre Przywara]

Arm Cortex cores contain a Performance Monitoring Unit (PMU), that needs
to be connected to the GIC distributor to be able to trigger interrupts.
The actual interrupt IDs are an integration choice, so need to be
advertised via the DT.

This series adds the DT nodes to the H3, H5 and H6 SoC .dtsi files.
The interrupt IDs are not always as described in the manual (off by 4
for the A64 and H5), so the IRQs have been both tested in U-Boot and
verified in Linux, using "perf record" (which requires working IRQs).

Cheers,
Andre.

Andre Przywara (3):
  arm64: dts: allwinner: H6: Add PMU mode
  arm64: dts: allwinner: H5: Add PMU node
  arm: dts: allwinner: H3: Add PMU node

 arch/arm/boot/dts/sun8i-h3.dtsi              | 15 ++++++++++++---
 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 16 +++++++++++++---
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
 3 files changed, 35 insertions(+), 6 deletions(-)

-- 
2.14.5

[PATCH 1/3] arm64: dts: allwinner: H6: Add PMU mode

[Andre Przywara]

Add the Performance Monitoring Unit (PMU) device tree node to the H6
.dtsi, which tells DT users which interrupts are triggered by PMU
overflow events on each core. The numbers come from the manual and have
been checked in U-Boot and with perf in Linux.

Tested with perf record and taskset on a Pine H64.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 29824081b43b..86a77b1734e0 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -70,6 +70,16 @@
 		clock-output-names = "ext_osc32k";
 	};
 
+        pmu {
+		compatible = "arm,cortex-a53-pmu",
+			     "arm,armv8-pmuv3";
+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
 	psci {
 		compatible = "arm,psci-0.2";
 		method = "smc";
-- 
2.14.5

[PATCH 2/3] arm64: dts: allwinner: H5: Add PMU node

[Andre Przywara]

Add the Performance Monitoring Unit (PMU) device tree node to the H5
.dtsi, which tells DT users which interrupts are triggered by PMU
overflow events on each core.
As with the A64, the interrupt numbers from the manual were wrong (off
by 4), the actual SPI IDs have been gathered in U-Boot, and were
verified with perf in Linux.

Tested with perf record and taskset on an OrangePi PC2.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index e92c4de5bf3b..7c775a918a4e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -54,21 +54,21 @@
 			enable-method = "psci";
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <1>;
 			enable-method = "psci";
 		};
 
-		cpu@2 {
+		cpu2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <2>;
 			enable-method = "psci";
 		};
 
-		cpu@3 {
+		cpu3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <3>;
@@ -76,6 +76,16 @@
 		};
 	};
 
+	pmu {
+		compatible = "arm,cortex-a53-pmu",
+			     "arm,armv8-pmuv3";
+		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
 	psci {
 		compatible = "arm,psci-0.2";
 		method = "smc";
-- 
2.14.5

[PATCH 3/3] arm: dts: allwinner: H3: Add PMU node

[Andre Przywara]

Add the Performance Monitoring Unit (PMU) device tree node to the H3
.dtsi, which tells DT users which interrupts are triggered by PMU
overflow events on each core. The numbers come from the manual and have
been checked in U-Boot and with perf in Linux.

Tested with perf record and taskset on an OrangePi Zero.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index fe773c72a69b..b4f1673df9ee 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -80,7 +80,7 @@
 			#cooling-cells = <2>;
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <1>;
@@ -90,7 +90,7 @@
 			#cooling-cells = <2>;
 		};
 
-		cpu@2 {
+		cpu2: cpu@2 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <2>;
@@ -100,7 +100,7 @@
 			#cooling-cells = <2>;
 		};
 
-		cpu@3 {
+		cpu3: cpu@3 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <3>;
@@ -111,6 +111,15 @@
 		};
 	};
 
+	pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-- 
2.14.5

Re: [PATCH 1/3] arm64: dts: allwinner: H6: Add PMU mode

[Maxime Ripard]

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On Thu, Nov 21, 2019 at 01:18:33AM +0000, Andre Przywara wrote:
> Add the Performance Monitoring Unit (PMU) device tree node to the H6
> .dtsi, which tells DT users which interrupts are triggered by PMU
> overflow events on each core. The numbers come from the manual and have
> been checked in U-Boot and with perf in Linux.
>
> Tested with perf record and taskset on a Pine H64.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Queued all three patches for 5.6, thanks for taking the time to do
this.

> ---
>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index 29824081b43b..86a77b1734e0 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -70,6 +70,16 @@
>  		clock-output-names = "ext_osc32k";
>  	};
>
> +        pmu {

This was indented with spaces however, unlike the rest of the DT. I've
fixed it while applying.

Maxime

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Re: [PATCH 1/3] arm64: dts: allwinner: H6: Add PMU mode

[Andre Przywara]

On Thu, 21 Nov 2019 08:22:30 +0100
Maxime Ripard <maxime@cerno.tech> wrote:

Hi,

> On Thu, Nov 21, 2019 at 01:18:33AM +0000, Andre Przywara wrote:
> > Add the Performance Monitoring Unit (PMU) device tree node to the H6
> > .dtsi, which tells DT users which interrupts are triggered by PMU
> > overflow events on each core. The numbers come from the manual and have
> > been checked in U-Boot and with perf in Linux.
> >
> > Tested with perf record and taskset on a Pine H64.
> >
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>  
> 
> Queued all three patches for 5.6, thanks for taking the time to do
> this.
> 
> > ---
> >  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > index 29824081b43b..86a77b1734e0 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > @@ -70,6 +70,16 @@
> >  		clock-output-names = "ext_osc32k";
> >  	};
> >
> > +        pmu {  
> 
> This was indented with spaces however, unlike the rest of the DT. I've
> fixed it while applying.

Shoot, thinks for fixing this up, also for queuing it!

Cheers,
Andre.