[RFC PATCH 0/1] arm64: dts: added basic DTS for qmx8 congatec board

devicetree.vger.kernel.org archive mirror
 help / color / mirror / Atom feed

* [RFC PATCH 0/1] arm64: dts: added basic DTS for qmx8 congatec board
@ 2019-10-29 12:22 Oliver Graute
  2019-10-29 12:23 ` [RFC PATCH 1/1] " Oliver Graute
  0 siblings, 1 reply; 7+ messages in thread
From: Oliver Graute @ 2019-10-29 12:22 UTC (permalink / raw)
  To: shawnguo
  Cc: oliver.graute, aisheng.dong, peng.fan, Oliver Graute,
	Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team,
	Fabio Estevam, NXP Linux Team, Li Yang, Manivannan Sadhasivam,
	Lucas Stach, Anson Huang, Pramod Kumar, Jon Nettleton,
	Stoica Cosmin-Stefan, devicetree, linux-kernel, linux-arm-kernel

This patch is ontop of Aisheng Dongs clock driver and imx8 changes for the
imx8qm.
https://patchwork.kernel.org/patch/11143321/
https://patchwork.kernel.org/patch/11138099/

I observe random crashes with this devicetree like this:

[  676.355973] fec 5b040000.ethernet eth0: MDIO read timeout
[  676.361455] ------------[ cut here ]------------
[  676.366087] WARNING: CPU: 0 PID: 208 at drivers/net/phy/phy.c:708 phy_error+0x10/0x58
[  676.373924] Modules linked in:
[  676.376984] CPU: 0 PID: 208 Comm: kworker/u8:2 Not tainted 5.3.0-rc7-next-20190904-00034-gdc1fd1a2104b #5
[  676.386553] Hardware name: Congatec QMX8 Qseven series (DT)
[  676.392128] Workqueue: events_power_efficient phy_state_machine
[  676.398049] pstate: 60000005 (nZCv daif -PAN -UAO)
[  676.402842] pc : phy_error+0x10/0x58
[  676.406413] lr : phy_state_machine+0xa8/0x168
[  676.410765] sp : ffff80001217bd60
[  676.414083] x29: ffff80001217bd60 x28: 0000000000000000
[  676.419399] x27: ffff0008f6b64338 x26: ffff800011073b98
[  676.424715] x25: 0000000000000000 x24: 00000000ffffff92
[  676.430032] x23: ffff0008f70c1000 x22: ffff0008f70c13e0
[  676.435348] x21: 0000000000000004 x20: ffff0008f70c1438
[  676.440665] x19: ffff0008f70c1000 x18: 0000000000000010
[  676.445973] x17: 0000000000000000 x16: 0000000000000000
[  676.451290] x15: ffffffffffffffff x14: ffff8000117398c8
[  676.456607] x13: ffff80009217b8b7 x12: ffff80001217b8bf
[  676.461923] x11: ffff800011752000 x10: ffff80001217b840
[  676.467240] x9 : 00000000ffffffd0 x8 : ffff800010698408
[  676.472557] x7 : 0000000000000151 x6 : 000000015f8c5440
[  676.477874] x5 : ffff0008f8341db0 x4 : ffff0008f6500000
[  676.483190] x3 : ffff0008f70c1438 x2 : 0000000000000000
[  676.488507] x1 : 0000000000000000 x0 : ffff0008f70c1000
[  676.493827] Call trace:
[  676.496273]  phy_error+0x10/0x58
[  676.499499]  phy_state_machine+0xa8/0x168
[  676.503510]  process_one_work+0x1e0/0x350
[  676.507518]  worker_thread+0x40/0x480
[  676.511179]  kthread+0x120/0x128
[  676.514413]  ret_from_fork+0x10/0x18
[  676.517990] ---[ end trace 919aac09d207cb93 ]---
[  676.522931] fec 5b040000.ethernet eth0: Link is Down

Some hints how to fix this?

Oliver Graute (1):
  arm64: dts: added basic DTS for qmx8 congatec board

 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 .../boot/dts/freescale/imx8qm-cgt-qmx8.dts    | 391 ++++++++++++++++++
 2 files changed, 392 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-cgt-qmx8.dts

-- 
2.17.1


^ permalink raw reply	[flat|nested] 7+ messages in thread

* [RFC PATCH 1/1] arm64: dts: added basic DTS for qmx8 congatec board
  2019-10-29 12:22 [RFC PATCH 0/1] arm64: dts: added basic DTS for qmx8 congatec board Oliver Graute
@ 2019-10-29 12:23 ` Oliver Graute
  2019-11-14 10:48   ` oliver.graute
  2019-11-28  9:29   ` Marc Gonzalez
  0 siblings, 2 replies; 7+ messages in thread
From: Oliver Graute @ 2019-10-29 12:23 UTC (permalink / raw)
  To: shawnguo
  Cc: oliver.graute, aisheng.dong, peng.fan, Oliver Graute,
	Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team,
	Fabio Estevam, NXP Linux Team, Li Yang, Lucas Stach,
	Pramod Kumar, Manivannan Sadhasivam, Anson Huang,
	Bhaskar Upadhaya, Stoica Cosmin-Stefan, devicetree, linux-kernel,
	linux-arm-kernel

Add basic dts support for a Congatec iMX8QM Qseven Board

Product Page: https://www.congatec.com/de/produkte/qseven/conga-qmx8x.html

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
---
 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 .../boot/dts/freescale/imx8qm-cgt-qmx8.dts    | 391 ++++++++++++++++++
 2 files changed, 392 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-cgt-qmx8.dts

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 5f7e4aa0da60..a3639654c567 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8qm-cgt-qmx8.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
 
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-cgt-qmx8.dts b/arch/arm64/boot/dts/freescale/imx8qm-cgt-qmx8.dts
new file mode 100644
index 000000000000..e1597bbfe0f5
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-cgt-qmx8.dts
@@ -0,0 +1,391 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ * Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
+ */
+/dts-v1/;
+
+#include "imx8qm.dtsi"
+
+/ {
+	model = "Congatec QMX8 Qseven series";
+	compatible = "fsl,imx8qm-qmx8", "fsl,imx8qm";
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
+		stdout-path = &lpuart0;
+	};
+
+	cpus {
+		/delete-node/ cpu-map;
+		/delete-node/ cpu@100;
+		/delete-node/ cpu@101;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000 0 0x40000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0 0x28000000>;
+			alloc-ranges = <0 0x80000000 0 0x80000000>;
+			linux,cma-default;
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_audio: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "cs42888_supply";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		reg_usdhc2_vmmc: usdhc2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "sw-3p3-sd1";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			off-on-delay = <3000>;
+		};
+
+		reg_usdhc3_vmmc: usdhc3_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "sw-3p3-sd2";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&lsio_gpio4 9 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			off-on-delay = <3000>;
+		};
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	fsl,rgmii_txc_dly;
+	fsl,rgmii_rxc_dly;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <6>;
+			at803x,eee-disabled;
+			at803x,vddio-1p8v;
+		};
+	};
+};
+
+&i2c0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c0>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	rtc_ext: m41t62@68 {
+		compatible = "st,m41t62";
+		reg = <0x68>;
+	};
+};
+
+&lpuart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart0>;
+	status = "okay";
+};
+
+&lpuart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart1>;
+	status = "okay";
+};
+
+&lsio_gpio2 {
+	status = "okay";
+};
+
+&lsio_gpio5 {
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	fsl,tuning-start-tap = <20>;
+	fsl,tuning-step= <2>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc3_vmmc>;
+	fsl,tuning-start-tap = <20>;
+	fsl,tuning-step= <2>;
+	no-1-8-v;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx8qm-qmx8 {
+
+		pinctrl_hog: hoggrp{
+			fsl,pins = <
+				IMX8QM_M40_GPIO0_01_LSIO_GPIO0_IO09		0x00000021
+				IMX8QM_USB_SS3_TC1_LSIO_GPIO4_IO04		0x00000021
+				IMX8QM_M40_GPIO0_00_LSIO_GPIO0_IO08		0x00000021
+				IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07		0x00000021
+				IMX8QM_SPDIF0_TX_LSIO_GPIO2_IO15		0x00000021
+				IMX8QM_FLEXCAN1_RX_LSIO_GPIO3_IO31		0x00000021
+				IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08		0x00000021
+				IMX8QM_FLEXCAN1_TX_LSIO_GPIO4_IO00		0x00000021
+				IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09		0x00000021
+			>;
+		};
+
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				IMX8QM_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO		0x06000020
+				IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
+				IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000020
+				IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000020
+				IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000020
+				IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000020
+				IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000020
+				IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000020
+				IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
+				IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000020
+				IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000020
+				IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000020
+				IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000020
+			>;
+		};
+
+		pinctrl_lpi2c0: lpi2c0grp {
+			fsl,pins = <
+				IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL	0xc600004c
+				IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA	0xc600004c
+			>;
+		};
+
+		pinctrl_lpi2c1: lpi2c1grp {
+			fsl,pins = <
+				IMX8QM_GPT0_CLK_DMA_I2C1_SCL		0xc600004c
+				IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA	0xc600004c
+			>;
+		};
+
+		pinctrl_lpuart0: lpuart0grp {
+			fsl,pins = <
+				IMX8QM_UART0_RX_DMA_UART0_RX		0x06000020
+				IMX8QM_UART0_TX_DMA_UART0_TX		0x06000020
+			>;
+		};
+
+		pinctrl_lpuart1: lpuart1grp {
+			fsl,pins = <
+				IMX8QM_UART1_RX_DMA_UART1_RX		0x06000020
+				IMX8QM_UART1_TX_DMA_UART1_TX		0x06000020
+				IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B	0x06000020
+				IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B	0x06000020
+			>;
+		};
+
+		pinctrl_lpuart3: lpuart3grp {
+			fsl,pins = <
+				IMX8QM_M41_GPIO0_00_DMA_UART3_RX	0x06000020
+				IMX8QM_M41_GPIO0_01_DMA_UART3_TX	0x06000020
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+				IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
+				IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
+				IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+				IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21	0x00000021
+				IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22	0x00000021
+				IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK	0x06000041
+				IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD	0x00000021
+				IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
+				IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
+				IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
+				IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
+				IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK	0x06000040
+				IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD	0x00000020
+				IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
+				IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
+				IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
+				IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
+				IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK	0x06000040
+				IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD	0x00000020
+				IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
+				IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
+				IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
+				IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
+				IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc3_gpio: usdhc3grpgpio {
+			fsl,pins = <
+				IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09	0x00000021
+				IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK	0x06000041
+				IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD	0x00000021
+				IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0	0x00000021
+				IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1	0x00000021
+				IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2	0x00000021
+				IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3	0x00000021
+				IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+			fsl,pins = <
+				IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK	0x06000040
+				IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD	0x00000020
+				IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0	0x00000020
+				IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1	0x00000020
+				IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2	0x00000020
+				IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3	0x00000020
+				IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+			fsl,pins = <
+				IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK	0x06000040
+				IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD	0x00000020
+				IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0	0x00000020
+				IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1	0x00000020
+				IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2	0x00000020
+				IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3	0x00000020
+				IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000020
+			>;
+		};
+	};
+};
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [RFC PATCH 1/1] arm64: dts: added basic DTS for qmx8 congatec board
  2019-10-29 12:23 ` [RFC PATCH 1/1] " Oliver Graute
@ 2019-11-14 10:48   ` oliver.graute
  2019-11-28  9:29   ` Marc Gonzalez
  1 sibling, 0 replies; 7+ messages in thread
From: oliver.graute @ 2019-11-14 10:48 UTC (permalink / raw)
  To: shawnguo
  Cc: aisheng.dong, peng.fan, Rob Herring, Mark Rutland, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Li Yang,
	Lucas Stach, Pramod Kumar, Manivannan Sadhasivam, Anson Huang,
	Bhaskar Upadhaya, Stoica Cosmin-Stefan, devicetree, linux-kernel,
	linux-arm-kernel

On 29/10/19, Oliver Graute wrote:
> Add basic dts support for a Congatec iMX8QM Qseven Board
> 
> Product Page: https://www.congatec.com/de/produkte/qseven/conga-qmx8x.html

just noticed that above product link is wrong. The right one is this:

https://www.congatec.com/de/produkte/qseven/conga-qmx8.html

Best regards,

Oliver

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [RFC PATCH 1/1] arm64: dts: added basic DTS for qmx8 congatec board
  2019-10-29 12:23 ` [RFC PATCH 1/1] " Oliver Graute
  2019-11-14 10:48   ` oliver.graute
@ 2019-11-28  9:29   ` Marc Gonzalez
  2019-11-28  9:55     ` Oliver Graute
  1 sibling, 1 reply; 7+ messages in thread
From: Marc Gonzalez @ 2019-11-28  9:29 UTC (permalink / raw)
  To: Oliver Graute; +Cc: Linux ARM, DT, Rob Herring

On 29/10/2019 13:23, Oliver Graute wrote:

> +&fec1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_fec1>;
> +	phy-mode = "rgmii";
> +	phy-handle = <&ethphy0>;
> +	fsl,magic-packet;
> +	fsl,rgmii_txc_dly;
> +	fsl,rgmii_rxc_dly;
> +	status = "okay";

The two fsl,rgmii* properties do not exist in mainline.
I suppose there were copied from downstream?

> +
> +	mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		ethphy0: ethernet-phy@0 {
> +			compatible = "ethernet-phy-ieee802.3-c22";
> +			reg = <6>;
> +			at803x,eee-disabled;
> +			at803x,vddio-1p8v;
> +		};
> +	};
> +};

Regards.

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [RFC PATCH 1/1] arm64: dts: added basic DTS for qmx8 congatec board
  2019-11-28  9:29   ` Marc Gonzalez
@ 2019-11-28  9:55     ` Oliver Graute
  2019-11-28 10:31       ` Marc Gonzalez
  0 siblings, 1 reply; 7+ messages in thread
From: Oliver Graute @ 2019-11-28  9:55 UTC (permalink / raw)
  To: Marc Gonzalez; +Cc: DT, Rob Herring, Linux ARM

On 28/11/19, Marc Gonzalez wrote:
> On 29/10/2019 13:23, Oliver Graute wrote:
> 
> > +&fec1 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_fec1>;
> > +	phy-mode = "rgmii";
> > +	phy-handle = <&ethphy0>;
> > +	fsl,magic-packet;
> > +	fsl,rgmii_txc_dly;
> > +	fsl,rgmii_rxc_dly;
> > +	status = "okay";
> 
> The two fsl,rgmii* properties do not exist in mainline.
> I suppose there were copied from downstream?

you are right, I'll remove them.

thx for your feedback.

Best regards,

Oliver

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [RFC PATCH 1/1] arm64: dts: added basic DTS for qmx8 congatec board
  2019-11-28  9:55     ` Oliver Graute
@ 2019-11-28 10:31       ` Marc Gonzalez
  2019-11-29  7:56         ` Oliver Graute
  0 siblings, 1 reply; 7+ messages in thread
From: Marc Gonzalez @ 2019-11-28 10:31 UTC (permalink / raw)
  To: Oliver Graute; +Cc: DT, Rob Herring, Linux ARM

On 28/11/2019 10:55, Oliver Graute wrote:

> On 28/11/19, Marc Gonzalez wrote:
> 
>> On 29/10/2019 13:23, Oliver Graute wrote:
>>
>>> +&fec1 {
>>> +	pinctrl-names = "default";
>>> +	pinctrl-0 = <&pinctrl_fec1>;
>>> +	phy-mode = "rgmii";
>>> +	phy-handle = <&ethphy0>;
>>> +	fsl,magic-packet;
>>> +	fsl,rgmii_txc_dly;
>>> +	fsl,rgmii_rxc_dly;
>>> +	status = "okay";
>>
>> The two fsl,rgmii* properties do not exist in mainline.
>> I suppose there were copied from downstream?
> 
> you are right, I'll remove them.

You should first check what the downstream driver does for them.
And check if there is an equivalent action in mainline.
These delays tend to be required for the PHY to work at all.

Regards.

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [RFC PATCH 1/1] arm64: dts: added basic DTS for qmx8 congatec board
  2019-11-28 10:31       ` Marc Gonzalez
@ 2019-11-29  7:56         ` Oliver Graute
  0 siblings, 0 replies; 7+ messages in thread
From: Oliver Graute @ 2019-11-29  7:56 UTC (permalink / raw)
  To: Marc Gonzalez
  Cc: DTR, Rob Herring,
	linuxppc-dev@lists.ozlabs.org Pantelis Antoniou,
	netdev@vger.kernel.org Linux ARM

On 28/11/19, Marc Gonzalez wrote:
> On 28/11/2019 10:55, Oliver Graute wrote:
> 
> > On 28/11/19, Marc Gonzalez wrote:
> > 
> >> On 29/10/2019 13:23, Oliver Graute wrote:
> >>
> >>> +&fec1 {
> >>> +	pinctrl-names = "default";
> >>> +	pinctrl-0 = <&pinctrl_fec1>;
> >>> +	phy-mode = "rgmii";
> >>> +	phy-handle = <&ethphy0>;
> >>> +	fsl,magic-packet;
> >>> +	fsl,rgmii_txc_dly;
> >>> +	fsl,rgmii_rxc_dly;
> >>> +	status = "okay";
> >>
> >> The two fsl,rgmii* properties do not exist in mainline.
> >> I suppose there were copied from downstream?
> > 
> > you are right, I'll remove them.
> 
> You should first check what the downstream driver does for them.
> And check if there is an equivalent action in mainline.
> These delays tend to be required for the PHY to work at all.

ok as far as I see there is currently no equilant action in mainline.
Downstream linux-imx use rgmii_txc_dly and rgmii_rxc_dly in fec_probe()
and fec_restart() for some imx8qm-fec and imx8mq-fec PHY delay quirks.
Perhaps this missing quirks are related to the random crashes in that
driver I have with imx8qm.

[  129.211959] fec 5b040000.ethernet eth0: rcv is not +last
[  129.217300] fec 5b040000.ethernet eth0: rcv is not +last
[  129.222647] fec 5b040000.ethernet eth0: rcv is not +last
[  129.227966] fec 5b040000.ethernet eth0: rcv is not +last
[  129.233282] fec 5b040000.ethernet eth0: rcv is not +last

Best regards,

Oliver

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2019-11-29  7:57 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-29 12:22 [RFC PATCH 0/1] arm64: dts: added basic DTS for qmx8 congatec board Oliver Graute
2019-10-29 12:23 ` [RFC PATCH 1/1] " Oliver Graute
2019-11-14 10:48   ` oliver.graute
2019-11-28  9:29   ` Marc Gonzalez
2019-11-28  9:55     ` Oliver Graute
2019-11-28 10:31       ` Marc Gonzalez
2019-11-29  7:56         ` Oliver Graute

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).