* [PATCH] dt-bindings: reset: meson8b: fix duplicate reset IDs
@ 2019-11-30 18:53 Martin Blumenstingl
2019-12-09 22:25 ` Kevin Hilman
0 siblings, 1 reply; 2+ messages in thread
From: Martin Blumenstingl @ 2019-11-30 18:53 UTC (permalink / raw)
To: p.zabel, linux-amlogic
Cc: linux-kernel, linux-arm-kernel, devicetree, narmstrong,
Martin Blumenstingl
According to the public S805 datasheet the RESET2 register uses the
following bits for the PIC_DC, PSC and NAND reset lines:
- PIC_DC is at bit 3 (meaning: RESET_VD_RMEM + 3)
- PSC is at bit 4 (meaning: RESET_VD_RMEM + 4)
- NAND is at bit 5 (meaning: RESET_VD_RMEM + 4)
Update the reset IDs of these three reset lines so they don't conflict
with PIC_DC and map to the actual hardware reset lines.
Fixes: 79795e20a184eb ("dt-bindings: reset: Add bindings for the Meson SoC Reset Controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
include/dt-bindings/reset/amlogic,meson8b-reset.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/dt-bindings/reset/amlogic,meson8b-reset.h b/include/dt-bindings/reset/amlogic,meson8b-reset.h
index c614438bcbdb..fbc524a900da 100644
--- a/include/dt-bindings/reset/amlogic,meson8b-reset.h
+++ b/include/dt-bindings/reset/amlogic,meson8b-reset.h
@@ -46,9 +46,9 @@
#define RESET_VD_RMEM 64
#define RESET_AUDIN 65
#define RESET_DBLK 66
-#define RESET_PIC_DC 66
-#define RESET_PSC 66
-#define RESET_NAND 66
+#define RESET_PIC_DC 67
+#define RESET_PSC 68
+#define RESET_NAND 69
#define RESET_GE2D 70
#define RESET_PARSER_REG 71
#define RESET_PARSER_FETCH 72
--
2.24.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] dt-bindings: reset: meson8b: fix duplicate reset IDs
2019-11-30 18:53 [PATCH] dt-bindings: reset: meson8b: fix duplicate reset IDs Martin Blumenstingl
@ 2019-12-09 22:25 ` Kevin Hilman
0 siblings, 0 replies; 2+ messages in thread
From: Kevin Hilman @ 2019-12-09 22:25 UTC (permalink / raw)
To: Martin Blumenstingl, p.zabel, linux-amlogic
Cc: linux-kernel, linux-arm-kernel, devicetree, narmstrong,
Martin Blumenstingl
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> According to the public S805 datasheet the RESET2 register uses the
> following bits for the PIC_DC, PSC and NAND reset lines:
> - PIC_DC is at bit 3 (meaning: RESET_VD_RMEM + 3)
> - PSC is at bit 4 (meaning: RESET_VD_RMEM + 4)
> - NAND is at bit 5 (meaning: RESET_VD_RMEM + 4)
>
> Update the reset IDs of these three reset lines so they don't conflict
> with PIC_DC and map to the actual hardware reset lines.
>
> Fixes: 79795e20a184eb ("dt-bindings: reset: Add bindings for the Meson SoC Reset Controller")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Queued as a fix for v5.5-rc,
Thanks,
Kevin
^ permalink raw reply [flat|nested] 2+ messages in thread
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2019-11-30 18:53 [PATCH] dt-bindings: reset: meson8b: fix duplicate reset IDs Martin Blumenstingl
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