* [PATCH v5 0/3] Add Unisoc's SC9863A support
@ 2019-12-23 9:29 Chunyan Zhang
2019-12-23 9:29 ` [PATCH v5 1/3] dt-bindings: arm: sprd: add global registers bindings Chunyan Zhang
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Chunyan Zhang @ 2019-12-23 9:29 UTC (permalink / raw)
To: soc, Rob Herring, Mark Rutland
Cc: devicetree, linux-kernel, Orson Zhai, Baolin Wang, Chunyan Zhang,
Chunyan Zhang
From: Chunyan Zhang <chunyan.zhang@unisoc.com>
SC9863A has Octa-core ARM Cortex A55 application processor. Find more
details about it on the website: http://www.unisoc.com/sc9863a
Changes from v4:
* Removed syscon nodes which should be added when used.
* Added Acked-by from Rob Herring.
Changes from v3:
* Rebased on v5.5-rc1;
* Fix the cpu-map to put all cpus into the single cluster;
* Fixed a bindings error.
Changes from v2:
* Discard some dt-bindings patches which have been applied by Rob Herring.
* Added a new dt-binding file for sprd global-regs, also added a vendor directory for sprd.
* Moved sprd.yaml to the vendor directory.
* Addressed comments from Rob:
- fixed dtbs_check errors;
- move gic under to the bus node;
- removed msi-controller from gic, sinceSC9863A doesn't provide ITS;
- added specific compatible string for syscon nodes;
- cut down registers range of syscon nodes;
- removed unnecessary property "sprd,sc-id";
- added earlycon support in devicetree.
Changes from v1:
- Convert DT bindings to json-schema.
Chunyan Zhang (3):
dt-bindings: arm: sprd: add global registers bindings
dt-bindings: arm: move sprd board file to vendor directory
arm64: dts: Add Unisoc's SC9863A SoC support
.../bindings/arm/sprd/global-regs.yaml | 34 ++
.../bindings/arm/{ => sprd}/sprd.yaml | 2 +-
arch/arm64/boot/dts/sprd/Makefile | 3 +-
arch/arm64/boot/dts/sprd/sc9863a.dtsi | 523 ++++++++++++++++++
arch/arm64/boot/dts/sprd/sharkl3.dtsi | 78 +++
arch/arm64/boot/dts/sprd/sp9863a-1h10.dts | 39 ++
6 files changed, 677 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/sprd/global-regs.yaml
rename Documentation/devicetree/bindings/arm/{ => sprd}/sprd.yaml (92%)
create mode 100644 arch/arm64/boot/dts/sprd/sc9863a.dtsi
create mode 100644 arch/arm64/boot/dts/sprd/sharkl3.dtsi
create mode 100644 arch/arm64/boot/dts/sprd/sp9863a-1h10.dts
--
2.20.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v5 1/3] dt-bindings: arm: sprd: add global registers bindings
2019-12-23 9:29 [PATCH v5 0/3] Add Unisoc's SC9863A support Chunyan Zhang
@ 2019-12-23 9:29 ` Chunyan Zhang
2019-12-23 9:29 ` [PATCH v5 2/3] dt-bindings: arm: move sprd board file to vendor directory Chunyan Zhang
2019-12-23 9:29 ` [PATCH v5 3/3] arm64: dts: Add Unisoc's SC9863A SoC support Chunyan Zhang
2 siblings, 0 replies; 4+ messages in thread
From: Chunyan Zhang @ 2019-12-23 9:29 UTC (permalink / raw)
To: soc, Rob Herring, Mark Rutland
Cc: devicetree, linux-kernel, Orson Zhai, Baolin Wang, Chunyan Zhang,
Chunyan Zhang
From: Chunyan Zhang <chunyan.zhang@unisoc.com>
The global registers would be used by different peripheral devices which
we can see them as syscon clients which can use regmap interface that
syscon driver provides.
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
---
.../bindings/arm/sprd/global-regs.yaml | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/sprd/global-regs.yaml
diff --git a/Documentation/devicetree/bindings/arm/sprd/global-regs.yaml b/Documentation/devicetree/bindings/arm/sprd/global-regs.yaml
new file mode 100644
index 000000000000..012207166116
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/sprd/global-regs.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2019 Unisoc Inc.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/sprd/global-regs.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Unisoc Global Registers
+
+maintainers:
+ - Orson Zhai <orsonzhai@gmail.com>
+ - Baolin Wang <baolin.wang7@gmail.com>
+ - Chunyan Zhang <zhang.lyra@gmail.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - sprd,sc9860-glbregs
+ - sprd,sc9863a-glbregs
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+examples:
+ - |
+ apb_regs: syscon@402e0000 {
+ compatible = "sprd,sc9863a-glbregs", "syscon";
+ reg = <0x402e0000 0x4000>;
+ };
+
+...
--
2.20.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v5 2/3] dt-bindings: arm: move sprd board file to vendor directory
2019-12-23 9:29 [PATCH v5 0/3] Add Unisoc's SC9863A support Chunyan Zhang
2019-12-23 9:29 ` [PATCH v5 1/3] dt-bindings: arm: sprd: add global registers bindings Chunyan Zhang
@ 2019-12-23 9:29 ` Chunyan Zhang
2019-12-23 9:29 ` [PATCH v5 3/3] arm64: dts: Add Unisoc's SC9863A SoC support Chunyan Zhang
2 siblings, 0 replies; 4+ messages in thread
From: Chunyan Zhang @ 2019-12-23 9:29 UTC (permalink / raw)
To: soc, Rob Herring, Mark Rutland
Cc: devicetree, linux-kernel, Orson Zhai, Baolin Wang, Chunyan Zhang,
Chunyan Zhang, Rob Herring
From: Chunyan Zhang <chunyan.zhang@unisoc.com>
We've created a vendor directory for sprd, so move the board bindings to
there.
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/{ => sprd}/sprd.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
rename Documentation/devicetree/bindings/arm/{ => sprd}/sprd.yaml (92%)
diff --git a/Documentation/devicetree/bindings/arm/sprd.yaml b/Documentation/devicetree/bindings/arm/sprd/sprd.yaml
similarity index 92%
rename from Documentation/devicetree/bindings/arm/sprd.yaml
rename to Documentation/devicetree/bindings/arm/sprd/sprd.yaml
index c35fb845ccaa..0258a96bfbde 100644
--- a/Documentation/devicetree/bindings/arm/sprd.yaml
+++ b/Documentation/devicetree/bindings/arm/sprd/sprd.yaml
@@ -2,7 +2,7 @@
# Copyright 2019 Unisoc Inc.
%YAML 1.2
---
-$id: http://devicetree.org/schemas/arm/sprd.yaml#
+$id: http://devicetree.org/schemas/arm/sprd/sprd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Unisoc platforms device tree bindings
--
2.20.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v5 3/3] arm64: dts: Add Unisoc's SC9863A SoC support
2019-12-23 9:29 [PATCH v5 0/3] Add Unisoc's SC9863A support Chunyan Zhang
2019-12-23 9:29 ` [PATCH v5 1/3] dt-bindings: arm: sprd: add global registers bindings Chunyan Zhang
2019-12-23 9:29 ` [PATCH v5 2/3] dt-bindings: arm: move sprd board file to vendor directory Chunyan Zhang
@ 2019-12-23 9:29 ` Chunyan Zhang
2 siblings, 0 replies; 4+ messages in thread
From: Chunyan Zhang @ 2019-12-23 9:29 UTC (permalink / raw)
To: soc, Rob Herring, Mark Rutland
Cc: devicetree, linux-kernel, Orson Zhai, Baolin Wang, Chunyan Zhang,
Chunyan Zhang
From: Chunyan Zhang <chunyan.zhang@unisoc.com>
Add basic DT to support Unisoc's SC9863A, with this patch,
the board sp9863a-1h10 can run into console.
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
---
arch/arm64/boot/dts/sprd/Makefile | 3 +-
arch/arm64/boot/dts/sprd/sc9863a.dtsi | 523 ++++++++++++++++++++++
arch/arm64/boot/dts/sprd/sharkl3.dtsi | 78 ++++
arch/arm64/boot/dts/sprd/sp9863a-1h10.dts | 39 ++
4 files changed, 642 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/sprd/sc9863a.dtsi
create mode 100644 arch/arm64/boot/dts/sprd/sharkl3.dtsi
create mode 100644 arch/arm64/boot/dts/sprd/sp9863a-1h10.dts
diff --git a/arch/arm64/boot/dts/sprd/Makefile b/arch/arm64/boot/dts/sprd/Makefile
index 2bdc23804f40..f4f1f5148cc2 100644
--- a/arch/arm64/boot/dts/sprd/Makefile
+++ b/arch/arm64/boot/dts/sprd/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \
- sp9860g-1h10.dtb
+ sp9860g-1h10.dtb \
+ sp9863a-1h10.dtb
diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi
new file mode 100644
index 000000000000..cd80756c888d
--- /dev/null
+++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi
@@ -0,0 +1,523 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Unisoc SC9863A SoC DTS file
+ *
+ * Copyright (C) 2019, Unisoc Inc.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "sharkl3.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+ core1 {
+ cpu = <&CPU1>;
+ };
+ core2 {
+ cpu = <&CPU2>;
+ };
+ core3 {
+ cpu = <&CPU3>;
+ };
+ core4 {
+ cpu = <&CPU4>;
+ };
+ core5 {
+ cpu = <&CPU5>;
+ };
+ core6 {
+ cpu = <&CPU6>;
+ };
+ core7 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ cpu-idle-states = <&CORE_PD>;
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CORE_PD>;
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ cpu-idle-states = <&CORE_PD>;
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ cpu-idle-states = <&CORE_PD>;
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ cpu-idle-states = <&CORE_PD>;
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ cpu-idle-states = <&CORE_PD>;
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ cpu-idle-states = <&CORE_PD>;
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ cpu-idle-states = <&CORE_PD>;
+ };
+ };
+
+ idle-states {
+ entry-method = "arm,psci";
+ CORE_PD: core-pd {
+ compatible = "arm,idle-state";
+ entry-latency-us = <4000>;
+ exit-latency-us = <4000>;
+ min-residency-us = <10000>;
+ local-timer-stop;
+ arm,psci-suspend-param = <0x00010000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ soc {
+ gic: interrupt-controller@14000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ redistributor-stride = <0x0 0x20000>; /* 128KB stride */
+ #redistributor-regions = <1>;
+ interrupt-controller;
+ reg = <0x0 0x14000000 0 0x20000>, /* GICD */
+ <0x0 0x14040000 0 0x100000>; /* GICR */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ funnel@10001000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x10001000 0 0x1000>;
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel_soc_out_port: endpoint {
+ remote-endpoint = <&etb_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ funnel_soc_in_port: endpoint {
+ remote-endpoint =
+ <&funnel_ca55_out_port>;
+ };
+ };
+ };
+ };
+
+ etb@10003000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x10003000 0 0x1000>;
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ etb_in: endpoint {
+ remote-endpoint =
+ <&funnel_soc_out_port>;
+ };
+ };
+ };
+ };
+
+ funnel@12001000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x12001000 0 0x1000>;
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel_little_out_port: endpoint {
+ remote-endpoint =
+ <&etf_little_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_little_in_port0: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_little_in_port1: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel_little_in_port2: endpoint {
+ remote-endpoint = <&etm2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ funnel_little_in_port3: endpoint {
+ remote-endpoint = <&etm3_out>;
+ };
+ };
+ };
+ };
+
+ etf@12002000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x12002000 0 0x1000>;
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etf_little_out: endpoint {
+ remote-endpoint =
+ <&funnel_ca55_in_port0>;
+ };
+ };
+ };
+
+ in-port {
+ port {
+ etf_little_in: endpoint {
+ remote-endpoint =
+ <&funnel_little_out_port>;
+ };
+ };
+ };
+ };
+
+ etf@12003000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x12003000 0 0x1000>;
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etf_big_out: endpoint {
+ remote-endpoint =
+ <&funnel_ca55_in_port1>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ etf_big_in: endpoint {
+ remote-endpoint =
+ <&funnel_big_out_port>;
+ };
+ };
+ };
+ };
+
+ funnel@12004000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x12004000 0 0x1000>;
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel_ca55_out_port: endpoint {
+ remote-endpoint =
+ <&funnel_soc_in_port>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_ca55_in_port0: endpoint {
+ remote-endpoint =
+ <&etf_little_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_ca55_in_port1: endpoint {
+ remote-endpoint =
+ <&etf_big_out>;
+ };
+ };
+ };
+ };
+
+ funnel@12005000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x12005000 0 0x1000>;
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel_big_out_port: endpoint {
+ remote-endpoint =
+ <&etf_big_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_big_in_port0: endpoint {
+ remote-endpoint = <&etm4_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_big_in_port1: endpoint {
+ remote-endpoint = <&etm5_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel_big_in_port2: endpoint {
+ remote-endpoint = <&etm6_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ funnel_big_in_port3: endpoint {
+ remote-endpoint = <&etm7_out>;
+ };
+ };
+ };
+ };
+
+ etm@13040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x13040000 0 0x1000>;
+ cpu = <&CPU0>;
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint =
+ <&funnel_little_in_port0>;
+ };
+ };
+ };
+ };
+
+ etm@13140000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x13140000 0 0x1000>;
+ cpu = <&CPU1>;
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint =
+ <&funnel_little_in_port1>;
+ };
+ };
+ };
+ };
+
+ etm@13240000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x13240000 0 0x1000>;
+ cpu = <&CPU2>;
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint =
+ <&funnel_little_in_port2>;
+ };
+ };
+ };
+ };
+
+ etm@13340000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x13340000 0 0x1000>;
+ cpu = <&CPU3>;
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint =
+ <&funnel_little_in_port3>;
+ };
+ };
+ };
+ };
+
+ etm@13440000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x13440000 0 0x1000>;
+ cpu = <&CPU4>;
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint =
+ <&funnel_big_in_port0>;
+ };
+ };
+ };
+ };
+
+ etm@13540000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x13540000 0 0x1000>;
+ cpu = <&CPU5>;
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint =
+ <&funnel_big_in_port1>;
+ };
+ };
+ };
+ };
+
+ etm@13640000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x13640000 0 0x1000>;
+ cpu = <&CPU6>;
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint =
+ <&funnel_big_in_port2>;
+ };
+ };
+ };
+ };
+
+ etm@13740000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x13740000 0 0x1000>;
+ cpu = <&CPU7>;
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint =
+ <&funnel_big_in_port3>;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/sprd/sharkl3.dtsi b/arch/arm64/boot/dts/sprd/sharkl3.dtsi
new file mode 100644
index 000000000000..0222128b10f7
--- /dev/null
+++ b/arch/arm64/boot/dts/sprd/sharkl3.dtsi
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Unisoc Sharkl3 platform DTS file
+ *
+ * Copyright (C) 2019, Unisoc Inc.
+ */
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ apb@70000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x70000000 0x10000000>;
+
+ uart0: serial@0 {
+ compatible = "sprd,sc9863a-uart",
+ "sprd,sc9836-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ext_26m>;
+ status = "disabled";
+ };
+
+ uart1: serial@100000 {
+ compatible = "sprd,sc9863a-uart",
+ "sprd,sc9836-uart";
+ reg = <0x100000 0x100>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ext_26m>;
+ status = "disabled";
+ };
+
+ uart2: serial@200000 {
+ compatible = "sprd,sc9863a-uart",
+ "sprd,sc9836-uart";
+ reg = <0x200000 0x100>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ext_26m>;
+ status = "disabled";
+ };
+
+ uart3: serial@300000 {
+ compatible = "sprd,sc9863a-uart",
+ "sprd,sc9836-uart";
+ reg = <0x300000 0x100>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ext_26m>;
+ status = "disabled";
+ };
+
+ uart4: serial@400000 {
+ compatible = "sprd,sc9863a-uart",
+ "sprd,sc9836-uart";
+ reg = <0x400000 0x100>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ext_26m>;
+ status = "disabled";
+ };
+ };
+ };
+
+ ext_26m: ext-26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "ext-26m";
+ };
+};
diff --git a/arch/arm64/boot/dts/sprd/sp9863a-1h10.dts b/arch/arm64/boot/dts/sprd/sp9863a-1h10.dts
new file mode 100644
index 000000000000..5c32c1596337
--- /dev/null
+++ b/arch/arm64/boot/dts/sprd/sp9863a-1h10.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Unisoc SP9863A-1h10 boards DTS file
+ *
+ * Copyright (C) 2019, Unisoc Inc.
+ */
+
+/dts-v1/;
+
+#include "sc9863a.dtsi"
+
+/ {
+ model = "Spreadtrum SP9863A-1H10 Board";
+
+ compatible = "sprd,sp9863a-1h10", "sprd,sc9863a";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ bootargs = "earlycon";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
--
2.20.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-12-23 9:30 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-23 9:29 [PATCH v5 0/3] Add Unisoc's SC9863A support Chunyan Zhang
2019-12-23 9:29 ` [PATCH v5 1/3] dt-bindings: arm: sprd: add global registers bindings Chunyan Zhang
2019-12-23 9:29 ` [PATCH v5 2/3] dt-bindings: arm: move sprd board file to vendor directory Chunyan Zhang
2019-12-23 9:29 ` [PATCH v5 3/3] arm64: dts: Add Unisoc's SC9863A SoC support Chunyan Zhang
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