[RFC 00/11] ARM: Initial Sunplus Plus1 SP7021 and BPI-F2S support

[RFC 00/11] ARM: Initial Sunplus Plus1 SP7021 and BPI-F2S support

[Andreas Färber]

Hello,

This patch series adds initial drivers and Device Trees for Sunplus Plus1
series (codename Pentagram) SP7021 SoC and Banana Pi BPI-F2S SBC.

First, minimal Kconfig, DT and earlycon driver are prepared to get serial
output at all. Next, interrupt controller and full serial driver are added
that allow to boot into an initrd with interactive serial console.

Device Tree files added are for the CPU-Chip (aka A-Chip) with quad Cortex-A7,
but the file split prepares for also adding the Peripheral-Chip (B-Chip) with
ARM9 later. However, for now this is not reflected in the .dts filename; this
corresponds to the vf610- vs. vf610m4- naming scheme, whereas an alternative
would be to use sp7021-cchip- vs. -pchip- prefix (as sp7021-cpu- looks weird).
It is assumed we can reuse the same SoC and board bindings for CA7 and ARM9
and only differ for IP blocks where needed.

My inquiry to Sunplus about their GIC (anticipating complaints from Marc)
remained unanswered, so I've added the two extra regions and irq myself,
without being able to test KVM due to BSP U-Boot not booting in HYP mode.
According to Sunplus the mode can be changed in U-Boot (but where/how?).

Similarly, the architectural timer is not properly initialized in BSP U-Boot,
so that I currently have a mach- hack in my tree below. Unlike RTD1195,
we do have U-Boot sources (v2019.04 based), so should be able to fix this
in the bootloader rather than in the kernel, thus not included as patch here.

Based on SoC online manual [1] and downstream BPI-F2S BSP tree [2] as well as
my previous Actions serial and Realtek irqchip drivers and DTs.

More details at:
https://en.opensuse.org/HCL:BananaPi_F2S

Latest experimental patches at:
https://github.com/afaerber/linux/commits/f2s-next

Have a lot of fun!

Cheers,
Andreas

[1] https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/pages/470450252/SP7021+Technical+Manual
[2] https://github.com/BPI-SINOVOIP/BPI-F2S-bsp

Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-serial@vger.kernel.org
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Wells Lu 呂芳騰 <wells.lu@sunplus.com>
Cc: Dvorkin Dmitry <dvorkin@tibbo.com>

Andreas Färber (11):
  dt-bindings: vendor-prefixes: Add Sunplus
  dt-bindings: arm: Add Sunplus SP7021 and Banana Pi BPI-F2S
  ARM: Prepare Sunplus Plus1 SoC family
  dt-bindings: interrupt-controller: Add Sunplus SP7021 mux
  dt-bindings: serial: Add Sunplus SP7021 UART
  tty: serial: Add Sunplus Plus1 UART earlycon
  ARM: dts: Add Sunplus Plus1 SP7021 and Banana Pi F2S
  tty: serial: sunplus: Implement full UART driver
  irqchip: Add Sunplus SP7021 interrupt (mux) controller
  ARM: dts: sp7021-cpu: Add interrupt controller node
  ARM: dts: sp7021-cpu: Add dummy UART0 clock and interrupt

 Documentation/devicetree/bindings/arm/sunplus.yaml |  22 +
 .../sunplus,pentagram-intc.yaml                    |  50 ++
 .../bindings/serial/sunplus,pentagram-uart.yaml    |  24 +
 .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
 arch/arm/Kconfig                                   |   2 +
 arch/arm/Makefile                                  |   1 +
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/pentagram-sp7021-bpi-f2s.dts     |  29 +
 arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi        |  93 +++
 arch/arm/boot/dts/pentagram-sp7021.dtsi            |  61 ++
 arch/arm/mach-sunplus/Kconfig                      |  10 +
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-sp7021.c                       | 285 ++++++++
 drivers/tty/serial/Kconfig                         |  19 +
 drivers/tty/serial/Makefile                        |   1 +
 drivers/tty/serial/sunplus-uart.c                  | 770 +++++++++++++++++++++
 include/uapi/linux/serial_core.h                   |   3 +
 17 files changed, 1375 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/sunplus.yaml
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,pentagram-intc.yaml
 create mode 100644 Documentation/devicetree/bindings/serial/sunplus,pentagram-uart.yaml
 create mode 100644 arch/arm/boot/dts/pentagram-sp7021-bpi-f2s.dts
 create mode 100644 arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi
 create mode 100644 arch/arm/boot/dts/pentagram-sp7021.dtsi
 create mode 100644 arch/arm/mach-sunplus/Kconfig
 create mode 100644 drivers/irqchip/irq-sp7021.c
 create mode 100644 drivers/tty/serial/sunplus-uart.c

-- 
2.16.4

[RFC 01/11] dt-bindings: vendor-prefixes: Add Sunplus

[Andreas Färber]

Sunplus Technology Co., Ltd. is a Taiwanese IC vendor.
Assign vendor prefix "sunplus".

Cc: Wells Lu 呂芳騰 <wells.lu@sunplus.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 6e09fc7362d5..2c764b0941b4 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -955,6 +955,8 @@ patternProperties:
     description: Summit microelectronics
   "^sunchip,.*":
     description: Shenzhen Sunchip Technology Co., Ltd
+  "^sunplus,.*":
+    description: Sunplus Technology Co., Ltd.
   "^SUNW,.*":
     description: Sun Microsystems, Inc
   "^swir,.*":
-- 
2.16.4

[RFC 02/11] dt-bindings: arm: Add Sunplus SP7021 and Banana Pi BPI-F2S

[Andreas Färber]

Cc: Wells Lu 呂芳騰 <wells.lu@sunplus.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 Documentation/devicetree/bindings/arm/sunplus.yaml | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/sunplus.yaml

diff --git a/Documentation/devicetree/bindings/arm/sunplus.yaml b/Documentation/devicetree/bindings/arm/sunplus.yaml
new file mode 100644
index 000000000000..c88856a00983
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/sunplus.yaml
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/sunplus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sunplus platforms device tree bindings
+
+maintainers:
+  - Andreas Färber <afaerber@suse.de>
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      # SP7021 SoC based boards
+      - items:
+          - enum:
+              - bananapi,bpi-f2s # Banana Pi BPI-F2S
+          - const: sunplus,sp7021
+...
-- 
2.16.4

[RFC 04/11] dt-bindings: interrupt-controller: Add Sunplus SP7021 mux

[Andreas Färber]

The Sunplus SP7021 SoC has an interrupt mux.

Cc: Wells Lu 呂芳騰 <wells.lu@sunplus.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 .../sunplus,pentagram-intc.yaml                    | 50 ++++++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,pentagram-intc.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sunplus,pentagram-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/sunplus,pentagram-intc.yaml
new file mode 100644
index 000000000000..baaf7bcd4a71
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/sunplus,pentagram-intc.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/sunplus,pentagram-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sunplus Pentagram SoC Interrupt Controller
+
+maintainers:
+  - Andreas Färber <afaerber@suse.de>
+
+allOf:
+  - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+  compatible:
+    const: sunplus,sp7021-intc
+
+  reg:
+    maxItems: 2
+
+  interrupts:
+    maxItems: 2
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 2
+
+required:
+  - compatible
+  - reg
+  - interrupt-controller
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    interrupt-controller@9c000780 {
+        compatible = "sunplus,sp7021-intc";
+        reg = <0x9c000780 0x80>,
+              <0x9c000a80 0x80>;
+        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+    };
+...
-- 
2.16.4

[RFC 05/11] dt-bindings: serial: Add Sunplus SP7021 UART

[Andreas Färber]

The Sunplus Plus1 (aka Pentagram) SP7021 SoC has five UARTs.

Cc: Wells Lu 呂芳騰 <wells.lu@sunplus.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 .../bindings/serial/sunplus,pentagram-uart.yaml    | 24 ++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/serial/sunplus,pentagram-uart.yaml

diff --git a/Documentation/devicetree/bindings/serial/sunplus,pentagram-uart.yaml b/Documentation/devicetree/bindings/serial/sunplus,pentagram-uart.yaml
new file mode 100644
index 000000000000..9d1641232a4c
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/sunplus,pentagram-uart.yaml
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/sunplus,pentagram-uart.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sunplus Pentagram SoC UART Serial Interface
+
+maintainers:
+  - Andreas Färber <afaerber@suse.de>
+
+properties:
+  compatible:
+    const: sunplus,sp7021-uart
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+...
-- 
2.16.4

[RFC 07/11] ARM: dts: Add Sunplus Plus1 SP7021 and Banana Pi F2S

[Andreas Färber]

Prepare Device Trees for Sunplus Plus1 (aka Pentagram) SP7021's
CPU-Chip aka A-Chip (Cortex-A7) as well as the Banana Pi BPI-F2S SBC.

Cc: Wells Lu 呂芳騰 <wells.lu@sunplus.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 arch/arm/boot/dts/Makefile                     |  2 +
 arch/arm/boot/dts/pentagram-sp7021-bpi-f2s.dts | 22 ++++++++
 arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi    | 75 ++++++++++++++++++++++++++
 arch/arm/boot/dts/pentagram-sp7021.dtsi        | 61 +++++++++++++++++++++
 4 files changed, 160 insertions(+)
 create mode 100644 arch/arm/boot/dts/pentagram-sp7021-bpi-f2s.dts
 create mode 100644 arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi
 create mode 100644 arch/arm/boot/dts/pentagram-sp7021.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 566c6d1cfc46..b514ead139f3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -846,6 +846,8 @@ dtb-$(CONFIG_ARCH_ACTIONS) += \
 	owl-s500-cubieboard6.dtb \
 	owl-s500-guitar-bb-rev-b.dtb \
 	owl-s500-sparky.dtb
+dtb-$(CONFIG_ARCH_SUNPLUS) += \
+	pentagram-sp7021-bpi-f2s.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += \
 	prima2-evb.dtb
 dtb-$(CONFIG_ARCH_PXA) += \
diff --git a/arch/arm/boot/dts/pentagram-sp7021-bpi-f2s.dts b/arch/arm/boot/dts/pentagram-sp7021-bpi-f2s.dts
new file mode 100644
index 000000000000..3c25b6e79fe2
--- /dev/null
+++ b/arch/arm/boot/dts/pentagram-sp7021-bpi-f2s.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
+
+/dts-v1/;
+
+#include "pentagram-sp7021-cpu.dtsi"
+
+/ {
+	compatible = "bananapi,bpi-f2s", "sunplus,sp7021";
+	model = "Banana Pi BPI-F2S";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi b/arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi
new file mode 100644
index 000000000000..ae58bf5ffadf
--- /dev/null
+++ b/arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
+/*
+ * SunPlus Plus1 (Pentagram) SP7021 CPU-Chip a.k.a. A-Chip (CA7)
+ *
+ * Copyright (c) 2020 Andreas Färber
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "pentagram-sp7021.dtsi"
+
+/ {
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0>;
+		};
+
+		cpu1: cpu@1{
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <1>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <2>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <3>;
+		};
+	};
+
+	arm-pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	timer: timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <27000000>;
+		arm,cpu-registers-not-fw-configured;
+	};
+
+	soc {
+		gic: interrupt-controller@9f101000 {
+			compatible = "arm,cortex-a7-gic";
+			reg = <0x9f101000 0x1000>,
+			      <0x9f102000 0x2000>,
+			      <0x9f104000 0x2000>,
+			      <0x9f106000 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/pentagram-sp7021.dtsi b/arch/arm/boot/dts/pentagram-sp7021.dtsi
new file mode 100644
index 000000000000..7dd44901cf4a
--- /dev/null
+++ b/arch/arm/boot/dts/pentagram-sp7021.dtsi
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
+/*
+ * Copyright (c) 2020 Andreas Färber
+ */
+
+/ {
+	compatible = "sunplus,sp7021";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x20000000 0x20000000 0xe0000000>;
+
+		rgst: bus@9c000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x9c000000 0x00100000>;
+
+			uart2: serial@800 {
+				compatible = "sunplus,sp7021-uart";
+				reg = <0x800 0x80>;
+				status = "disabled";
+			};
+
+			uart3: serial@880 {
+				compatible = "sunplus,sp7021-uart";
+				reg = <0x880 0x80>;
+				status = "disabled";
+			};
+
+			uart0: serial@900 {
+				compatible = "sunplus,sp7021-uart";
+				reg = <0x900 0x80>;
+				status = "disabled";
+			};
+
+			uart1: serial@980 {
+				compatible = "sunplus,sp7021-uart";
+				reg = <0x980 0x80>;
+				status = "disabled";
+			};
+
+			uart4: serial@8780 {
+				compatible = "sunplus,sp7021-uart";
+				reg = <0x8780 0x80>;
+				status = "disabled";
+			};
+		};
+
+		amba: bus@9c100000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x9c100000 0x01ef0000>;
+		};
+	};
+};
-- 
2.16.4

[RFC 10/11] ARM: dts: sp7021-cpu: Add interrupt controller node

[Andreas Färber]

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi b/arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi
index ae58bf5ffadf..7e424baa9214 100644
--- a/arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi
+++ b/arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi
@@ -73,3 +73,16 @@
 		};
 	};
 };
+
+&rgst {
+	intc: interrupt-controller@780 {
+		compatible = "sunplus,sp7021-intc";
+		reg = <0x780 0x80>, /* G15 */
+		      <0xa80 0x80>; /* G21 */
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
-- 
2.16.4

[RFC 11/11] ARM: dts: sp7021-cpu: Add dummy UART0 clock and interrupt

[Andreas Färber]

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 arch/arm/boot/dts/pentagram-sp7021-bpi-f2s.dts | 7 +++++++
 arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi    | 5 +++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/pentagram-sp7021-bpi-f2s.dts b/arch/arm/boot/dts/pentagram-sp7021-bpi-f2s.dts
index 3c25b6e79fe2..455416ce9d82 100644
--- a/arch/arm/boot/dts/pentagram-sp7021-bpi-f2s.dts
+++ b/arch/arm/boot/dts/pentagram-sp7021-bpi-f2s.dts
@@ -15,8 +15,15 @@
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	uart0_clk: clk {
+		compatible = "fixed-clock";
+		clock-frequency = <27000000>;
+		#clock-cells = <0>;
+	};
 };
 
 &uart0 {
 	status = "okay";
+	clocks = <&uart0_clk>;
 };
diff --git a/arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi b/arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi
index 7e424baa9214..48c5986a31ed 100644
--- a/arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi
+++ b/arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi
@@ -86,3 +86,8 @@
 		#interrupt-cells = <2>;
 	};
 };
+
+&uart0 {
+	interrupt-parent = <&intc>;
+	interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+};
-- 
2.16.4

RE: [RFC 00/11] ARM: Initial Sunplus Plus1 SP7021 and BPI-F2S support

[Wells Lu 呂芳騰]

Added Jie Zhang and Jian Qin in to cc list.

Jie Zhang is software leader of Sunplus Plus 1 (SP7021) platform.


-----Original Message-----
From: Andreas Färber <afaerber@suse.de> 
Sent: Monday, March 09, 2020 12:32 AM
To: linux-arm-kernel@lists.infradead.org
Cc: Wells Lu 呂芳騰 <wells.lu@sunplus.com>; Dvorkin Dmitry <dvorkin@tibbo.com>; linux-kernel@vger.kernel.org; Andreas Färber <afaerber@suse.de>; devicetree@vger.kernel.org; Rob Herring <robh+dt@kernel.org>; Greg Kroah-Hartman <gregkh@linuxfoundation.org>; linux-serial@vger.kernel.org; Thomas Gleixner <tglx@linutronix.de>; Jason Cooper <jason@lakedaemon.net>; Marc Zyngier <maz@kernel.org>
Subject: [RFC 00/11] ARM: Initial Sunplus Plus1 SP7021 and BPI-F2S support

Hello,

This patch series adds initial drivers and Device Trees for Sunplus Plus1 series (codename Pentagram) SP7021 SoC and Banana Pi BPI-F2S SBC.

First, minimal Kconfig, DT and earlycon driver are prepared to get serial output at all. Next, interrupt controller and full serial driver are added that allow to boot into an initrd with interactive serial console.

Device Tree files added are for the CPU-Chip (aka A-Chip) with quad Cortex-A7, but the file split prepares for also adding the Peripheral-Chip (B-Chip) with
ARM9 later. However, for now this is not reflected in the .dts filename; this corresponds to the vf610- vs. vf610m4- naming scheme, whereas an alternative would be to use sp7021-cchip- vs. -pchip- prefix (as sp7021-cpu- looks weird).
It is assumed we can reuse the same SoC and board bindings for CA7 and ARM9 and only differ for IP blocks where needed.

My inquiry to Sunplus about their GIC (anticipating complaints from Marc) remained unanswered, so I've added the two extra regions and irq myself, without being able to test KVM due to BSP U-Boot not booting in HYP mode.
According to Sunplus the mode can be changed in U-Boot (but where/how?).

Similarly, the architectural timer is not properly initialized in BSP U-Boot, so that I currently have a mach- hack in my tree below. Unlike RTD1195, we do have U-Boot sources (v2019.04 based), so should be able to fix this in the bootloader rather than in the kernel, thus not included as patch here.

Based on SoC online manual [1] and downstream BPI-F2S BSP tree [2] as well as my previous Actions serial and Realtek irqchip drivers and DTs.

More details at:
https://en.opensuse.org/HCL:BananaPi_F2S

Latest experimental patches at:
https://github.com/afaerber/linux/commits/f2s-next

Have a lot of fun!

Cheers,
Andreas

[1] https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/pages/470450252/SP7021+Technical+Manual
[2] https://github.com/BPI-SINOVOIP/BPI-F2S-bsp

Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-serial@vger.kernel.org
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Wells Lu 呂芳騰 <wells.lu@sunplus.com>
Cc: Dvorkin Dmitry <dvorkin@tibbo.com>

Andreas Färber (11):
  dt-bindings: vendor-prefixes: Add Sunplus
  dt-bindings: arm: Add Sunplus SP7021 and Banana Pi BPI-F2S
  ARM: Prepare Sunplus Plus1 SoC family
  dt-bindings: interrupt-controller: Add Sunplus SP7021 mux
  dt-bindings: serial: Add Sunplus SP7021 UART
  tty: serial: Add Sunplus Plus1 UART earlycon
  ARM: dts: Add Sunplus Plus1 SP7021 and Banana Pi F2S
  tty: serial: sunplus: Implement full UART driver
  irqchip: Add Sunplus SP7021 interrupt (mux) controller
  ARM: dts: sp7021-cpu: Add interrupt controller node
  ARM: dts: sp7021-cpu: Add dummy UART0 clock and interrupt

 Documentation/devicetree/bindings/arm/sunplus.yaml |  22 +
 .../sunplus,pentagram-intc.yaml                    |  50 ++
 .../bindings/serial/sunplus,pentagram-uart.yaml    |  24 +
 .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
 arch/arm/Kconfig                                   |   2 +
 arch/arm/Makefile                                  |   1 +
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/pentagram-sp7021-bpi-f2s.dts     |  29 +
 arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi        |  93 +++
 arch/arm/boot/dts/pentagram-sp7021.dtsi            |  61 ++
 arch/arm/mach-sunplus/Kconfig                      |  10 +
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-sp7021.c                       | 285 ++++++++
 drivers/tty/serial/Kconfig                         |  19 +
 drivers/tty/serial/Makefile                        |   1 +
 drivers/tty/serial/sunplus-uart.c                  | 770 +++++++++++++++++++++
 include/uapi/linux/serial_core.h                   |   3 +
 17 files changed, 1375 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/sunplus.yaml
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,pentagram-intc.yaml
 create mode 100644 Documentation/devicetree/bindings/serial/sunplus,pentagram-uart.yaml
 create mode 100644 arch/arm/boot/dts/pentagram-sp7021-bpi-f2s.dts
 create mode 100644 arch/arm/boot/dts/pentagram-sp7021-cpu.dtsi
 create mode 100644 arch/arm/boot/dts/pentagram-sp7021.dtsi
 create mode 100644 arch/arm/mach-sunplus/Kconfig  create mode 100644 drivers/irqchip/irq-sp7021.c  create mode 100644 drivers/tty/serial/sunplus-uart.c

--
2.16.4

Re: [RFC 04/11] dt-bindings: interrupt-controller: Add Sunplus SP7021 mux

[Rob Herring]

On Sun, Mar 08, 2020 at 05:32:22PM +0100, Andreas Färber wrote:
> The Sunplus SP7021 SoC has an interrupt mux.
> 
> Cc: Wells Lu 呂芳騰 <wells.lu@sunplus.com>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  .../sunplus,pentagram-intc.yaml                    | 50 ++++++++++++++++++++++
>  1 file changed, 50 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,pentagram-intc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sunplus,pentagram-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/sunplus,pentagram-intc.yaml
> new file mode 100644
> index 000000000000..baaf7bcd4a71
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sunplus,pentagram-intc.yaml
> @@ -0,0 +1,50 @@
> +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/sunplus,pentagram-intc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Sunplus Pentagram SoC Interrupt Controller
> +
> +maintainers:
> +  - Andreas Färber <afaerber@suse.de>
> +
> +allOf:
> +  - $ref: /schemas/interrupt-controller.yaml#

No need for this. It's applied based on the node name.

> +
> +properties:
> +  compatible:
> +    const: sunplus,sp7021-intc
> +
> +  reg:
> +    maxItems: 2

Need to define what each one is.

> +
> +  interrupts:
> +    maxItems: 2

Same here.

> +
> +  interrupt-controller: true
> +
> +  "#interrupt-cells":
> +    const: 2
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupt-controller
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    interrupt-controller@9c000780 {
> +        compatible = "sunplus,sp7021-intc";
> +        reg = <0x9c000780 0x80>,
> +              <0x9c000a80 0x80>;
> +        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> +        interrupt-controller;
> +        #interrupt-cells = <2>;
> +    };
> +...
> -- 
> 2.16.4
> 

Re: [RFC 05/11] dt-bindings: serial: Add Sunplus SP7021 UART

[Rob Herring]

On Sun, Mar 08, 2020 at 05:32:23PM +0100, Andreas Färber wrote:
> The Sunplus Plus1 (aka Pentagram) SP7021 SoC has five UARTs.
> 
> Cc: Wells Lu 呂芳騰 <wells.lu@sunplus.com>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  .../bindings/serial/sunplus,pentagram-uart.yaml    | 24 ++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/serial/sunplus,pentagram-uart.yaml
> 
> diff --git a/Documentation/devicetree/bindings/serial/sunplus,pentagram-uart.yaml b/Documentation/devicetree/bindings/serial/sunplus,pentagram-uart.yaml
> new file mode 100644
> index 000000000000..9d1641232a4c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/sunplus,pentagram-uart.yaml
> @@ -0,0 +1,24 @@
> +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/serial/sunplus,pentagram-uart.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Sunplus Pentagram SoC UART Serial Interface
> +
> +maintainers:
> +  - Andreas Färber <afaerber@suse.de>
> +

Soon this will need to reference serial.yaml which is getting added to 
5.7.

> +properties:
> +  compatible:
> +    const: sunplus,sp7021-uart
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +...
> -- 
> 2.16.4
>