[PATCH v3 0/4] PCI: brcmstb: Some minor fixes/features

[PATCH v3 0/4] PCI: brcmstb: Some minor fixes/features

[Jim Quinlan]

v3 -- A change was submitted to [1] to make 'aspm-no-l0s' a general
      property for PCIe devices.  As such, the STB PCIe YAML  file
      merely notes that it may be used.

v2 -- Dropped commit concerning CRS.
   -- Chanded new prop 'brcm,aspm-en-l0s' to 'aspm-no-l0s'.
   -- Capitalize first letter in commit subject line; spelling.

v1 -- original

[1] https://github.com/devicetree-org/dt-schema/blob/master/schemas/pci/pci-bus.yaml

Jim Quinlan (4):
  PCI: brcmstb: Don't clk_put() a managed clock
  PCI: brcmstb: Fix window register offset from 4 to 8
  dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s'
  PCI: brcmstb: Disable L0s component of ASPM if requested

 .../bindings/pci/brcm,stb-pcie.yaml           |  2 ++
 drivers/pci/controller/pcie-brcmstb.c         | 19 +++++++++++++++----
 2 files changed, 17 insertions(+), 4 deletions(-)

-- 
2.17.1

[PATCH v3 3/4] dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s'

[Jim Quinlan]

From: Jim Quinlan <jquinlan@broadcom.com>

For various reasons, one may want to disable the ASPM L0s
capability.

Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
---
 Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
index 77d3e81a437b..8680a0f86c5a 100644
--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -56,6 +56,8 @@ properties:
     description: Indicates usage of spread-spectrum clocking.
     type: boolean
 
+  aspm-no-l0s: true
+
 required:
   - reg
   - dma-ranges
-- 
2.17.1

Re: [PATCH v3 3/4] dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s'

[Rob Herring]

On Thu, May 7, 2020 at 3:16 PM Jim Quinlan <james.quinlan@broadcom.com> wrote:
>
> From: Jim Quinlan <jquinlan@broadcom.com>
>
> For various reasons, one may want to disable the ASPM L0s
> capability.
>
> Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
> ---
>  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 2 ++
>  1 file changed, 2 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v3 0/4] PCI: brcmstb: Some minor fixes/features

[Lorenzo Pieralisi]

On Thu, May 07, 2020 at 04:15:39PM -0400, Jim Quinlan wrote:
> v3 -- A change was submitted to [1] to make 'aspm-no-l0s' a general
>       property for PCIe devices.  As such, the STB PCIe YAML  file
>       merely notes that it may be used.
> 
> v2 -- Dropped commit concerning CRS.
>    -- Chanded new prop 'brcm,aspm-en-l0s' to 'aspm-no-l0s'.
>    -- Capitalize first letter in commit subject line; spelling.
> 
> v1 -- original
> 
> [1] https://github.com/devicetree-org/dt-schema/blob/master/schemas/pci/pci-bus.yaml
> 
> Jim Quinlan (4):
>   PCI: brcmstb: Don't clk_put() a managed clock
>   PCI: brcmstb: Fix window register offset from 4 to 8
>   dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s'
>   PCI: brcmstb: Disable L0s component of ASPM if requested
> 
>  .../bindings/pci/brcm,stb-pcie.yaml           |  2 ++
>  drivers/pci/controller/pcie-brcmstb.c         | 19 +++++++++++++++----
>  2 files changed, 17 insertions(+), 4 deletions(-)

Applied to pci/brcmstb, thanks !

Lorenzo