* [PATCH v3 00/14] Enable GPU for SM8150 and SM8250
@ 2020-07-09 13:52 Jonathan Marek
2020-07-09 13:52 ` [PATCH v3 06/14] dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc Jonathan Marek
` (6 more replies)
0 siblings, 7 replies; 16+ messages in thread
From: Jonathan Marek @ 2020-07-09 13:52 UTC (permalink / raw)
To: linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Deepak Katragadda,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:COMMON CLK FRAMEWORK, open list, Michael Turquette,
Rob Herring, Stephen Boyd, Taniya Das, Vinod Koul
This series adds the missing clock drivers and dts nodes to enable
the GPU on both SM8150 and SM8250.
Note an extra drm/msm patch [1] is required for SM8250.
As noted by Dmitry, GMU init fails with newer firmware, needs this patch [2].
[1] https://patchwork.freedesktop.org/series/78968/
[2] https://git.linaro.org/landing-teams/working/qualcomm/kernel.git/commit/?h=tracking-qcomlt-sm8250&id=01331f2ccbe7e6c4719dbe038a5fb496db32646d
Changes in V2:
* Added "clk: qcom: gcc: fix sm8150 GPU and NPU clocks" to fix the newly added
SM8150 GPU gcc clocks
* Added "Fixes:" tag to "clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL"
* Added yaml schemas to gpucc dt-bindings patches
* Added "clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers" and changed
gpucc patches to use it.
* Removed CLK_IS_CRITICAL from gpu_cc_ahb_clk
* Added missing rpmh regulator level for sm8250 GPU clock levels
* Use sm8150/sm8250 iommu compatibles in dts
* Add gcc_gpu_gpll0_clk_src/gcc_gpu_gpll0_div_clk_src to gpucc clocks in dts
Changes in V3:
* Combined gpucc yaml bindings into one
* Removed some unused clocks from gpucc drivers to move closely match other gpucc
* Use parent_data instead of parent_names
Jonathan Marek (14):
clk: qcom: gcc: fix sm8150 GPU and NPU clocks
clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL
clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid
clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pll
clk: qcom: gcc: remove unnecessary vco_table from SM8150
dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc
dt-bindings: clock: add SM8150 QCOM Graphics clock bindings
dt-bindings: clock: add SM8250 QCOM Graphics clock bindings
clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers
clk: qcom: Add graphics clock controller driver for SM8150
clk: qcom: Add graphics clock controller driver for SM8250
dt-bindings: power: Add missing rpmpd rpmh regulator level
arm64: dts: qcom: add sm8150 GPU nodes
arm64: dts: qcom: add sm8250 GPU nodes
...qcom,sdm845-gpucc.yaml => qcom,gpucc.yaml} | 18 +-
.../bindings/clock/qcom,sc7180-gpucc.yaml | 74 ----
arch/arm64/boot/dts/qcom/sm8150.dtsi | 136 +++++++
arch/arm64/boot/dts/qcom/sm8250.dtsi | 143 +++++++
drivers/clk/qcom/Kconfig | 16 +
drivers/clk/qcom/Makefile | 2 +
drivers/clk/qcom/clk-alpha-pll.c | 70 ++--
drivers/clk/qcom/clk-alpha-pll.h | 15 +-
drivers/clk/qcom/gcc-sm8150.c | 26 +-
drivers/clk/qcom/gdsc.c | 25 ++
drivers/clk/qcom/gdsc.h | 1 +
drivers/clk/qcom/gpucc-sc7180.c | 27 +-
drivers/clk/qcom/gpucc-sdm845.c | 27 +-
drivers/clk/qcom/gpucc-sm8150.c | 320 ++++++++++++++++
drivers/clk/qcom/gpucc-sm8250.c | 348 ++++++++++++++++++
include/dt-bindings/clock/qcom,gpucc-sm8150.h | 33 ++
include/dt-bindings/clock/qcom,gpucc-sm8250.h | 34 ++
include/dt-bindings/power/qcom-rpmpd.h | 1 +
18 files changed, 1128 insertions(+), 188 deletions(-)
rename Documentation/devicetree/bindings/clock/{qcom,sdm845-gpucc.yaml => qcom,gpucc.yaml} (75%)
delete mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml
create mode 100644 drivers/clk/qcom/gpucc-sm8150.c
create mode 100644 drivers/clk/qcom/gpucc-sm8250.c
create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8150.h
create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8250.h
--
2.26.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 06/14] dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc
2020-07-09 13:52 [PATCH v3 00/14] Enable GPU for SM8150 and SM8250 Jonathan Marek
@ 2020-07-09 13:52 ` Jonathan Marek
2020-07-13 23:06 ` Rob Herring
2020-07-24 8:52 ` Stephen Boyd
2020-07-09 13:52 ` [PATCH v3 07/14] dt-bindings: clock: add SM8150 QCOM Graphics clock bindings Jonathan Marek
` (5 subsequent siblings)
6 siblings, 2 replies; 16+ messages in thread
From: Jonathan Marek @ 2020-07-09 13:52 UTC (permalink / raw)
To: linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Taniya Das, open list:COMMON CLK FRAMEWORK,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
These two bindings are almost identical, so combine them into one. This
will make it easier to add the sm8150 and sm8250 gpucc bindings.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
...qcom,sdm845-gpucc.yaml => qcom,gpucc.yaml} | 14 ++--
.../bindings/clock/qcom,sc7180-gpucc.yaml | 74 -------------------
2 files changed, 9 insertions(+), 79 deletions(-)
rename Documentation/devicetree/bindings/clock/{qcom,sdm845-gpucc.yaml => qcom,gpucc.yaml} (82%)
delete mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml
diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
similarity index 82%
rename from Documentation/devicetree/bindings/clock/qcom,sdm845-gpucc.yaml
rename to Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
index 8a0c576ba8b3..aab6bef79771 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sdm845-gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
@@ -1,23 +1,27 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
-$id: http://devicetree.org/schemas/clock/qcom,sdm845-gpucc.yaml#
+$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Graphics Clock & Reset Controller Binding for SDM845
+title: Qualcomm Graphics Clock & Reset Controller Binding
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm graphics clock control module which supports the clocks, resets and
- power domains on SDM845.
+ power domains on SDM845/SC7180.
- See also dt-bindings/clock/qcom,gpucc-sdm845.h.
+ See also:
+ dt-bindings/clock/qcom,gpucc-sdm845.h
+ dt-bindings/clock/qcom,gpucc-sc7180.h
properties:
compatible:
- const: qcom,sdm845-gpucc
+ enum:
+ - qcom,sdm845-gpucc
+ - qcom,sc7180-gpucc
clocks:
items:
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml
deleted file mode 100644
index fe08461fce05..000000000000
--- a/Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml
+++ /dev/null
@@ -1,74 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/qcom,sc7180-gpucc.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Graphics Clock & Reset Controller Binding for SC7180
-
-maintainers:
- - Taniya Das <tdas@codeaurora.org>
-
-description: |
- Qualcomm graphics clock control module which supports the clocks, resets and
- power domains on SC7180.
-
- See also dt-bindings/clock/qcom,gpucc-sc7180.h.
-
-properties:
- compatible:
- const: qcom,sc7180-gpucc
-
- clocks:
- items:
- - description: Board XO source
- - description: GPLL0 main branch source
- - description: GPLL0 div branch source
-
- clock-names:
- items:
- - const: bi_tcxo
- - const: gcc_gpu_gpll0_clk_src
- - const: gcc_gpu_gpll0_div_clk_src
-
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/clock/qcom,gcc-sc7180.h>
- #include <dt-bindings/clock/qcom,rpmh.h>
- clock-controller@5090000 {
- compatible = "qcom,sc7180-gpucc";
- reg = <0x05090000 0x9000>;
- clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_GPU_GPLL0_CLK_SRC>,
- <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
- clock-names = "bi_tcxo",
- "gcc_gpu_gpll0_clk_src",
- "gcc_gpu_gpll0_div_clk_src";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
-...
--
2.26.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 07/14] dt-bindings: clock: add SM8150 QCOM Graphics clock bindings
2020-07-09 13:52 [PATCH v3 00/14] Enable GPU for SM8150 and SM8250 Jonathan Marek
2020-07-09 13:52 ` [PATCH v3 06/14] dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc Jonathan Marek
@ 2020-07-09 13:52 ` Jonathan Marek
2020-07-13 23:06 ` Rob Herring
2020-07-24 8:52 ` Stephen Boyd
2020-07-09 13:52 ` [PATCH v3 08/14] dt-bindings: clock: add SM8250 " Jonathan Marek
` (4 subsequent siblings)
6 siblings, 2 replies; 16+ messages in thread
From: Jonathan Marek @ 2020-07-09 13:52 UTC (permalink / raw)
To: linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Taniya Das, open list:COMMON CLK FRAMEWORK,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SM8150 SoCs.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
.../devicetree/bindings/clock/qcom,gpucc.yaml | 4 ++-
include/dt-bindings/clock/qcom,gpucc-sm8150.h | 33 +++++++++++++++++++
2 files changed, 36 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8150.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
index aab6bef79771..3e064ed0e0ea 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
@@ -11,17 +11,19 @@ maintainers:
description: |
Qualcomm graphics clock control module which supports the clocks, resets and
- power domains on SDM845/SC7180.
+ power domains on SDM845/SC7180/SM8150.
See also:
dt-bindings/clock/qcom,gpucc-sdm845.h
dt-bindings/clock/qcom,gpucc-sc7180.h
+ dt-bindings/clock/qcom,gpucc-sm8150.h
properties:
compatible:
enum:
- qcom,sdm845-gpucc
- qcom,sc7180-gpucc
+ - qcom,sm8150-gpucc
clocks:
items:
diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8150.h b/include/dt-bindings/clock/qcom,gpucc-sm8150.h
new file mode 100644
index 000000000000..c5b70aad7770
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gpucc-sm8150.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H
+
+/* GPU_CC clock registers */
+#define GPU_CC_AHB_CLK 0
+#define GPU_CC_CRC_AHB_CLK 1
+#define GPU_CC_CX_APB_CLK 2
+#define GPU_CC_CX_GMU_CLK 3
+#define GPU_CC_CX_SNOC_DVM_CLK 4
+#define GPU_CC_CXO_AON_CLK 5
+#define GPU_CC_CXO_CLK 6
+#define GPU_CC_GMU_CLK_SRC 7
+#define GPU_CC_GX_GMU_CLK 8
+#define GPU_CC_PLL1 9
+
+/* GPU_CC Resets */
+#define GPUCC_GPU_CC_CX_BCR 0
+#define GPUCC_GPU_CC_GFX3D_AON_BCR 1
+#define GPUCC_GPU_CC_GMU_BCR 2
+#define GPUCC_GPU_CC_GX_BCR 3
+#define GPUCC_GPU_CC_SPDM_BCR 4
+#define GPUCC_GPU_CC_XO_BCR 5
+
+/* GPU_CC GDSCRs */
+#define GPU_CX_GDSC 0
+#define GPU_GX_GDSC 1
+
+#endif
--
2.26.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 08/14] dt-bindings: clock: add SM8250 QCOM Graphics clock bindings
2020-07-09 13:52 [PATCH v3 00/14] Enable GPU for SM8150 and SM8250 Jonathan Marek
2020-07-09 13:52 ` [PATCH v3 06/14] dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc Jonathan Marek
2020-07-09 13:52 ` [PATCH v3 07/14] dt-bindings: clock: add SM8150 QCOM Graphics clock bindings Jonathan Marek
@ 2020-07-09 13:52 ` Jonathan Marek
2020-07-13 23:06 ` Rob Herring
2020-07-24 8:52 ` Stephen Boyd
2020-07-09 13:52 ` [PATCH v3 12/14] dt-bindings: power: Add missing rpmpd rpmh regulator level Jonathan Marek
` (3 subsequent siblings)
6 siblings, 2 replies; 16+ messages in thread
From: Jonathan Marek @ 2020-07-09 13:52 UTC (permalink / raw)
To: linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Taniya Das, open list:COMMON CLK FRAMEWORK,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SM8250 SoCs.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
.../devicetree/bindings/clock/qcom,gpucc.yaml | 4 ++-
include/dt-bindings/clock/qcom,gpucc-sm8250.h | 34 +++++++++++++++++++
2 files changed, 37 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8250.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
index 3e064ed0e0ea..df943c4c3234 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
@@ -11,12 +11,13 @@ maintainers:
description: |
Qualcomm graphics clock control module which supports the clocks, resets and
- power domains on SDM845/SC7180/SM8150.
+ power domains on SDM845/SC7180/SM8150/SM8250.
See also:
dt-bindings/clock/qcom,gpucc-sdm845.h
dt-bindings/clock/qcom,gpucc-sc7180.h
dt-bindings/clock/qcom,gpucc-sm8150.h
+ dt-bindings/clock/qcom,gpucc-sm8250.h
properties:
compatible:
@@ -24,6 +25,7 @@ properties:
- qcom,sdm845-gpucc
- qcom,sc7180-gpucc
- qcom,sm8150-gpucc
+ - qcom,sm8250-gpucc
clocks:
items:
diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8250.h b/include/dt-bindings/clock/qcom,gpucc-sm8250.h
new file mode 100644
index 000000000000..dc8e387c48ad
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gpucc-sm8250.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
+
+/* GPU_CC clock registers */
+#define GPU_CC_AHB_CLK 0
+#define GPU_CC_CRC_AHB_CLK 1
+#define GPU_CC_CX_APB_CLK 2
+#define GPU_CC_CX_GMU_CLK 3
+#define GPU_CC_CX_SNOC_DVM_CLK 4
+#define GPU_CC_CXO_AON_CLK 5
+#define GPU_CC_CXO_CLK 6
+#define GPU_CC_GMU_CLK_SRC 7
+#define GPU_CC_GX_GMU_CLK 8
+#define GPU_CC_PLL1 9
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 10
+
+/* GPU_CC Resets */
+#define GPUCC_GPU_CC_ACD_BCR 0
+#define GPUCC_GPU_CC_CX_BCR 1
+#define GPUCC_GPU_CC_GFX3D_AON_BCR 2
+#define GPUCC_GPU_CC_GMU_BCR 3
+#define GPUCC_GPU_CC_GX_BCR 4
+#define GPUCC_GPU_CC_XO_BCR 5
+
+/* GPU_CC GDSCRs */
+#define GPU_CX_GDSC 0
+#define GPU_GX_GDSC 1
+
+#endif
--
2.26.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 12/14] dt-bindings: power: Add missing rpmpd rpmh regulator level
2020-07-09 13:52 [PATCH v3 00/14] Enable GPU for SM8150 and SM8250 Jonathan Marek
` (2 preceding siblings ...)
2020-07-09 13:52 ` [PATCH v3 08/14] dt-bindings: clock: add SM8250 " Jonathan Marek
@ 2020-07-09 13:52 ` Jonathan Marek
2020-07-13 23:07 ` Rob Herring
2020-07-09 13:52 ` [PATCH v3 13/14] arm64: dts: qcom: add sm8150 GPU nodes Jonathan Marek
` (2 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Jonathan Marek @ 2020-07-09 13:52 UTC (permalink / raw)
To: linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
Add RPMH_REGULATOR_LEVEL_SVS_L0, used by sm8250.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
include/dt-bindings/power/qcom-rpmpd.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
index dc146e44228b..5e61eaf73bdd 100644
--- a/include/dt-bindings/power/qcom-rpmpd.h
+++ b/include/dt-bindings/power/qcom-rpmpd.h
@@ -55,6 +55,7 @@
#define RPMH_REGULATOR_LEVEL_MIN_SVS 48
#define RPMH_REGULATOR_LEVEL_LOW_SVS 64
#define RPMH_REGULATOR_LEVEL_SVS 128
+#define RPMH_REGULATOR_LEVEL_SVS_L0 144
#define RPMH_REGULATOR_LEVEL_SVS_L1 192
#define RPMH_REGULATOR_LEVEL_SVS_L2 224
#define RPMH_REGULATOR_LEVEL_NOM 256
--
2.26.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 13/14] arm64: dts: qcom: add sm8150 GPU nodes
2020-07-09 13:52 [PATCH v3 00/14] Enable GPU for SM8150 and SM8250 Jonathan Marek
` (3 preceding siblings ...)
2020-07-09 13:52 ` [PATCH v3 12/14] dt-bindings: power: Add missing rpmpd rpmh regulator level Jonathan Marek
@ 2020-07-09 13:52 ` Jonathan Marek
2020-07-09 13:52 ` [PATCH v3 14/14] arm64: dts: qcom: add sm8250 " Jonathan Marek
2020-07-21 7:54 ` [PATCH v3 00/14] Enable GPU for SM8150 and SM8250 Stephen Boyd
6 siblings, 0 replies; 16+ messages in thread
From: Jonathan Marek @ 2020-07-09 13:52 UTC (permalink / raw)
To: linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
This brings up the GPU. Tested on HDK855 by running vulkan CTS.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 136 +++++++++++++++++++++++++++
1 file changed, 136 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index d117a64f591e..b65fd7027d1e 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
+#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -549,6 +550,141 @@ glink-edge {
};
};
+ gpu: gpu@2c00000 {
+ /*
+ * note: the amd,imageon compatible makes it possible
+ * to use the drm/msm driver without the display node,
+ * make sure to remove it when display node is added
+ */
+ compatible = "qcom,adreno-640.1",
+ "qcom,adreno",
+ "amd,imageon";
+ #stream-id-cells = <16>;
+
+ reg = <0 0x2c00000 0 0x40000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&adreno_smmu 0 0x401>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+
+ zap-shader {
+ memory-region = <&gpu_mem>;
+ };
+
+ /* note: downstream checks gpu binning for 675 Mhz */
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-675000000 {
+ opp-hz = /bits/ 64 <675000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ opp-585000000 {
+ opp-hz = /bits/ 64 <585000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ opp-499200000 {
+ opp-hz = /bits/ 64 <499200000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ };
+
+ opp-427000000 {
+ opp-hz = /bits/ 64 <427000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-345000000 {
+ opp-hz = /bits/ 64 <345000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-257000000 {
+ opp-hz = /bits/ 64 <257000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+ };
+ };
+
+ gmu: gmu@2c6a000 {
+ compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
+
+ reg = <0 0x2c6a000 0 0x30000>,
+ <0 0xb290000 0 0x10000>,
+ <0 0xb490000 0 0x10000>;
+ reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+
+ clocks = <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+ clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
+
+ power-domains = <&gpucc GPU_CX_GDSC>,
+ <&gpucc GPU_GX_GDSC>;
+ power-domain-names = "cx", "gx";
+
+ iommus = <&adreno_smmu 5 0x400>;
+
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+ };
+ };
+
+ gpucc: clock-controller@2c90000 {
+ compatible = "qcom,sm8150-gpucc";
+ reg = <0 0x2c90000 0 0x9000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ clock-names = "bi_tcxo",
+ "gcc_gpu_gpll0_clk_src",
+ "gcc_gpu_gpll0_div_clk_src";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ adreno_smmu: iommu@2ca0000 {
+ compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
+ reg = <0 0x2ca0000 0 0x10000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gpucc GPU_CC_AHB_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
+ clock-names = "ahb", "bus", "iface";
+
+ power-domains = <&gpucc GPU_CX_GDSC>;
+ };
+
tlmm: pinctrl@3100000 {
compatible = "qcom,sm8150-pinctrl";
reg = <0x0 0x03100000 0x0 0x300000>,
--
2.26.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 14/14] arm64: dts: qcom: add sm8250 GPU nodes
2020-07-09 13:52 [PATCH v3 00/14] Enable GPU for SM8150 and SM8250 Jonathan Marek
` (4 preceding siblings ...)
2020-07-09 13:52 ` [PATCH v3 13/14] arm64: dts: qcom: add sm8150 GPU nodes Jonathan Marek
@ 2020-07-09 13:52 ` Jonathan Marek
2020-07-21 7:54 ` [PATCH v3 00/14] Enable GPU for SM8150 and SM8250 Stephen Boyd
6 siblings, 0 replies; 16+ messages in thread
From: Jonathan Marek @ 2020-07-09 13:52 UTC (permalink / raw)
To: linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
This brings up the GPU. Tested on HDK865 by running vulkan CTS.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 143 +++++++++++++++++++++++++++
1 file changed, 143 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 3564f233064c..636e2196138c 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
+#include <dt-bindings/clock/qcom,gpucc-sm8250.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
@@ -1131,6 +1132,148 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
};
};
+ gpu: gpu@3d00000 {
+ /*
+ * note: the amd,imageon compatible makes it possible
+ * to use the drm/msm driver without the display node,
+ * make sure to remove it when display node is added
+ */
+ compatible = "qcom,adreno-650.2",
+ "qcom,adreno",
+ "amd,imageon";
+ #stream-id-cells = <16>;
+
+ reg = <0 0x3d00000 0 0x40000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&adreno_smmu 0 0x401>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+
+ zap-shader {
+ memory-region = <&gpu_mem>;
+ };
+
+ /* note: downstream checks gpu binning for 670 Mhz */
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-670000000 {
+ opp-hz = /bits/ 64 <670000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ opp-587000000 {
+ opp-hz = /bits/ 64 <587000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ opp-525000000 {
+ opp-hz = /bits/ 64 <525000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ };
+
+ opp-490000000 {
+ opp-hz = /bits/ 64 <490000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-441600000 {
+ opp-hz = /bits/ 64 <441600000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-305000000 {
+ opp-hz = /bits/ 64 <305000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+ };
+ };
+
+ gmu: gmu@3d6a000 {
+ compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
+
+ reg = <0 0x3d6a000 0 0x30000>,
+ <0 0x3de0000 0 0x10000>,
+ <0 0xb290000 0 0x10000>,
+ <0 0xb490000 0 0x10000>;
+ reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+
+ clocks = <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+ clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
+
+ power-domains = <&gpucc GPU_CX_GDSC>,
+ <&gpucc GPU_GX_GDSC>;
+ power-domain-names = "cx", "gx";
+
+ iommus = <&adreno_smmu 5 0x400>;
+
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+ };
+ };
+
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,sm8250-gpucc";
+ reg = <0 0x3d90000 0 0x9000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ clock-names = "bi_tcxo",
+ "gcc_gpu_gpll0_clk_src",
+ "gcc_gpu_gpll0_div_clk_src";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
+ reg = <0 0x3da0000 0 0x10000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gpucc GPU_CC_AHB_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
+ clock-names = "ahb", "bus", "iface";
+
+ power-domains = <&gpucc GPU_CX_GDSC>;
+ };
+
usb_1_hsphy: phy@88e3000 {
compatible = "qcom,sm8250-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
--
2.26.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3 06/14] dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc
2020-07-09 13:52 ` [PATCH v3 06/14] dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc Jonathan Marek
@ 2020-07-13 23:06 ` Rob Herring
2020-07-24 8:52 ` Stephen Boyd
1 sibling, 0 replies; 16+ messages in thread
From: Rob Herring @ 2020-07-13 23:06 UTC (permalink / raw)
To: Jonathan Marek
Cc: devicetree, linux-arm-msm, Michael Turquette, linux-clk,
Bjorn Andersson, Stephen Boyd, Rob Herring, Taniya Das,
Andy Gross, linux-kernel
On Thu, 09 Jul 2020 09:52:37 -0400, Jonathan Marek wrote:
> These two bindings are almost identical, so combine them into one. This
> will make it easier to add the sm8150 and sm8250 gpucc bindings.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> ...qcom,sdm845-gpucc.yaml => qcom,gpucc.yaml} | 14 ++--
> .../bindings/clock/qcom,sc7180-gpucc.yaml | 74 -------------------
> 2 files changed, 9 insertions(+), 79 deletions(-)
> rename Documentation/devicetree/bindings/clock/{qcom,sdm845-gpucc.yaml => qcom,gpucc.yaml} (82%)
> delete mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 07/14] dt-bindings: clock: add SM8150 QCOM Graphics clock bindings
2020-07-09 13:52 ` [PATCH v3 07/14] dt-bindings: clock: add SM8150 QCOM Graphics clock bindings Jonathan Marek
@ 2020-07-13 23:06 ` Rob Herring
2020-07-24 8:52 ` Stephen Boyd
1 sibling, 0 replies; 16+ messages in thread
From: Rob Herring @ 2020-07-13 23:06 UTC (permalink / raw)
To: Jonathan Marek
Cc: Andy Gross, linux-arm-msm, Michael Turquette, linux-clk,
linux-kernel, devicetree, Rob Herring, Stephen Boyd,
Bjorn Andersson, Taniya Das
On Thu, 09 Jul 2020 09:52:38 -0400, Jonathan Marek wrote:
> Add device tree bindings for graphics clock controller for
> Qualcomm Technology Inc's SM8150 SoCs.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> .../devicetree/bindings/clock/qcom,gpucc.yaml | 4 ++-
> include/dt-bindings/clock/qcom,gpucc-sm8150.h | 33 +++++++++++++++++++
> 2 files changed, 36 insertions(+), 1 deletion(-)
> create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8150.h
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 08/14] dt-bindings: clock: add SM8250 QCOM Graphics clock bindings
2020-07-09 13:52 ` [PATCH v3 08/14] dt-bindings: clock: add SM8250 " Jonathan Marek
@ 2020-07-13 23:06 ` Rob Herring
2020-07-24 8:52 ` Stephen Boyd
1 sibling, 0 replies; 16+ messages in thread
From: Rob Herring @ 2020-07-13 23:06 UTC (permalink / raw)
To: Jonathan Marek
Cc: Michael Turquette, linux-arm-msm, Rob Herring, devicetree,
Stephen Boyd, linux-kernel, Andy Gross, Bjorn Andersson,
Taniya Das, linux-clk
On Thu, 09 Jul 2020 09:52:39 -0400, Jonathan Marek wrote:
> Add device tree bindings for graphics clock controller for
> Qualcomm Technology Inc's SM8250 SoCs.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> .../devicetree/bindings/clock/qcom,gpucc.yaml | 4 ++-
> include/dt-bindings/clock/qcom,gpucc-sm8250.h | 34 +++++++++++++++++++
> 2 files changed, 37 insertions(+), 1 deletion(-)
> create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8250.h
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 12/14] dt-bindings: power: Add missing rpmpd rpmh regulator level
2020-07-09 13:52 ` [PATCH v3 12/14] dt-bindings: power: Add missing rpmpd rpmh regulator level Jonathan Marek
@ 2020-07-13 23:07 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2020-07-13 23:07 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Bjorn Andersson, linux-kernel, devicetree,
Andy Gross, Rob Herring
On Thu, 09 Jul 2020 09:52:43 -0400, Jonathan Marek wrote:
> Add RPMH_REGULATOR_LEVEL_SVS_L0, used by sm8250.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> include/dt-bindings/power/qcom-rpmpd.h | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 00/14] Enable GPU for SM8150 and SM8250
2020-07-09 13:52 [PATCH v3 00/14] Enable GPU for SM8150 and SM8250 Jonathan Marek
` (5 preceding siblings ...)
2020-07-09 13:52 ` [PATCH v3 14/14] arm64: dts: qcom: add sm8250 " Jonathan Marek
@ 2020-07-21 7:54 ` Stephen Boyd
2020-07-21 15:45 ` Dmitry Baryshkov
6 siblings, 1 reply; 16+ messages in thread
From: Stephen Boyd @ 2020-07-21 7:54 UTC (permalink / raw)
To: Jonathan Marek, linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Deepak Katragadda, devicetree,
linux-clk, linux-kernel, Michael Turquette, Rob Herring,
Taniya Das, Vinod Koul
Quoting Jonathan Marek (2020-07-09 06:52:31)
> This series adds the missing clock drivers and dts nodes to enable
> the GPU on both SM8150 and SM8250.
>
> Note an extra drm/msm patch [1] is required for SM8250.
>
> As noted by Dmitry, GMU init fails with newer firmware, needs this patch [2].
>
> [1] https://patchwork.freedesktop.org/series/78968/
> [2] https://git.linaro.org/landing-teams/working/qualcomm/kernel.git/commit/?h=tracking-qcomlt-sm8250&id=01331f2ccbe7e6c4719dbe038a5fb496db32646d
Vinod, can you test this patch series? And Taniya, can you review it?
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 00/14] Enable GPU for SM8150 and SM8250
2020-07-21 7:54 ` [PATCH v3 00/14] Enable GPU for SM8150 and SM8250 Stephen Boyd
@ 2020-07-21 15:45 ` Dmitry Baryshkov
0 siblings, 0 replies; 16+ messages in thread
From: Dmitry Baryshkov @ 2020-07-21 15:45 UTC (permalink / raw)
To: Stephen Boyd, Jonathan Marek, linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Deepak Katragadda, devicetree,
linux-clk, linux-kernel, Michael Turquette, Rob Herring,
Taniya Das, Vinod Koul
On 21/07/2020 10:54, Stephen Boyd wrote:
> Quoting Jonathan Marek (2020-07-09 06:52:31)
>> This series adds the missing clock drivers and dts nodes to enable
>> the GPU on both SM8150 and SM8250.
>>
>> Note an extra drm/msm patch [1] is required for SM8250.
>>
>> As noted by Dmitry, GMU init fails with newer firmware, needs this patch [2].
>>
>> [1] https://patchwork.freedesktop.org/series/78968/
>> [2] https://git.linaro.org/landing-teams/working/qualcomm/kernel.git/commit/?h=tracking-qcomlt-sm8250&id=01331f2ccbe7e6c4719dbe038a5fb496db32646d
>
> Vinod, can you test this patch series? And Taniya, can you review it?
On SM8250:
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 06/14] dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc
2020-07-09 13:52 ` [PATCH v3 06/14] dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc Jonathan Marek
2020-07-13 23:06 ` Rob Herring
@ 2020-07-24 8:52 ` Stephen Boyd
1 sibling, 0 replies; 16+ messages in thread
From: Stephen Boyd @ 2020-07-24 8:52 UTC (permalink / raw)
To: Jonathan Marek, linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Rob Herring,
Taniya Das, linux-clk, devicetree, linux-kernel
Quoting Jonathan Marek (2020-07-09 06:52:37)
> These two bindings are almost identical, so combine them into one. This
> will make it easier to add the sm8150 and sm8250 gpucc bindings.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 07/14] dt-bindings: clock: add SM8150 QCOM Graphics clock bindings
2020-07-09 13:52 ` [PATCH v3 07/14] dt-bindings: clock: add SM8150 QCOM Graphics clock bindings Jonathan Marek
2020-07-13 23:06 ` Rob Herring
@ 2020-07-24 8:52 ` Stephen Boyd
1 sibling, 0 replies; 16+ messages in thread
From: Stephen Boyd @ 2020-07-24 8:52 UTC (permalink / raw)
To: Jonathan Marek, linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Rob Herring,
Taniya Das, linux-clk, devicetree, linux-kernel
Quoting Jonathan Marek (2020-07-09 06:52:38)
> Add device tree bindings for graphics clock controller for
> Qualcomm Technology Inc's SM8150 SoCs.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 08/14] dt-bindings: clock: add SM8250 QCOM Graphics clock bindings
2020-07-09 13:52 ` [PATCH v3 08/14] dt-bindings: clock: add SM8250 " Jonathan Marek
2020-07-13 23:06 ` Rob Herring
@ 2020-07-24 8:52 ` Stephen Boyd
1 sibling, 0 replies; 16+ messages in thread
From: Stephen Boyd @ 2020-07-24 8:52 UTC (permalink / raw)
To: Jonathan Marek, linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Rob Herring,
Taniya Das, linux-clk, devicetree, linux-kernel
Quoting Jonathan Marek (2020-07-09 06:52:39)
> Add device tree bindings for graphics clock controller for
> Qualcomm Technology Inc's SM8250 SoCs.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2020-07-24 8:52 UTC | newest]
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2020-07-09 13:52 [PATCH v3 00/14] Enable GPU for SM8150 and SM8250 Jonathan Marek
2020-07-09 13:52 ` [PATCH v3 06/14] dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc Jonathan Marek
2020-07-13 23:06 ` Rob Herring
2020-07-24 8:52 ` Stephen Boyd
2020-07-09 13:52 ` [PATCH v3 07/14] dt-bindings: clock: add SM8150 QCOM Graphics clock bindings Jonathan Marek
2020-07-13 23:06 ` Rob Herring
2020-07-24 8:52 ` Stephen Boyd
2020-07-09 13:52 ` [PATCH v3 08/14] dt-bindings: clock: add SM8250 " Jonathan Marek
2020-07-13 23:06 ` Rob Herring
2020-07-24 8:52 ` Stephen Boyd
2020-07-09 13:52 ` [PATCH v3 12/14] dt-bindings: power: Add missing rpmpd rpmh regulator level Jonathan Marek
2020-07-13 23:07 ` Rob Herring
2020-07-09 13:52 ` [PATCH v3 13/14] arm64: dts: qcom: add sm8150 GPU nodes Jonathan Marek
2020-07-09 13:52 ` [PATCH v3 14/14] arm64: dts: qcom: add sm8250 " Jonathan Marek
2020-07-21 7:54 ` [PATCH v3 00/14] Enable GPU for SM8150 and SM8250 Stephen Boyd
2020-07-21 15:45 ` Dmitry Baryshkov
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