* [PATCH 1/2] clk: qoriq: modify MAX_PLL_DIV to 32
@ 2020-09-16 3:03 Qiang Zhao
2020-09-16 3:03 ` [PATCH 2/2] arm64: dts: layerscape: modify clocks divider to 32 for wdt Qiang Zhao
2020-10-14 2:48 ` [PATCH 1/2] clk: qoriq: modify MAX_PLL_DIV to 32 Stephen Boyd
0 siblings, 2 replies; 3+ messages in thread
From: Qiang Zhao @ 2020-09-16 3:03 UTC (permalink / raw)
To: shawnguo, robh+dt, mturquette
Cc: andy.tang, linux-kernel, devicetree, linux-clk, Zhao Qiang
From: Zhao Qiang <qiang.zhao@nxp.com>
On LS2088A, Watchdog need clk divided by 32,
so modify MAX_PLL_DIV to 32
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
drivers/clk/clk-qoriq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 5942e98..46101c6 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -31,7 +31,7 @@
#define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
#define CGB_PLL1 4
#define CGB_PLL2 5
-#define MAX_PLL_DIV 16
+#define MAX_PLL_DIV 32
struct clockgen_pll_div {
struct clk *clk;
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] arm64: dts: layerscape: modify clocks divider to 32 for wdt
2020-09-16 3:03 [PATCH 1/2] clk: qoriq: modify MAX_PLL_DIV to 32 Qiang Zhao
@ 2020-09-16 3:03 ` Qiang Zhao
2020-10-14 2:48 ` [PATCH 1/2] clk: qoriq: modify MAX_PLL_DIV to 32 Stephen Boyd
1 sibling, 0 replies; 3+ messages in thread
From: Qiang Zhao @ 2020-09-16 3:03 UTC (permalink / raw)
To: shawnguo, robh+dt, mturquette
Cc: andy.tang, linux-kernel, devicetree, linux-clk, Zhao Qiang
From: Zhao Qiang <qiang.zhao@nxp.com>
On LX2088A, wdt's clock are get from clockgen divided by 32,
so modify clocks in device tree.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 7016791..de6c751 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -194,56 +194,56 @@
cluster1_core0_watchdog: wdt@c000000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 4 31>, <&clockgen 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster1_core1_watchdog: wdt@c010000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc010000 0x0 0x1000>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 4 31>, <&clockgen 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster2_core0_watchdog: wdt@c100000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc100000 0x0 0x1000>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 4 31>, <&clockgen 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster2_core1_watchdog: wdt@c110000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc110000 0x0 0x1000>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 4 31>, <&clockgen 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster3_core0_watchdog: wdt@c200000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc200000 0x0 0x1000>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 4 31>, <&clockgen 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster3_core1_watchdog: wdt@c210000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc210000 0x0 0x1000>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 4 31>, <&clockgen 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster4_core0_watchdog: wdt@c300000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc300000 0x0 0x1000>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 4 31>, <&clockgen 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster4_core1_watchdog: wdt@c310000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc310000 0x0 0x1000>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 4 31>, <&clockgen 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/2] clk: qoriq: modify MAX_PLL_DIV to 32
2020-09-16 3:03 [PATCH 1/2] clk: qoriq: modify MAX_PLL_DIV to 32 Qiang Zhao
2020-09-16 3:03 ` [PATCH 2/2] arm64: dts: layerscape: modify clocks divider to 32 for wdt Qiang Zhao
@ 2020-10-14 2:48 ` Stephen Boyd
1 sibling, 0 replies; 3+ messages in thread
From: Stephen Boyd @ 2020-10-14 2:48 UTC (permalink / raw)
To: Qiang Zhao, mturquette, robh+dt, shawnguo
Cc: andy.tang, linux-kernel, devicetree, linux-clk, Zhao Qiang
Quoting Qiang Zhao (2020-09-15 20:03:10)
> From: Zhao Qiang <qiang.zhao@nxp.com>
>
> On LS2088A, Watchdog need clk divided by 32,
> so modify MAX_PLL_DIV to 32
>
> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-10-14 2:48 UTC | newest]
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2020-09-16 3:03 [PATCH 1/2] clk: qoriq: modify MAX_PLL_DIV to 32 Qiang Zhao
2020-09-16 3:03 ` [PATCH 2/2] arm64: dts: layerscape: modify clocks divider to 32 for wdt Qiang Zhao
2020-10-14 2:48 ` [PATCH 1/2] clk: qoriq: modify MAX_PLL_DIV to 32 Stephen Boyd
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