[PATCH 0/4] Add i.MX8MN power domain and fix USB

[PATCH 0/4] Add i.MX8MN power domain and fix USB

[Adam Ford]

The OTG on the Nano does not work unless the USB was started in 
the bootloader, because was lacking the power-domain control. 

This series is based on patches from [1] and an additional, pending 
patch [2] which removed a USB node which does not exist according to
documentation for the SoC.

[1] - https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=357903
[2] - https://patchwork.kernel.org/project/linux-arm-kernel/patch/20201008183300.726756-1-aford173@gmail.com/

Adam Ford (4):
  dt-bindings: add defines for i.MX8MN power domains
  soc: imx: gpcv2: add support for i.MX8MN power domains
  arm64: dts: imx8mn: add GPC node and power domains
  arm64: dts: imx8mn: Add power-domain reference in USB controller

 .../bindings/power/fsl,imx-gpcv2.yaml         |   1 +
 arch/arm64/boot/dts/freescale/imx8mn.dtsi     |  50 ++++++++
 drivers/soc/imx/gpcv2.c                       | 117 ++++++++++++++++++
 include/dt-bindings/power/imx8mn-power.h      |  15 +++
 4 files changed, 183 insertions(+)
 create mode 100644 include/dt-bindings/power/imx8mn-power.h

-- 
2.25.1

[PATCH 1/4] dt-bindings: add defines for i.MX8MN power domains

[Adam Ford]

The i.MX8M Nano has a similar power domain controller to that of the
mini, but it isn't fully compatible, so it needs a separate binding
and power domain tables.

Add the bindings and tables.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml
index 8dd86f67c210..e71a01a541ad 100644
--- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml
+++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml
@@ -25,6 +25,7 @@ properties:
   compatible:
     enum:
       - fsl,imx7d-gpc
+      - fsl,imx8mn-gpc
       - fsl,imx8mq-gpc
       - fsl,imx8mm-gpc
 
diff --git a/include/dt-bindings/power/imx8mn-power.h b/include/dt-bindings/power/imx8mn-power.h
new file mode 100644
index 000000000000..102ee85a9b62
--- /dev/null
+++ b/include/dt-bindings/power/imx8mn-power.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ *  Copyright (C) 2020 Compass Electronics Group, LLC
+ */
+
+#ifndef __DT_BINDINGS_IMX8MN_POWER_H__
+#define __DT_BINDINGS_IMX8MN_POWER_H__
+
+#define IMX8MN_POWER_DOMAIN_HSIOMIX	0
+#define IMX8MN_POWER_DOMAIN_OTG1	1
+#define IMX8MN_POWER_DOMAIN_GPUMIX	2
+#define IMX8MN_POWER_DOMAIN_DISPMIX	3
+#define IMX8MN_POWER_DOMAIN_MIPI	4
+
+#endif
-- 
2.25.1

[PATCH 2/4] soc: imx: gpcv2: add support for i.MX8MN power domains

[Adam Ford]

This adds support for the power domains founds on i.MX8MN. The Nano
has fewer domains than the Mini, and the access to some of these domains
is different than that of the Mini, the Mini power domains cannot be
reused.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index a118eb9ff8b7..91aad9ea74ee 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -20,6 +20,7 @@
 #include <dt-bindings/power/imx7-power.h>
 #include <dt-bindings/power/imx8mq-power.h>
 #include <dt-bindings/power/imx8mm-power.h>
+#include <dt-bindings/power/imx8mn-power.h>
 
 #define GPC_LPCR_A_CORE_BSC			0x000
 
@@ -58,6 +59,12 @@
 #define IMX8MM_PCIE_A53_DOMAIN			BIT(3)
 #define IMX8MM_MIPI_A53_DOMAIN			BIT(2)
 
+#define IMX8MN_DISPMIX_A53_DOMAIN		BIT(12)
+#define IMX8MN_GPUMIX_A53_DOMAIN		BIT(9)
+#define IMX8MN_DDR1_A53_DOMAIN		BIT(7)
+#define IMX8MN_OTG1_A53_DOMAIN		BIT(4)
+#define IMX8MN_MIPI_A53_DOMAIN		BIT(2)
+
 #define GPC_PU_PGC_SW_PUP_REQ		0x0f8
 #define GPC_PU_PGC_SW_PDN_REQ		0x104
 
@@ -94,6 +101,12 @@
 #define IMX8MM_PCIE_SW_Pxx_REQ			BIT(1)
 #define IMX8MM_MIPI_SW_Pxx_REQ			BIT(0)
 
+#define IMX8MN_DISPMIX_SW_Pxx_REQ		BIT(10)
+#define IMX8MN_GPUMIX_SW_Pxx_REQ		BIT(7)
+#define IMX8MN_DDR1_SW_Pxx_REQ		BIT(5)
+#define IMX8MN_OTG1_SW_Pxx_REQ		BIT(2)
+#define IMX8MN_MIPI_SW_Pxx_REQ		BIT(0)
+
 #define GPC_M4_PU_PDN_FLG		0x1bc
 
 #define GPC_PU_PWRHSK			0x1fc
@@ -116,6 +129,14 @@
 #define IMX8MM_VPUMIX_HSK_PWRDNREQN		BIT(8)
 #define IMX8MM_DISPMIX_HSK_PWRDNREQN		BIT(7)
 #define IMX8MM_HSIO_HSK_PWRDNREQN		(BIT(5) | BIT(6))
+
+#define IMX8MN_GPUMIX_HSK_PWRDNACKN		(BIT(29) | BIT(27))
+#define IMX8MN_DISPMIX_HSK_PWRDNACKN		BIT(25)
+#define IMX8MN_HSIO_HSK_PWRDNACKN		BIT(23)
+#define IMX8MN_GPUMIX_HSK_PWRDNREQN		(BIT(11) | BIT(9))
+#define IMX8MN_DISPMIX_HSK_PWRDNREQN		BIT(7)
+#define IMX8MN_HSIO_HSK_PWRDNREQN		BIT(5)
+
 /*
  * The PGC offset values in Reference Manual
  * (Rev. 1, 01/2018 and the older ones) GPC chapter's
@@ -152,6 +173,12 @@
 #define IMX8MM_PGC_VPUG2		28
 #define IMX8MM_PGC_VPUH1		29
 
+#define IMX8MN_PGC_MIPI		16
+#define IMX8MN_PGC_OTG1		18
+#define IMX8MN_PGC_DDR1		21
+#define IMX8MN_PGC_GPUMIX		23
+#define IMX8MN_PGC_DISPMIX		26
+
 #define GPC_PGC_CTRL(n)			(0x800 + (n) * 0x40)
 #define GPC_PGC_SR(n)			(GPC_PGC_CTRL(n) + 0xc)
 
@@ -766,6 +793,95 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
 	.reg_access_table = &imx8mm_access_table,
 };
 
+
+static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
+	[IMX8MN_POWER_DOMAIN_HSIOMIX] = {
+		.genpd = {
+			.name = "hsiomix",
+		},
+		.bits  = {
+			.pxx = 0, /* no power sequence control */
+			.map = 0, /* no power sequence control */
+			.hskreq = IMX8MN_HSIO_HSK_PWRDNREQN,
+			.hskack = IMX8MN_HSIO_HSK_PWRDNACKN,
+		},
+	},
+
+	[IMX8MN_POWER_DOMAIN_OTG1] = {
+		.genpd = {
+			.name = "usb-otg1",
+		},
+		.bits  = {
+			.pxx = IMX8MN_OTG1_SW_Pxx_REQ,
+			.map = IMX8MN_OTG1_A53_DOMAIN,
+		},
+		.pgc   = IMX8MN_PGC_OTG1,
+	},
+
+	[IMX8MN_POWER_DOMAIN_GPUMIX] = {
+		.genpd = {
+			.name = "gpumix",
+		},
+		.bits  = {
+			.pxx = IMX8MN_GPUMIX_SW_Pxx_REQ,
+			.map = IMX8MN_GPUMIX_A53_DOMAIN,
+			.hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN,
+			.hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
+		},
+		.pgc   = IMX8MN_PGC_GPUMIX,
+	},
+
+	[IMX8MN_POWER_DOMAIN_DISPMIX] = {
+		.genpd = {
+			.name = "dispmix",
+		},
+		.bits  = {
+			.pxx = IMX8MN_DISPMIX_SW_Pxx_REQ,
+			.map = IMX8MN_DISPMIX_A53_DOMAIN,
+			.hskreq = IMX8MN_DISPMIX_HSK_PWRDNREQN,
+			.hskack = IMX8MN_DISPMIX_HSK_PWRDNACKN,
+		},
+		.pgc   = IMX8MN_PGC_DISPMIX,
+	},
+
+	[IMX8MN_POWER_DOMAIN_MIPI] = {
+		.genpd = {
+			.name = "mipi",
+		},
+		.bits  = {
+			.pxx = IMX8MN_MIPI_SW_Pxx_REQ,
+			.map = IMX8MN_MIPI_A53_DOMAIN,
+		},
+		.pgc   = IMX8MN_PGC_MIPI,
+	},
+};
+
+static const struct regmap_range imx8mn_yes_ranges[] = {
+	regmap_reg_range(GPC_LPCR_A_CORE_BSC,
+			 GPC_PU_PWRHSK),
+	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_MIPI),
+			 GPC_PGC_SR(IMX8MN_PGC_MIPI)),
+	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_OTG1),
+			 GPC_PGC_SR(IMX8MN_PGC_OTG1)),
+	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DDR1),
+			 GPC_PGC_SR(IMX8MN_PGC_DDR1)),
+	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_GPUMIX),
+			 GPC_PGC_SR(IMX8MN_PGC_GPUMIX)),
+	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DISPMIX),
+			 GPC_PGC_SR(IMX8MN_PGC_DISPMIX)),
+};
+
+static const struct regmap_access_table imx8mn_access_table = {
+	.yes_ranges	= imx8mn_yes_ranges,
+	.n_yes_ranges	= ARRAY_SIZE(imx8mn_yes_ranges),
+};
+
+static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = {
+	.domains = imx8mn_pgc_domains,
+	.domains_num = ARRAY_SIZE(imx8mn_pgc_domains),
+	.reg_access_table = &imx8mn_access_table,
+};
+
 static int imx_pgc_get_clocks(struct imx_pgc_domain *domain)
 {
 	int i, ret;
@@ -995,6 +1111,7 @@ static const struct of_device_id imx_gpcv2_dt_ids[] = {
 	{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
 	{ .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
 	{ .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
+	{ .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, },
 	{ }
 };
 
-- 
2.25.1

[PATCH 3/4] arm64: dts: imx8mn: add GPC node and power domains

[Adam Ford]

This adds the DT nodes to describe the power domains available on the
i.MX8MN. There are four power domains, but the displaymix and mipi
power domains need a separate clock block controller which is also
pending for 8MP and 8MM. Once the path for those is clear, Nano will
need something similar, but the registers for Nano differ.  For now,
the dispmix and mipi are placeholders.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 9b4baf7bdfb1..27733fbe87e9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -596,6 +596,55 @@ src: reset-controller@30390000 {
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 				#reset-cells = <1>;
 			};
+
+			gpc: gpc@303a0000 {
+				compatible = "fsl,imx8mn-gpc";
+				reg = <0x303a0000 0x10000>;
+				interrupt-parent = <&gic>;
+				interrupt-controller;
+				#interrupt-cells = <3>;
+
+				pgc {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pgc_hsiomix: power-domain@0 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>;
+						clocks = <&clk IMX8MN_CLK_USB_BUS>;
+					};
+
+					pgc_otg1: power-domain@1 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MN_POWER_DOMAIN_OTG1>;
+						power-domains = <&pgc_hsiomix>;
+					};
+
+					pgc_gpumix: power-domain@2 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
+						clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
+							 <&clk IMX8MN_CLK_GPU_SHADER_DIV>,
+							 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
+							 <&clk IMX8MN_CLK_GPU_AHB>;
+						resets = <&src IMX8MQ_RESET_GPU_RESET>;
+					};
+
+					dispmix_pd: power-domain@3 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MN_POWER_DOMAIN_DISPMIX>;
+						clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
+							 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+							 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+					};
+
+					mipi_pd: power-domain@4 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MN_POWER_DOMAIN_MIPI>;
+						power-domains = <&dispmix_pd>;
+					};
+				};
+			};
 		};
 
 		aips2: bus@30400000 {
-- 
2.25.1

[PATCH 4/4] arm64: dts: imx8mn: Add power-domain reference in USB controller

[Adam Ford]

The USB OTG controller cannot be used until the power-domain is enabled
unless it was started in the bootloader.

Adding the power-domain reference to the OTG node allows the OTG
controller to operate.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 27733fbe87e9..605e6dbd2c6f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -979,6 +979,7 @@ usbotg1: usb@32e40000 {
 				assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
 				fsl,usbphy = <&usbphynop1>;
 				fsl,usbmisc = <&usbmisc1 0>;
+				power-domains = <&pgc_otg1>;
 				status = "disabled";
 			};
 
-- 
2.25.1

Re: [PATCH 1/4] dt-bindings: add defines for i.MX8MN power domains

[Krzysztof Kozlowski]

On Thu, Oct 22, 2020 at 10:08:04AM -0500, Adam Ford wrote:
> The i.MX8M Nano has a similar power domain controller to that of the
> mini, but it isn't fully compatible, so it needs a separate binding
> and power domain tables.
> 
> Add the bindings and tables.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> 

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

Re: [PATCH 2/4] soc: imx: gpcv2: add support for i.MX8MN power domains

[Krzysztof Kozlowski]

On Thu, Oct 22, 2020 at 10:08:05AM -0500, Adam Ford wrote:
> This adds support for the power domains founds on i.MX8MN. The Nano
> has fewer domains than the Mini, and the access to some of these domains
> is different than that of the Mini, the Mini power domains cannot be
> reused.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

Re: [PATCH 3/4] arm64: dts: imx8mn: add GPC node and power domains

[Krzysztof Kozlowski]

On Thu, Oct 22, 2020 at 10:08:06AM -0500, Adam Ford wrote:
> This adds the DT nodes to describe the power domains available on the
> i.MX8MN. There are four power domains, but the displaymix and mipi
> power domains need a separate clock block controller which is also
> pending for 8MP and 8MM. Once the path for those is clear, Nano will
> need something similar, but the registers for Nano differ.  For now,
> the dispmix and mipi are placeholders.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 9b4baf7bdfb1..27733fbe87e9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -596,6 +596,55 @@ src: reset-controller@30390000 {
>  				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
>  				#reset-cells = <1>;
>  			};
> +
> +			gpc: gpc@303a0000 {
> +				compatible = "fsl,imx8mn-gpc";
> +				reg = <0x303a0000 0x10000>;
> +				interrupt-parent = <&gic>;
> +				interrupt-controller;
> +				#interrupt-cells = <3>;

Missing interrupts.

> +
> +				pgc {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					pgc_hsiomix: power-domain@0 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>;
> +						clocks = <&clk IMX8MN_CLK_USB_BUS>;
> +					};
> +
> +					pgc_otg1: power-domain@1 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MN_POWER_DOMAIN_OTG1>;
> +						power-domains = <&pgc_hsiomix>;
> +					};
> +
> +					pgc_gpumix: power-domain@2 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
> +						clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
> +							 <&clk IMX8MN_CLK_GPU_SHADER_DIV>,
> +							 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
> +							 <&clk IMX8MN_CLK_GPU_AHB>;
> +						resets = <&src IMX8MQ_RESET_GPU_RESET>;

Does it compile without include? Did the include come via dependencies
of this patch?

Best regards,
Krzysztof

Re: [PATCH 4/4] arm64: dts: imx8mn: Add power-domain reference in USB controller

[Krzysztof Kozlowski]

On Thu, Oct 22, 2020 at 10:08:07AM -0500, Adam Ford wrote:
> The USB OTG controller cannot be used until the power-domain is enabled
> unless it was started in the bootloader.
> 
> Adding the power-domain reference to the OTG node allows the OTG
> controller to operate.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> 

I wonder, why your patches do not have usual Git trailer with summary of
changes (after '---')?

> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 27733fbe87e9..605e6dbd2c6f 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -979,6 +979,7 @@ usbotg1: usb@32e40000 {
>  				assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
>  				fsl,usbphy = <&usbphynop1>;
>  				fsl,usbmisc = <&usbmisc1 0>;
> +				power-domains = <&pgc_otg1>;

I guess you need it also for the usbphynop1 and usbmisc1.

Best regards,
Krzysztof

Re: [PATCH 3/4] arm64: dts: imx8mn: add GPC node and power domains

[Adam Ford]

On Fri, Oct 23, 2020 at 4:52 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On Thu, Oct 22, 2020 at 10:08:06AM -0500, Adam Ford wrote:
> > This adds the DT nodes to describe the power domains available on the
> > i.MX8MN. There are four power domains, but the displaymix and mipi
> > power domains need a separate clock block controller which is also
> > pending for 8MP and 8MM. Once the path for those is clear, Nano will
> > need something similar, but the registers for Nano differ.  For now,
> > the dispmix and mipi are placeholders.
> >
> > Signed-off-by: Adam Ford <aford173@gmail.com>
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > index 9b4baf7bdfb1..27733fbe87e9 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > @@ -596,6 +596,55 @@ src: reset-controller@30390000 {
> >                               interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> >                               #reset-cells = <1>;
> >                       };
> > +
> > +                     gpc: gpc@303a0000 {
> > +                             compatible = "fsl,imx8mn-gpc";
> > +                             reg = <0x303a0000 0x10000>;
> > +                             interrupt-parent = <&gic>;
> > +                             interrupt-controller;
> > +                             #interrupt-cells = <3>;
>
> Missing interrupts.
Oops.  I'll go back and review this.

>
> > +
> > +                             pgc {
> > +                                     #address-cells = <1>;
> > +                                     #size-cells = <0>;
> > +
> > +                                     pgc_hsiomix: power-domain@0 {
> > +                                             #power-domain-cells = <0>;
> > +                                             reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>;
> > +                                             clocks = <&clk IMX8MN_CLK_USB_BUS>;
> > +                                     };
> > +
> > +                                     pgc_otg1: power-domain@1 {
> > +                                             #power-domain-cells = <0>;
> > +                                             reg = <IMX8MN_POWER_DOMAIN_OTG1>;
> > +                                             power-domains = <&pgc_hsiomix>;
> > +                                     };
> > +
> > +                                     pgc_gpumix: power-domain@2 {
> > +                                             #power-domain-cells = <0>;
> > +                                             reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
> > +                                             clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
> > +                                                      <&clk IMX8MN_CLK_GPU_SHADER_DIV>,
> > +                                                      <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
> > +                                                      <&clk IMX8MN_CLK_GPU_AHB>;
> > +                                             resets = <&src IMX8MQ_RESET_GPU_RESET>;
>
> Does it compile without include? Did the include come via dependencies
> of this patch?

Oops.  I cherry picked the git commits, but I forgot to include the
includes which is why it compiles for me.  I'll fix in a V2.

Thanks for all the reviews.

adam
>
> Best regards,
> Krzysztof
>

Re: [PATCH 4/4] arm64: dts: imx8mn: Add power-domain reference in USB controller

[Adam Ford]

On Fri, Oct 23, 2020 at 4:55 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On Thu, Oct 22, 2020 at 10:08:07AM -0500, Adam Ford wrote:
> > The USB OTG controller cannot be used until the power-domain is enabled
> > unless it was started in the bootloader.
> >
> > Adding the power-domain reference to the OTG node allows the OTG
> > controller to operate.
> >
> > Signed-off-by: Adam Ford <aford173@gmail.com>
> >
>
> I wonder, why your patches do not have usual Git trailer with summary of
> changes (after '---')?

I historically have just done 'git format-patch -pX'  but I haven't
seen complaints that the summary was missing.  I can add them going
forward.  Most of these individual patches have only touched single
files or created new files all together.

>
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > index 27733fbe87e9..605e6dbd2c6f 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > @@ -979,6 +979,7 @@ usbotg1: usb@32e40000 {
> >                               assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
> >                               fsl,usbphy = <&usbphynop1>;
> >                               fsl,usbmisc = <&usbmisc1 0>;
> > +                             power-domains = <&pgc_otg1>;
>
> I guess you need it also for the usbphynop1 and usbmisc1.

From what I can see looking at the IP blocks and the vendor's code
repo, only the usbotg IP block needs the power-domain to enable the
clocking going to it.  AFAICT, neither the usbphynop nor the usbmisc
are using clocks gated by the power-domain.
Thanks again for all your reviews.

adam
>
> Best regards,
> Krzysztof

Re: [PATCH 4/4] arm64: dts: imx8mn: Add power-domain reference in USB controller

[Krzysztof Kozlowski]

On Fri, Oct 23, 2020 at 06:03:32AM -0500, Adam Ford wrote:
> On Fri, Oct 23, 2020 at 4:55 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >
> > On Thu, Oct 22, 2020 at 10:08:07AM -0500, Adam Ford wrote:
> > > The USB OTG controller cannot be used until the power-domain is enabled
> > > unless it was started in the bootloader.
> > >
> > > Adding the power-domain reference to the OTG node allows the OTG
> > > controller to operate.
> > >
> > > Signed-off-by: Adam Ford <aford173@gmail.com>
> > >
> >
> > I wonder, why your patches do not have usual Git trailer with summary of
> > changes (after '---')?
> 
> I historically have just done 'git format-patch -pX'  but I haven't
> seen complaints that the summary was missing.  I can add them going
> forward.  Most of these individual patches have only touched single
> files or created new files all together.

The patch stat is useful, especially if it touches multiple
files/subsystems. However it's not needed, so I was just wondering :)

> 
> >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > > index 27733fbe87e9..605e6dbd2c6f 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > > @@ -979,6 +979,7 @@ usbotg1: usb@32e40000 {
> > >                               assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
> > >                               fsl,usbphy = <&usbphynop1>;
> > >                               fsl,usbmisc = <&usbmisc1 0>;
> > > +                             power-domains = <&pgc_otg1>;
> >
> > I guess you need it also for the usbphynop1 and usbmisc1.
> 
> From what I can see looking at the IP blocks and the vendor's code
> repo, only the usbotg IP block needs the power-domain to enable the
> clocking going to it.  AFAICT, neither the usbphynop nor the usbmisc
> are using clocks gated by the power-domain.
> Thanks again for all your reviews.

Mhm, ok then.  Thanks for checking.

Best regards,
Krzysztof

Re: [PATCH 1/4] dt-bindings: add defines for i.MX8MN power domains

[Rob Herring]

On Thu, 22 Oct 2020 10:08:04 -0500, Adam Ford wrote:
> The i.MX8M Nano has a similar power domain controller to that of the
> mini, but it isn't fully compatible, so it needs a separate binding
> and power domain tables.
> 
> Add the bindings and tables.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> 

Acked-by: Rob Herring <robh@kernel.org>