[PATCH 0/3] Add HwSpinlock & Mailbox nodes on J7200 SoCs

[PATCH 0/3] Add HwSpinlock & Mailbox nodes on J7200 SoCs

[Suman Anna]

Hi Nishanth,

The following series adds the HwSpinlock and Mailbox nodes for the J7200
series. The sub-mailbox nodes that will be used by the K3 R5F remoteproc
nodes are also added to the k3-j7200-som-p0.dtsi file in sync with the
convention used on J721E SoCs.

Patches are based on 5.10-rc1 and your current staged branch commit 
9dcd17be61e4 ("arm64: dts: ti: k3-am65: ringacc: drop 
ti,dma-ring-reset-quirk")

FYI, the HwSpinlock binding has been converted to YAML in 5.10-rc1, but
the Mailbox bindings are still in text format.

regards
Suman

Suman Anna (3):
  arm64: dts: ti: k3-j7200-main: Add hwspinlock node
  arm64: dts: ti: k3-j7200-main: Add mailbox cluster nodes
  arm64: dts: ti: k3-j7200-som-p0: Add IPC sub-mailbox nodes

 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi   | 114 ++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi |  68 ++++++++++++
 2 files changed, 182 insertions(+)

-- 
2.28.0

[PATCH 1/3] arm64: dts: ti: k3-j7200-main: Add hwspinlock node

[Suman Anna]

The Main NavSS block on J7200 SoCs contains a HwSpinlock IP instance that
is same as the IP on AM65x and J721E SoCs. Add the DT node for this on
J7200 SoCs. The node is present within the Main NavSS block, and is added
as a child node under the main_navss interconnect node.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 72d6496e88dd..4c53a3036066 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -115,6 +115,12 @@ secure_proxy_main: mailbox@32c00000 {
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		hwspinlock: spinlock@30e00000 {
+			compatible = "ti,am654-hwspinlock";
+			reg = <0x00 0x30e00000 0x00 0x1000>;
+			#hwlock-cells = <1>;
+		};
+
 		main_ringacc: ringacc@3c000000 {
 			compatible = "ti,am654-navss-ringacc";
 			reg =	<0x00 0x3c000000 0x00 0x400000>,
-- 
2.28.0

[PATCH 2/3] arm64: dts: ti: k3-j7200-main: Add mailbox cluster nodes

[Suman Anna]

The J7200 Main NavSS block contains a Mailbox IP instance with
multiple clusters, and follows the same integration style as on
J721E SoCs.

Add all the Mailbox clusters as their own nodes under the MAIN
NavSS interconnect node instead of creating an almost empty parent
node for the new K3 mailbox IP and the clusters as its child nodes.
All these nodes are enabled by default in the base dtsi file, but
any cluster that does not define any child sub-mailbox nodes
should be disabled in the corresponding board dts files.

NOTE:
The NavSS only has a limited number of interrupts, so none of the
interrupts generated by a Mailbox IP are added by default. Only
the needed interrupts that are targeted towards the A72 GIC will
have to be added later on in the board dts files alongside the
corresponding sub-mailbox child nodes.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 108 ++++++++++++++++++++++
 1 file changed, 108 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 4c53a3036066..b0094212aa82 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -121,6 +121,114 @@ hwspinlock: spinlock@30e00000 {
 			#hwlock-cells = <1>;
 		};
 
+		mailbox0_cluster0: mailbox@31f80000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f80000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster1: mailbox@31f81000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f81000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster2: mailbox@31f82000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f82000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster3: mailbox@31f83000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f83000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster4: mailbox@31f84000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f84000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster5: mailbox@31f85000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f85000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster6: mailbox@31f86000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f86000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster7: mailbox@31f87000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f87000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster8: mailbox@31f88000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f88000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster9: mailbox@31f89000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f89000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster10: mailbox@31f8a000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f8a000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster11: mailbox@31f8b000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f8b000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
 		main_ringacc: ringacc@3c000000 {
 			compatible = "ti,am654-navss-ringacc";
 			reg =	<0x00 0x3c000000 0x00 0x400000>,
-- 
2.28.0

[PATCH 3/3] arm64: dts: ti: k3-j7200-som-p0: Add IPC sub-mailbox nodes

[Suman Anna]

Add the sub-mailbox nodes that are used to communicate between MPU and
various remote processors present in the J7200 SoCs to the J7200 common
processor board. These include the R5F remote processors in the dual-R5F
clusters in the MCU domain (MCU_R5FSS0) and the MAIN domain (MAIN_R5FSS0).
These sub-mailbox nodes utilize the System Mailbox clusters 0 and 1. All
the remaining mailbox clusters are currently not used on A72 core, and
so are disabled. The nodes are added in the k3-j7200-som-p0.dtsi file
to co-locate these alongside future reserved-memory nodes required for
remoteprocs.

The sub-mailbox nodes added match the hard-coded mailbox configuration
used within the TI RTOS IPC software packages. A sub-mailbox node is added
for each of the R5F cores to accommodate the R5F processor sub-systems
running in Split mode. Only the sub-mailbox node for the first R5F core in
each cluster is used in case of Lockstep mode for that R5F cluster.

NOTE:
The GIC_SPI interrupts to be used are dynamically allocated and managed
by the System Firmware through the ti-sci-intr irqchip driver. So, only
valid interrupts that are used by the sub-mailbox devices (each cluster's
User 0 IRQ output) are enabled. This is done to minimize the number of
NavSS Interrupt Router outputs utilized.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 68 +++++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
index 6a98ba499bc2..fbd17d38f6b6 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
@@ -63,3 +63,71 @@ flash@0,0 {
 		reg = <0x00 0x00 0x4000000>;
 	};
 };
+
+&mailbox0_cluster0 {
+	interrupts = <436>;
+
+	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster1 {
+	interrupts = <432>;
+
+	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster2 {
+	status = "disabled";
+};
+
+&mailbox0_cluster3 {
+	status = "disabled";
+};
+
+&mailbox0_cluster4 {
+	status = "disabled";
+};
+
+&mailbox0_cluster5 {
+	status = "disabled";
+};
+
+&mailbox0_cluster6 {
+	status = "disabled";
+};
+
+&mailbox0_cluster7 {
+	status = "disabled";
+};
+
+&mailbox0_cluster8 {
+	status = "disabled";
+};
+
+&mailbox0_cluster9 {
+	status = "disabled";
+};
+
+&mailbox0_cluster10 {
+	status = "disabled";
+};
+
+&mailbox0_cluster11 {
+	status = "disabled";
+};
-- 
2.28.0

Re: [PATCH 0/3] Add HwSpinlock & Mailbox nodes on J7200 SoCs

[Nishanth Menon]

On 18:26-20201026, Suman Anna wrote:
> Hi Nishanth,
> 
> The following series adds the HwSpinlock and Mailbox nodes for the J7200
> series. The sub-mailbox nodes that will be used by the K3 R5F remoteproc
> nodes are also added to the k3-j7200-som-p0.dtsi file in sync with the
> convention used on J721E SoCs.
> 
> Patches are based on 5.10-rc1 and your current staged branch commit 
> 9dcd17be61e4 ("arm64: dts: ti: k3-am65: ringacc: drop 
> ti,dma-ring-reset-quirk")
> 
> FYI, the HwSpinlock binding has been converted to YAML in 5.10-rc1, but
> the Mailbox bindings are still in text format.
> 
> regards
> Suman
> 
> Suman Anna (3):
>   arm64: dts: ti: k3-j7200-main: Add hwspinlock node
>   arm64: dts: ti: k3-j7200-main: Add mailbox cluster nodes
>   arm64: dts: ti: k3-j7200-som-p0: Add IPC sub-mailbox nodes
> 
>  arch/arm64/boot/dts/ti/k3-j7200-main.dtsi   | 114 ++++++++++++++++++++
>  arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi |  68 ++++++++++++
>  2 files changed, 182 insertions(+)
> 
> -- 
> 2.28.0
> 

I dont personally see a specific issue in this series, but will
appreciate additional reviewed-by before I pick this series up.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH 0/3] Add HwSpinlock & Mailbox nodes on J7200 SoCs

[Bajjuri, Praneeth]

On 10/27/2020 7:41 AM, Nishanth Menon wrote:
> On 18:26-20201026, Suman Anna wrote:
>> Hi Nishanth,
>>
>> The following series adds the HwSpinlock and Mailbox nodes for the J7200
>> series. The sub-mailbox nodes that will be used by the K3 R5F remoteproc
>> nodes are also added to the k3-j7200-som-p0.dtsi file in sync with the
>> convention used on J721E SoCs.
>>
>> Patches are based on 5.10-rc1 and your current staged branch commit
>> 9dcd17be61e4 ("arm64: dts: ti: k3-am65: ringacc: drop
>> ti,dma-ring-reset-quirk")
>>
>> FYI, the HwSpinlock binding has been converted to YAML in 5.10-rc1, but
>> the Mailbox bindings are still in text format.
>>
>> regards
>> Suman
>>
>> Suman Anna (3):
>>    arm64: dts: ti: k3-j7200-main: Add hwspinlock node
>>    arm64: dts: ti: k3-j7200-main: Add mailbox cluster nodes
>>    arm64: dts: ti: k3-j7200-som-p0: Add IPC sub-mailbox nodes
>>
>>   arch/arm64/boot/dts/ti/k3-j7200-main.dtsi   | 114 ++++++++++++++++++++
>>   arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi |  68 ++++++++++++
>>   2 files changed, 182 insertions(+)
>>
>> -- 
>> 2.28.0
>>
> 
> I dont personally see a specific issue in this series, but will
> appreciate additional reviewed-by before I pick this series up.

Reviewed-by: Praneeth Bajjuri <praneeth@ti.com>

> 

Re: [PATCH 0/3] Add HwSpinlock & Mailbox nodes on J7200 SoCs

[Nishanth Menon]

On Mon, 26 Oct 2020 18:26:34 -0500, Suman Anna wrote:
> The following series adds the HwSpinlock and Mailbox nodes for the J7200
> series. The sub-mailbox nodes that will be used by the K3 R5F remoteproc
> nodes are also added to the k3-j7200-som-p0.dtsi file in sync with the
> convention used on J721E SoCs.
> 
> Patches are based on 5.10-rc1 and your current staged branch commit
> 9dcd17be61e4 ("arm64: dts: ti: k3-am65: ringacc: drop
> ti,dma-ring-reset-quirk")
> 
> [...]

Hi Suman Anna,

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/3] arm64: dts: ti: k3-j7200-main: Add hwspinlock node
      commit: 1d7a01c40840d844fb5d353c151f0ee0a7680c2f
[2/3] arm64: dts: ti: k3-j7200-main: Add mailbox cluster nodes
      commit: d15d1cfbd765b4b2a113b6025e8edc7db4a7800a
[3/3] arm64: dts: ti: k3-j7200-som-p0: Add IPC sub-mailbox nodes
      commit: 6804a987de733c805675973e3afde128fe7a7cfa


All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D