* [PATCH v1] arm64: dts: add spi nodes for MT6779
@ 2021-01-26 13:35 Mason Zhang
2021-01-26 13:35 ` [PATCH v1 1/1] arm64: dts: mt6779: add spi host dts nodes Mason Zhang
0 siblings, 1 reply; 2+ messages in thread
From: Mason Zhang @ 2021-01-26 13:35 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger
Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
hanks.chen, Mason Zhang
This patch adds support spi to MT6779 SOC
Signed-off-by: Mason Zhang <mason.zhang@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
index 370f309d32de..272f4346d35e 100644
--- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -219,6 +219,102 @@
status = "disabled";
};
+ spi0: spi0@1100a000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x1100a000 0 0x1000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi1: spi1@11010000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11010000 0 0x1000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI1>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi2: spi2@11012000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11012000 0 0x1000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI2>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi3: spi3@11013000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11013000 0 0x1000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI3>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi4: spi4@11018000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11018000 0 0x1000>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI4>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi5: spi5@11019000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11019000 0 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI5>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi6: spi6@1101d000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x1101d000 0 0x1000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI6>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi7: spi7@1101e000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x1101e000 0 0x1000>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI7>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
audio: clock-controller@11210000 {
compatible = "mediatek,mt6779-audio", "syscon";
reg = <0 0x11210000 0 0x1000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [PATCH v1 1/1] arm64: dts: mt6779: add spi host dts nodes
2021-01-26 13:35 [PATCH v1] arm64: dts: add spi nodes for MT6779 Mason Zhang
@ 2021-01-26 13:35 ` Mason Zhang
0 siblings, 0 replies; 2+ messages in thread
From: Mason Zhang @ 2021-01-26 13:35 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger
Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
hanks.chen, Mason Zhang
this patch add spi host dts nodes for mt6779 IC.
Change-Id: If4a3cbb09843f472210b390352db4b9886f5c00c
Signed-off-by: Mason Zhang <mason.zhang@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
index 370f309d32de..272f4346d35e 100644
--- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -219,6 +219,102 @@
status = "disabled";
};
+ spi0: spi0@1100a000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x1100a000 0 0x1000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi1: spi1@11010000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11010000 0 0x1000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI1>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi2: spi2@11012000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11012000 0 0x1000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI2>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi3: spi3@11013000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11013000 0 0x1000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI3>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi4: spi4@11018000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11018000 0 0x1000>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI4>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi5: spi5@11019000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11019000 0 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI5>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi6: spi6@1101d000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x1101d000 0 0x1000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI6>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi7: spi7@1101e000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x1101e000 0 0x1000>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI7>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
audio: clock-controller@11210000 {
compatible = "mediatek,mt6779-audio", "syscon";
reg = <0 0x11210000 0 0x1000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
end of thread, other threads:[~2021-01-26 14:00 UTC | newest]
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2021-01-26 13:35 [PATCH v1] arm64: dts: add spi nodes for MT6779 Mason Zhang
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