* [RESEND PATCH v3 0/2] STM32 USBPHYC ck_usbo_48m clock provider
@ 2021-03-04 16:04 Amelie Delaunay
2021-03-04 16:04 ` [RESEND PATCH v3 1/2] dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property Amelie Delaunay
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Amelie Delaunay @ 2021-03-04 16:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Alexandre Torgue, Maxime Coquelin
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-stm32, Amelie Delaunay
STM32 USBPHYC provides clocks to STM32 RCC pour STM32 USB controllers.
Specifically, ck_usbo_48m is a possible clock parent for USB OTG clock,
during OTG Full-Speed operation.
This series registers the usbphyc as clock provider of this ck_usbo_48m clock.
---
Changes in v3:
- remove #clock-cells from required properties
Changes in v2:
- fix COMMON_CLK dependency issue reported by kernel test robot
---
Amelie Delaunay (2):
dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property
phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock
.../bindings/phy/phy-stm32-usbphyc.yaml | 5 ++
drivers/phy/st/Kconfig | 1 +
drivers/phy/st/phy-stm32-usbphyc.c | 65 +++++++++++++++++++
3 files changed, 71 insertions(+)
--
2.17.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [RESEND PATCH v3 1/2] dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property
2021-03-04 16:04 [RESEND PATCH v3 0/2] STM32 USBPHYC ck_usbo_48m clock provider Amelie Delaunay
@ 2021-03-04 16:04 ` Amelie Delaunay
2021-03-04 16:04 ` [RESEND PATCH v3 2/2] phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock Amelie Delaunay
2021-03-15 9:57 ` [RESEND PATCH v3 0/2] STM32 USBPHYC ck_usbo_48m clock provider Vinod Koul
2 siblings, 0 replies; 5+ messages in thread
From: Amelie Delaunay @ 2021-03-04 16:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Alexandre Torgue, Maxime Coquelin
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-stm32, Amelie Delaunay
usbphyc provides a unique clock called ck_usbo_48m.
STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation.
ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock.
ck_usbo_48m is available as soon as the PLL is enabled.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v3:
- add Rob's Acked-by
- remove #clock-cells from required properties
---
Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 46df6786727a..018cc1246ee1 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -51,6 +51,10 @@ properties:
vdda1v8-supply:
description: regulator providing 1V8 power supply to the PLL block
+ '#clock-cells':
+ description: number of clock cells for ck_usbo_48m consumer
+ const: 0
+
#Required child nodes:
patternProperties:
@@ -120,6 +124,7 @@ examples:
vdda1v8-supply = <®18>;
#address-cells = <1>;
#size-cells = <0>;
+ #clock-cells = <0>;
usbphyc_port0: usb-phy@0 {
reg = <0>;
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [RESEND PATCH v3 2/2] phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock
2021-03-04 16:04 [RESEND PATCH v3 0/2] STM32 USBPHYC ck_usbo_48m clock provider Amelie Delaunay
2021-03-04 16:04 ` [RESEND PATCH v3 1/2] dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property Amelie Delaunay
@ 2021-03-04 16:04 ` Amelie Delaunay
2021-03-15 9:57 ` [RESEND PATCH v3 0/2] STM32 USBPHYC ck_usbo_48m clock provider Vinod Koul
2 siblings, 0 replies; 5+ messages in thread
From: Amelie Delaunay @ 2021-03-04 16:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Alexandre Torgue, Maxime Coquelin
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-stm32, Amelie Delaunay
ck_usbo_48m is generated by usbphyc PLL and used by OTG controller
for Full-Speed use cases with dedicated Full-Speed transceiver.
ck_usbo_48m is available as soon as the PLL is enabled.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
---
No changes in v3.
Changes in v2:
- fix COMMON_CLK dependency issue reported by kernel test robot
---
drivers/phy/st/Kconfig | 1 +
drivers/phy/st/phy-stm32-usbphyc.c | 65 ++++++++++++++++++++++++++++++
2 files changed, 66 insertions(+)
diff --git a/drivers/phy/st/Kconfig b/drivers/phy/st/Kconfig
index b32f44ff9033..3fc3d0781fb8 100644
--- a/drivers/phy/st/Kconfig
+++ b/drivers/phy/st/Kconfig
@@ -36,6 +36,7 @@ config PHY_STIH407_USB
config PHY_STM32_USBPHYC
tristate "STMicroelectronics STM32 USB HS PHY Controller driver"
depends on ARCH_STM32 || COMPILE_TEST
+ depends on COMMON_CLK
select GENERIC_PHY
help
Enable this to support the High-Speed USB transceivers that are part
diff --git a/drivers/phy/st/phy-stm32-usbphyc.c b/drivers/phy/st/phy-stm32-usbphyc.c
index d08fbb180e43..c184f4e34584 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -7,6 +7,7 @@
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
@@ -70,6 +71,7 @@ struct stm32_usbphyc {
struct regulator *vdda1v1;
struct regulator *vdda1v8;
atomic_t n_pll_cons;
+ struct clk_hw clk48_hw;
int switch_setup;
};
@@ -295,6 +297,61 @@ static const struct phy_ops stm32_usbphyc_phy_ops = {
.owner = THIS_MODULE,
};
+static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
+{
+ struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
+
+ return stm32_usbphyc_pll_enable(usbphyc);
+}
+
+static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
+{
+ struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
+
+ stm32_usbphyc_pll_disable(usbphyc);
+}
+
+static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ return 48000000;
+}
+
+static const struct clk_ops usbphyc_clk48_ops = {
+ .prepare = stm32_usbphyc_clk48_prepare,
+ .unprepare = stm32_usbphyc_clk48_unprepare,
+ .recalc_rate = stm32_usbphyc_clk48_recalc_rate,
+};
+
+static void stm32_usbphyc_clk48_unregister(void *data)
+{
+ struct stm32_usbphyc *usbphyc = data;
+
+ of_clk_del_provider(usbphyc->dev->of_node);
+ clk_hw_unregister(&usbphyc->clk48_hw);
+}
+
+static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
+{
+ struct device_node *node = usbphyc->dev->of_node;
+ struct clk_init_data init = { };
+ int ret = 0;
+
+ init.name = "ck_usbo_48m";
+ init.ops = &usbphyc_clk48_ops;
+
+ usbphyc->clk48_hw.init = &init;
+
+ ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
+ if (ret)
+ return ret;
+
+ ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &usbphyc->clk48_hw);
+ if (ret)
+ clk_hw_unregister(&usbphyc->clk48_hw);
+
+ return ret;
+}
+
static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
u32 utmi_switch)
{
@@ -473,6 +530,12 @@ static int stm32_usbphyc_probe(struct platform_device *pdev)
goto clk_disable;
}
+ ret = stm32_usbphyc_clk48_register(usbphyc);
+ if (ret) {
+ dev_err(dev, "failed to register ck_usbo_48m clock: %d\n", ret);
+ goto clk_disable;
+ }
+
version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
dev_info(dev, "registered rev:%lu.%lu\n",
FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
@@ -497,6 +560,8 @@ static int stm32_usbphyc_remove(struct platform_device *pdev)
if (usbphyc->phys[port]->active)
stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
+ stm32_usbphyc_clk48_unregister(usbphyc);
+
clk_disable_unprepare(usbphyc->clk);
return 0;
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [RESEND PATCH v3 0/2] STM32 USBPHYC ck_usbo_48m clock provider
2021-03-04 16:04 [RESEND PATCH v3 0/2] STM32 USBPHYC ck_usbo_48m clock provider Amelie Delaunay
2021-03-04 16:04 ` [RESEND PATCH v3 1/2] dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property Amelie Delaunay
2021-03-04 16:04 ` [RESEND PATCH v3 2/2] phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock Amelie Delaunay
@ 2021-03-15 9:57 ` Vinod Koul
2 siblings, 0 replies; 5+ messages in thread
From: Vinod Koul @ 2021-03-15 9:57 UTC (permalink / raw)
To: Amelie Delaunay
Cc: Kishon Vijay Abraham I, Rob Herring, Alexandre Torgue,
Maxime Coquelin, linux-kernel, devicetree, linux-arm-kernel,
linux-stm32
On 04-03-21, 17:04, Amelie Delaunay wrote:
> STM32 USBPHYC provides clocks to STM32 RCC pour STM32 USB controllers.
> Specifically, ck_usbo_48m is a possible clock parent for USB OTG clock,
> during OTG Full-Speed operation.
>
> This series registers the usbphyc as clock provider of this ck_usbo_48m clock.
Applied, thanks
--
~Vinod
^ permalink raw reply [flat|nested] 5+ messages in thread
* [RESEND PATCH v3 2/2] phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock
2021-03-09 8:26 Amelie Delaunay
@ 2021-03-09 8:26 ` Amelie Delaunay
0 siblings, 0 replies; 5+ messages in thread
From: Amelie Delaunay @ 2021-03-09 8:26 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Alexandre Torgue, Maxime Coquelin
Cc: linux-phy, linux-kernel, devicetree, linux-arm-kernel,
linux-stm32, Amelie Delaunay
ck_usbo_48m is generated by usbphyc PLL and used by OTG controller
for Full-Speed use cases with dedicated Full-Speed transceiver.
ck_usbo_48m is available as soon as the PLL is enabled.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
---
No changes in v3.
Changes in v2:
- fix COMMON_CLK dependency issue reported by kernel test robot
---
drivers/phy/st/Kconfig | 1 +
drivers/phy/st/phy-stm32-usbphyc.c | 65 ++++++++++++++++++++++++++++++
2 files changed, 66 insertions(+)
diff --git a/drivers/phy/st/Kconfig b/drivers/phy/st/Kconfig
index b32f44ff9033..3fc3d0781fb8 100644
--- a/drivers/phy/st/Kconfig
+++ b/drivers/phy/st/Kconfig
@@ -36,6 +36,7 @@ config PHY_STIH407_USB
config PHY_STM32_USBPHYC
tristate "STMicroelectronics STM32 USB HS PHY Controller driver"
depends on ARCH_STM32 || COMPILE_TEST
+ depends on COMMON_CLK
select GENERIC_PHY
help
Enable this to support the High-Speed USB transceivers that are part
diff --git a/drivers/phy/st/phy-stm32-usbphyc.c b/drivers/phy/st/phy-stm32-usbphyc.c
index d08fbb180e43..c184f4e34584 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -7,6 +7,7 @@
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
@@ -70,6 +71,7 @@ struct stm32_usbphyc {
struct regulator *vdda1v1;
struct regulator *vdda1v8;
atomic_t n_pll_cons;
+ struct clk_hw clk48_hw;
int switch_setup;
};
@@ -295,6 +297,61 @@ static const struct phy_ops stm32_usbphyc_phy_ops = {
.owner = THIS_MODULE,
};
+static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
+{
+ struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
+
+ return stm32_usbphyc_pll_enable(usbphyc);
+}
+
+static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
+{
+ struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
+
+ stm32_usbphyc_pll_disable(usbphyc);
+}
+
+static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ return 48000000;
+}
+
+static const struct clk_ops usbphyc_clk48_ops = {
+ .prepare = stm32_usbphyc_clk48_prepare,
+ .unprepare = stm32_usbphyc_clk48_unprepare,
+ .recalc_rate = stm32_usbphyc_clk48_recalc_rate,
+};
+
+static void stm32_usbphyc_clk48_unregister(void *data)
+{
+ struct stm32_usbphyc *usbphyc = data;
+
+ of_clk_del_provider(usbphyc->dev->of_node);
+ clk_hw_unregister(&usbphyc->clk48_hw);
+}
+
+static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
+{
+ struct device_node *node = usbphyc->dev->of_node;
+ struct clk_init_data init = { };
+ int ret = 0;
+
+ init.name = "ck_usbo_48m";
+ init.ops = &usbphyc_clk48_ops;
+
+ usbphyc->clk48_hw.init = &init;
+
+ ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
+ if (ret)
+ return ret;
+
+ ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &usbphyc->clk48_hw);
+ if (ret)
+ clk_hw_unregister(&usbphyc->clk48_hw);
+
+ return ret;
+}
+
static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
u32 utmi_switch)
{
@@ -473,6 +530,12 @@ static int stm32_usbphyc_probe(struct platform_device *pdev)
goto clk_disable;
}
+ ret = stm32_usbphyc_clk48_register(usbphyc);
+ if (ret) {
+ dev_err(dev, "failed to register ck_usbo_48m clock: %d\n", ret);
+ goto clk_disable;
+ }
+
version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
dev_info(dev, "registered rev:%lu.%lu\n",
FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
@@ -497,6 +560,8 @@ static int stm32_usbphyc_remove(struct platform_device *pdev)
if (usbphyc->phys[port]->active)
stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
+ stm32_usbphyc_clk48_unregister(usbphyc);
+
clk_disable_unprepare(usbphyc->clk);
return 0;
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-03-15 9:58 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-04 16:04 [RESEND PATCH v3 0/2] STM32 USBPHYC ck_usbo_48m clock provider Amelie Delaunay
2021-03-04 16:04 ` [RESEND PATCH v3 1/2] dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property Amelie Delaunay
2021-03-04 16:04 ` [RESEND PATCH v3 2/2] phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock Amelie Delaunay
2021-03-15 9:57 ` [RESEND PATCH v3 0/2] STM32 USBPHYC ck_usbo_48m clock provider Vinod Koul
2021-03-09 8:26 Amelie Delaunay
2021-03-09 8:26 ` [RESEND PATCH v3 2/2] phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock Amelie Delaunay
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).