From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
Evan Green <evgreen@chromium.org>, Tomasz Figa <tfiga@google.com>,
Tomasz Figa <tfiga@chromium.org>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<iommu@lists.linux-foundation.org>, <yong.wu@mediatek.com>,
<youlin.pei@mediatek.com>,
Nicolas Boichat <drinkcat@chromium.org>, <anan.sun@mediatek.com>,
<chao.hao@mediatek.com>
Subject: [PATCH v2 28/29] iommu/mediatek: Backup/restore regsiters for multi banks
Date: Fri, 13 Aug 2021 14:53:23 +0800 [thread overview]
Message-ID: <20210813065324.29220-29-yong.wu@mediatek.com> (raw)
In-Reply-To: <20210813065324.29220-1-yong.wu@mediatek.com>
Each bank has some independent registers. thus backup/restore them for
each a bank when suspend and resume.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 39 +++++++++++++++++++++++++++------------
drivers/iommu/mtk_iommu.h | 14 +++++++++++---
2 files changed, 38 insertions(+), 15 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 142ee8f3a560..3d474eedce3e 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -1135,16 +1135,23 @@ static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev)
{
struct mtk_iommu_data *data = dev_get_drvdata(dev);
struct mtk_iommu_suspend_reg *reg = &data->reg;
- void __iomem *base = data->bank[0].base;
+ void __iomem *base;
+ int i = 0;
+ base = data->bank[i].base;
reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL);
reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
- reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
- reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
- reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR);
reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG);
+ do {
+ if (!data->plat_data->bank_enable[i])
+ continue;
+ base = data->bank[i].base;
+ reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0);
+ reg->int_main_control[i] = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
+ reg->ivrp_paddr[i] = readl_relaxed(base + REG_MMU_IVRP_PADDR);
+ } while (++i < data->plat_data->bank_nr);
clk_disable_unprepare(data->bclk);
return 0;
}
@@ -1153,9 +1160,9 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
{
struct mtk_iommu_data *data = dev_get_drvdata(dev);
struct mtk_iommu_suspend_reg *reg = &data->reg;
- struct mtk_iommu_domain *m4u_dom = data->bank[0].m4u_dom;
- void __iomem *base = data->bank[0].base;
- int ret;
+ struct mtk_iommu_domain *m4u_dom;
+ void __iomem *base;
+ int ret, i = 0;
ret = clk_prepare_enable(data->bclk);
if (ret) {
@@ -1167,18 +1174,26 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
* Uppon first resume, only enable the clk and return, since the values of the
* registers are not yet set.
*/
- if (!m4u_dom)
+ if (!reg->wr_len_ctrl)
return 0;
+ base = data->bank[i].base;
writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL);
writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
- writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
- writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
- writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
- writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR);
+ do {
+ m4u_dom = data->bank[i].m4u_dom;
+ if (!data->plat_data->bank_enable[i] || !m4u_dom)
+ continue;
+ base = data->bank[i].base;
+ writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0);
+ writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL);
+ writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
+ writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
+ base + REG_MMU_PT_BASE_ADDR);
+ } while (++i < data->plat_data->bank_nr);
return 0;
}
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 905d8740dbcf..279c6c3ee56f 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -33,11 +33,19 @@ struct mtk_iommu_suspend_reg {
};
u32 dcm_dis;
u32 ctrl_reg;
- u32 int_control0;
- u32 int_main_control;
- u32 ivrp_paddr;
u32 vld_pa_rng;
u32 wr_len_ctrl;
+ union {
+ struct { /* only for gen1 */
+ u32 int_control0;
+ };
+
+ struct { /* only for gen2 that support multi-banks */
+ u32 int_control[MTK_IOMMU_BANK_MAX];
+ u32 int_main_control[MTK_IOMMU_BANK_MAX];
+ u32 ivrp_paddr[MTK_IOMMU_BANK_MAX];
+ };
+ };
};
enum mtk_iommu_plat {
--
2.18.0
next prev parent reply other threads:[~2021-08-13 6:57 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-13 6:52 [PATCH v2 00/29] MT8195 IOMMU SUPPORT Yong Wu
2021-08-13 6:52 ` [PATCH v2 01/29] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU Yong Wu
2021-08-13 6:52 ` [PATCH v2 02/29] dt-bindings: mediatek: mt8195: Add binding for infra IOMMU Yong Wu
2021-08-17 21:44 ` Rob Herring
2021-08-13 6:52 ` [PATCH v2 03/29] iommu/mediatek: Fix 2 HW sharing pgtable issue Yong Wu
2021-08-13 6:52 ` [PATCH v2 04/29] iommu/mediatek: Adapt sharing and non-sharing pgtable case Yong Wu
2021-08-13 6:53 ` [PATCH v2 05/29] iommu/mediatek: Add 12G~16G support for multi domains Yong Wu
2021-08-13 6:53 ` [PATCH v2 06/29] iommu/mediatek: Add a flag DCM_DISABLE Yong Wu
2021-08-13 6:53 ` [PATCH v2 07/29] iommu/mediatek: Add a flag NON_STD_AXI Yong Wu
2021-08-13 6:53 ` [PATCH v2 08/29] iommu/mediatek: Remove for_each_m4u in tlb_sync_all Yong Wu
2021-08-13 6:53 ` [PATCH v2 09/29] iommu/mediatek: Add tlb_lock in tlb_flush_all Yong Wu
2021-08-13 6:53 ` [PATCH v2 10/29] iommu/mediatek: Remove the granule in the tlb flush Yong Wu
2021-08-13 6:53 ` [PATCH v2 11/29] iommu/mediatek: Always pm_runtime_get while " Yong Wu
2021-08-24 7:10 ` Hsin-Yi Wang
2021-09-01 12:10 ` Yong Wu (吴勇)
2021-09-30 11:26 ` Dafna Hirschfeld
2021-10-07 3:00 ` Yong Wu
2021-08-13 6:53 ` [PATCH v2 12/29] iommu/mediatek: Always enable output PA over 32bits in isr Yong Wu
2021-08-13 6:53 ` [PATCH v2 13/29] iommu/mediatek: Add SUB_COMMON_3BITS flag Yong Wu
2021-08-13 6:53 ` [PATCH v2 14/29] iommu/mediatek: Add IOMMU_TYPE flag Yong Wu
2021-08-13 6:53 ` [PATCH v2 15/29] iommu/mediatek: Contain MM IOMMU flow with the MM TYPE Yong Wu
2021-08-13 6:53 ` [PATCH v2 16/29] iommu/mediatek: Adjust device link when it is sub-common Yong Wu
2021-08-24 7:35 ` Hsin-Yi Wang
2021-09-01 12:01 ` Yong Wu (吴勇)
2021-08-13 6:53 ` [PATCH v2 17/29] iommu/mediatek: Add infra iommu support Yong Wu
2021-08-13 6:53 ` [PATCH v2 18/29] iommu/mediatek: Add PCIe support Yong Wu
2021-08-13 6:53 ` [PATCH v2 19/29] iommu/mediatek: Add mt8195 support Yong Wu
2021-08-13 6:53 ` [PATCH v2 20/29] iommu/mediatek: Only adjust code about register base Yong Wu
2021-08-13 6:53 ` [PATCH v2 21/29] iommu/mediatek: Just move code position in hw_init Yong Wu
2021-08-13 6:53 ` [PATCH v2 22/29] iommu/mediatek: Add mtk_iommu_bank_data structure Yong Wu
2021-08-13 6:53 ` [PATCH v2 23/29] iommu/mediatek: Initialise bank HW for each a bank Yong Wu
2021-08-13 6:53 ` [PATCH v2 24/29] iommu/mediatek: Add bank_nr and bank_enable Yong Wu
2021-08-13 6:53 ` [PATCH v2 25/29] iommu/mediatek: Change the domid to iova_region_id Yong Wu
2021-08-13 6:53 ` [PATCH v2 26/29] iommu/mediatek: Get the proper bankid for multi banks Yong Wu
2021-08-13 6:53 ` [PATCH v2 27/29] iommu/mediatek: Initialise/Remove for multi bank dev Yong Wu
2021-08-13 6:53 ` Yong Wu [this message]
2021-08-13 6:53 ` [PATCH v2 29/29] iommu/mediatek: mt8195: Enable multi banks for infra iommu Yong Wu
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