* [PATCH 1/2] dt-bindings: arm: cpus: Add ARM Cortex-A78
@ 2021-11-12 13:19 Thierry Reding
2021-11-12 13:19 ` [PATCH 2/2] arm64: tegra: Describe Tegra234 CPU hierarchy Thierry Reding
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Thierry Reding @ 2021-11-12 13:19 UTC (permalink / raw)
To: Thierry Reding, Rob Herring
Cc: Robin Murphy, Jon Hunter, devicetree, linux-arm-kernel, linux-tegra
From: Thierry Reding <treding@nvidia.com>
The ARM Cortex-A78 CPU can be found in a number of recent SoCs such as
the NVIDIA Tegra234 (Orin).
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index f2ab6423b4af..452bfd1d4ecc 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -137,6 +137,7 @@ properties:
- arm,cortex-a75
- arm,cortex-a76
- arm,cortex-a77
+ - arm,cortex-a78
- arm,cortex-m0
- arm,cortex-m0+
- arm,cortex-m1
--
2.33.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] arm64: tegra: Describe Tegra234 CPU hierarchy
2021-11-12 13:19 [PATCH 1/2] dt-bindings: arm: cpus: Add ARM Cortex-A78 Thierry Reding
@ 2021-11-12 13:19 ` Thierry Reding
2021-11-29 21:06 ` Rob Herring
2021-11-12 13:39 ` [PATCH 1/2] dt-bindings: arm: cpus: Add ARM Cortex-A78 Robin Murphy
2021-11-29 21:06 ` Rob Herring
2 siblings, 1 reply; 7+ messages in thread
From: Thierry Reding @ 2021-11-12 13:19 UTC (permalink / raw)
To: Thierry Reding, Rob Herring
Cc: Robin Murphy, Jon Hunter, devicetree, linux-arm-kernel, linux-tegra
From: Thierry Reding <treding@nvidia.com>
The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each,
for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches
with each cluster having an additional 256 KiB unified L2 cache and a 2
MiB L3 cache.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 365 ++++++++++++++++++++++-
1 file changed, 363 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 104e5fdd5f8a..db24f48edc9f 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -736,12 +736,373 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0_0: cpu@0 {
+ compatible = "arm,cortex-a78";
device_type = "cpu";
- reg = <0x000>;
+ reg = <0x00000>;
enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c0_0>;
+ };
+
+ cpu0_1: cpu@100 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ reg = <0x00100>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c0_1>;
+ };
+
+ cpu0_2: cpu@200 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ reg = <0x00200>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c0_2>;
+ };
+
+ cpu0_3: cpu@300 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ reg = <0x00300>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c0_3>;
+ };
+
+ cpu1_0: cpu@10000 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ reg = <0x10000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c1_0>;
+ };
+
+ cpu1_1: cpu@10100 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ reg = <0x10100>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c1_1>;
+ };
+
+ cpu1_2: cpu@10200 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ reg = <0x10200>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c1_2>;
+ };
+
+ cpu1_3: cpu@10300 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ reg = <0x10300>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c1_3>;
+ };
+
+ cpu2_0: cpu@20000 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ reg = <0x20000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c2_0>;
+ };
+
+ cpu2_1: cpu@20100 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ reg = <0x20100>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c2_1>;
+ };
+
+ cpu2_2: cpu@20200 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ reg = <0x20200>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c2_2>;
+ };
+
+ cpu2_3: cpu@20300 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ reg = <0x20300>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c2_3>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0_0>;
+ };
+
+ core1 {
+ cpu = <&cpu0_1>;
+ };
+
+ core2 {
+ cpu = <&cpu0_2>;
+ };
+
+ core3 {
+ cpu = <&cpu0_3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu1_0>;
+ };
+
+ core1 {
+ cpu = <&cpu1_1>;
+ };
+
+ core2 {
+ cpu = <&cpu1_2>;
+ };
+
+ core3 {
+ cpu = <&cpu1_3>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&cpu2_0>;
+ };
+
+ core1 {
+ cpu = <&cpu2_1>;
+ };
+
+ core2 {
+ cpu = <&cpu2_2>;
+ };
+
+ core3 {
+ cpu = <&cpu2_3>;
+ };
+ };
+ };
+
+ l2c0_0: l2-cache00 {
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-unified;
+ next-level-cache = <&l3c0>;
+ };
+
+ l2c0_1: l2-cache01 {
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-unified;
+ next-level-cache = <&l3c0>;
};
+
+ l2c0_2: l2-cache02 {
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-unified;
+ next-level-cache = <&l3c0>;
+ };
+
+ l2c0_3: l2-cache03 {
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-unified;
+ next-level-cache = <&l3c0>;
+ };
+
+ l2c1_0: l2-cache10 {
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-unified;
+ next-level-cache = <&l3c1>;
+ };
+
+ l2c1_1: l2-cache11 {
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-unified;
+ next-level-cache = <&l3c1>;
+ };
+
+ l2c1_2: l2-cache12 {
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-unified;
+ next-level-cache = <&l3c1>;
+ };
+
+ l2c1_3: l2-cache13 {
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-unified;
+ next-level-cache = <&l3c1>;
+ };
+
+ l2c2_0: l2-cache20 {
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-unified;
+ next-level-cache = <&l3c2>;
+ };
+
+ l2c2_1: l2-cache21 {
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-unified;
+ next-level-cache = <&l3c2>;
+ };
+
+ l2c2_2: l2-cache22 {
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-unified;
+ next-level-cache = <&l3c2>;
+ };
+
+ l2c2_3: l2-cache23 {
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-unified;
+ next-level-cache = <&l3c2>;
+ };
+
+ l3c0: l3-cache0 {
+ cache-size = <2097152>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ };
+
+ l3c1: l3-cache1 {
+ cache-size = <2097152>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ };
+
+ l3c2: l3-cache2 {
+ cache-size = <2097152>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ status = "okay";
};
psci {
--
2.33.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] dt-bindings: arm: cpus: Add ARM Cortex-A78
2021-11-12 13:19 [PATCH 1/2] dt-bindings: arm: cpus: Add ARM Cortex-A78 Thierry Reding
2021-11-12 13:19 ` [PATCH 2/2] arm64: tegra: Describe Tegra234 CPU hierarchy Thierry Reding
@ 2021-11-12 13:39 ` Robin Murphy
2021-11-29 21:06 ` Rob Herring
2 siblings, 0 replies; 7+ messages in thread
From: Robin Murphy @ 2021-11-12 13:39 UTC (permalink / raw)
To: Thierry Reding, Rob Herring
Cc: Jon Hunter, devicetree, linux-arm-kernel, linux-tegra
On 12/11/2021 1:19 pm, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> The ARM Cortex-A78 CPU can be found in a number of recent SoCs such as
> the NVIDIA Tegra234 (Orin).
Oops, that reminds me that I'm sitting on a patch somewhere to bring
these fully up-to-date (I got sidetracked pondering what to do about PMU
naming). I should track that down and post it next week...
However if Rob feels like applying this one first,
Acked-by: Robin Murphy <robin.muephy@arm.com>
Cheers,
Robin.
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
> index f2ab6423b4af..452bfd1d4ecc 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.yaml
> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
> @@ -137,6 +137,7 @@ properties:
> - arm,cortex-a75
> - arm,cortex-a76
> - arm,cortex-a77
> + - arm,cortex-a78
> - arm,cortex-m0
> - arm,cortex-m0+
> - arm,cortex-m1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] arm64: tegra: Describe Tegra234 CPU hierarchy
2021-11-12 13:19 ` [PATCH 2/2] arm64: tegra: Describe Tegra234 CPU hierarchy Thierry Reding
@ 2021-11-29 21:06 ` Rob Herring
2021-11-29 22:53 ` Robin Murphy
0 siblings, 1 reply; 7+ messages in thread
From: Rob Herring @ 2021-11-29 21:06 UTC (permalink / raw)
To: Thierry Reding
Cc: Robin Murphy, Jon Hunter, devicetree, linux-arm-kernel, linux-tegra
On Fri, Nov 12, 2021 at 02:19:04PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each,
> for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches
> with each cluster having an additional 256 KiB unified L2 cache and a 2
> MiB L3 cache.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 365 ++++++++++++++++++++++-
> 1 file changed, 363 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> index 104e5fdd5f8a..db24f48edc9f 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> @@ -736,12 +736,373 @@ cpus {
> #address-cells = <1>;
> #size-cells = <0>;
>
> - cpu@0 {
> + cpu0_0: cpu@0 {
> + compatible = "arm,cortex-a78";
> device_type = "cpu";
> - reg = <0x000>;
> + reg = <0x00000>;
>
> enable-method = "psci";
> +
> + i-cache-size = <65536>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <65536>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
Isn't all this discoverable?
> + next-level-cache = <&l2c0_0>;
> + };
> +
> + cpu0_1: cpu@100 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + reg = <0x00100>;
> +
> + enable-method = "psci";
> +
> + i-cache-size = <65536>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <65536>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2c0_1>;
> + };
> +
> + cpu0_2: cpu@200 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + reg = <0x00200>;
> +
> + enable-method = "psci";
> +
> + i-cache-size = <65536>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <65536>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2c0_2>;
> + };
> +
> + cpu0_3: cpu@300 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + reg = <0x00300>;
> +
> + enable-method = "psci";
> +
> + i-cache-size = <65536>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <65536>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2c0_3>;
> + };
> +
> + cpu1_0: cpu@10000 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + reg = <0x10000>;
> +
> + enable-method = "psci";
> +
> + i-cache-size = <65536>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <65536>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2c1_0>;
> + };
> +
> + cpu1_1: cpu@10100 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + reg = <0x10100>;
> +
> + enable-method = "psci";
> +
> + i-cache-size = <65536>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <65536>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2c1_1>;
> + };
> +
> + cpu1_2: cpu@10200 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + reg = <0x10200>;
> +
> + enable-method = "psci";
> +
> + i-cache-size = <65536>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <65536>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2c1_2>;
> + };
> +
> + cpu1_3: cpu@10300 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + reg = <0x10300>;
> +
> + enable-method = "psci";
> +
> + i-cache-size = <65536>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <65536>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2c1_3>;
> + };
> +
> + cpu2_0: cpu@20000 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + reg = <0x20000>;
> +
> + enable-method = "psci";
> +
> + i-cache-size = <65536>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <65536>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2c2_0>;
> + };
> +
> + cpu2_1: cpu@20100 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + reg = <0x20100>;
> +
> + enable-method = "psci";
> +
> + i-cache-size = <65536>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <65536>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2c2_1>;
> + };
> +
> + cpu2_2: cpu@20200 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + reg = <0x20200>;
> +
> + enable-method = "psci";
> +
> + i-cache-size = <65536>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <65536>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2c2_2>;
> + };
> +
> + cpu2_3: cpu@20300 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + reg = <0x20300>;
> +
> + enable-method = "psci";
> +
> + i-cache-size = <65536>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <65536>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2c2_3>;
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0_0>;
> + };
> +
> + core1 {
> + cpu = <&cpu0_1>;
> + };
> +
> + core2 {
> + cpu = <&cpu0_2>;
> + };
> +
> + core3 {
> + cpu = <&cpu0_3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu1_0>;
> + };
> +
> + core1 {
> + cpu = <&cpu1_1>;
> + };
> +
> + core2 {
> + cpu = <&cpu1_2>;
> + };
> +
> + core3 {
> + cpu = <&cpu1_3>;
> + };
> + };
> +
> + cluster2 {
> + core0 {
> + cpu = <&cpu2_0>;
> + };
> +
> + core1 {
> + cpu = <&cpu2_1>;
> + };
> +
> + core2 {
> + cpu = <&cpu2_2>;
> + };
> +
> + core3 {
> + cpu = <&cpu2_3>;
> + };
> + };
> + };
> +
> + l2c0_0: l2-cache00 {
> + cache-size = <262144>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + cache-unified;
> + next-level-cache = <&l3c0>;
> + };
> +
> + l2c0_1: l2-cache01 {
> + cache-size = <262144>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + cache-unified;
> + next-level-cache = <&l3c0>;
> };
> +
> + l2c0_2: l2-cache02 {
> + cache-size = <262144>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + cache-unified;
> + next-level-cache = <&l3c0>;
> + };
> +
> + l2c0_3: l2-cache03 {
> + cache-size = <262144>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + cache-unified;
> + next-level-cache = <&l3c0>;
> + };
> +
> + l2c1_0: l2-cache10 {
> + cache-size = <262144>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + cache-unified;
> + next-level-cache = <&l3c1>;
> + };
> +
> + l2c1_1: l2-cache11 {
> + cache-size = <262144>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + cache-unified;
> + next-level-cache = <&l3c1>;
> + };
> +
> + l2c1_2: l2-cache12 {
> + cache-size = <262144>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + cache-unified;
> + next-level-cache = <&l3c1>;
> + };
> +
> + l2c1_3: l2-cache13 {
> + cache-size = <262144>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + cache-unified;
> + next-level-cache = <&l3c1>;
> + };
> +
> + l2c2_0: l2-cache20 {
> + cache-size = <262144>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + cache-unified;
> + next-level-cache = <&l3c2>;
> + };
> +
> + l2c2_1: l2-cache21 {
> + cache-size = <262144>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + cache-unified;
> + next-level-cache = <&l3c2>;
> + };
> +
> + l2c2_2: l2-cache22 {
> + cache-size = <262144>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + cache-unified;
> + next-level-cache = <&l3c2>;
> + };
> +
> + l2c2_3: l2-cache23 {
> + cache-size = <262144>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + cache-unified;
> + next-level-cache = <&l3c2>;
> + };
> +
> + l3c0: l3-cache0 {
> + cache-size = <2097152>;
> + cache-line-size = <64>;
> + cache-sets = <2048>;
> + };
> +
> + l3c1: l3-cache1 {
> + cache-size = <2097152>;
> + cache-line-size = <64>;
> + cache-sets = <2048>;
> + };
> +
> + l3c2: l3-cache2 {
> + cache-size = <2097152>;
> + cache-line-size = <64>;
> + cache-sets = <2048>;
> + };
> + };
> +
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + status = "okay";
That's the default.
> };
>
> psci {
> --
> 2.33.1
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] dt-bindings: arm: cpus: Add ARM Cortex-A78
2021-11-12 13:19 [PATCH 1/2] dt-bindings: arm: cpus: Add ARM Cortex-A78 Thierry Reding
2021-11-12 13:19 ` [PATCH 2/2] arm64: tegra: Describe Tegra234 CPU hierarchy Thierry Reding
2021-11-12 13:39 ` [PATCH 1/2] dt-bindings: arm: cpus: Add ARM Cortex-A78 Robin Murphy
@ 2021-11-29 21:06 ` Rob Herring
2 siblings, 0 replies; 7+ messages in thread
From: Rob Herring @ 2021-11-29 21:06 UTC (permalink / raw)
To: Thierry Reding
Cc: Robin Murphy, linux-tegra, Rob Herring, linux-arm-kernel,
devicetree, Jon Hunter
On Fri, 12 Nov 2021 14:19:03 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> The ARM Cortex-A78 CPU can be found in a number of recent SoCs such as
> the NVIDIA Tegra234 (Orin).
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Applied, thanks!
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] arm64: tegra: Describe Tegra234 CPU hierarchy
2021-11-29 21:06 ` Rob Herring
@ 2021-11-29 22:53 ` Robin Murphy
2021-12-14 12:27 ` Thierry Reding
0 siblings, 1 reply; 7+ messages in thread
From: Robin Murphy @ 2021-11-29 22:53 UTC (permalink / raw)
To: Rob Herring, Thierry Reding
Cc: Jon Hunter, devicetree, linux-arm-kernel, linux-tegra,
Mark Rutland, Will Deacon
On 2021-11-29 21:06, Rob Herring wrote:
> On Fri, Nov 12, 2021 at 02:19:04PM +0100, Thierry Reding wrote:
>> From: Thierry Reding <treding@nvidia.com>
>>
>> The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each,
>> for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches
>> with each cluster having an additional 256 KiB unified L2 cache and a 2
>> MiB L3 cache.
>>
>> Signed-off-by: Thierry Reding <treding@nvidia.com>
>> ---
>> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 365 ++++++++++++++++++++++-
>> 1 file changed, 363 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
>> index 104e5fdd5f8a..db24f48edc9f 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
>> +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
>> @@ -736,12 +736,373 @@ cpus {
>> #address-cells = <1>;
>> #size-cells = <0>;
>>
>> - cpu@0 {
>> + cpu0_0: cpu@0 {
>> + compatible = "arm,cortex-a78";
>> device_type = "cpu";
>> - reg = <0x000>;
>> + reg = <0x00000>;
>>
>> enable-method = "psci";
>> +
>
>> + i-cache-size = <65536>;
>> + i-cache-line-size = <64>;
>> + i-cache-sets = <256>;
>> + d-cache-size = <65536>;
>> + d-cache-line-size = <64>;
>> + d-cache-sets = <256>;
>
> Isn't all this discoverable?
No. The required parameters for cache maintenance by set/way are
discoverable from the CTR, and if you're particularly lucky they might
even happen to reflect the underlying physical cache structures, but
there's absolutely no guarantee of that, and there definitely exist
cases where they don't.
[...]
>> + pmu {
>> + compatible = "arm,armv8-pmuv3";
Oh, I'd missed this - per the current state of things, we should really
have a proper compatible for the PMU as well.
(Suggestions for ways to improve the current state of things for better
forward- and backward- compatibility welcome - I started having a mad
idea about autogenerating a PMU name from the CPU compatible if the
generic PMU compatible is present, but I'm not sure that's realistic).
Robin.
>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "okay";
>
> That's the default.
>
>> };
>>
>> psci {
>> --
>> 2.33.1
>>
>>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] arm64: tegra: Describe Tegra234 CPU hierarchy
2021-11-29 22:53 ` Robin Murphy
@ 2021-12-14 12:27 ` Thierry Reding
0 siblings, 0 replies; 7+ messages in thread
From: Thierry Reding @ 2021-12-14 12:27 UTC (permalink / raw)
To: Robin Murphy
Cc: Rob Herring, Jon Hunter, devicetree, linux-arm-kernel,
linux-tegra, Mark Rutland, Will Deacon
[-- Attachment #1: Type: text/plain, Size: 2170 bytes --]
On Mon, Nov 29, 2021 at 10:53:37PM +0000, Robin Murphy wrote:
> On 2021-11-29 21:06, Rob Herring wrote:
> > On Fri, Nov 12, 2021 at 02:19:04PM +0100, Thierry Reding wrote:
> > > From: Thierry Reding <treding@nvidia.com>
> > >
> > > The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each,
> > > for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches
> > > with each cluster having an additional 256 KiB unified L2 cache and a 2
> > > MiB L3 cache.
> > >
> > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > ---
> > > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 365 ++++++++++++++++++++++-
> > > 1 file changed, 363 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> > > index 104e5fdd5f8a..db24f48edc9f 100644
> > > --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> > > +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> > > @@ -736,12 +736,373 @@ cpus {
> > > #address-cells = <1>;
> > > #size-cells = <0>;
> > > - cpu@0 {
> > > + cpu0_0: cpu@0 {
> > > + compatible = "arm,cortex-a78";
> > > device_type = "cpu";
> > > - reg = <0x000>;
> > > + reg = <0x00000>;
> > > enable-method = "psci";
> > > +
> >
> > > + i-cache-size = <65536>;
> > > + i-cache-line-size = <64>;
> > > + i-cache-sets = <256>;
> > > + d-cache-size = <65536>;
> > > + d-cache-line-size = <64>;
> > > + d-cache-sets = <256>;
> >
> > Isn't all this discoverable?
>
> No. The required parameters for cache maintenance by set/way are
> discoverable from the CTR, and if you're particularly lucky they might even
> happen to reflect the underlying physical cache structures, but there's
> absolutely no guarantee of that, and there definitely exist cases where they
> don't.
>
> [...]
> > > + pmu {
> > > + compatible = "arm,armv8-pmuv3";
>
> Oh, I'd missed this - per the current state of things, we should really have
> a proper compatible for the PMU as well.
Good catch! I've changed this to arm,cortex-a78-pmu since that's what
Tegra234 has.
Thanks,
Thierry
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-12-14 12:27 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-12 13:19 [PATCH 1/2] dt-bindings: arm: cpus: Add ARM Cortex-A78 Thierry Reding
2021-11-12 13:19 ` [PATCH 2/2] arm64: tegra: Describe Tegra234 CPU hierarchy Thierry Reding
2021-11-29 21:06 ` Rob Herring
2021-11-29 22:53 ` Robin Murphy
2021-12-14 12:27 ` Thierry Reding
2021-11-12 13:39 ` [PATCH 1/2] dt-bindings: arm: cpus: Add ARM Cortex-A78 Robin Murphy
2021-11-29 21:06 ` Rob Herring
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