From: Shawn Guo <shawn.guo@linaro.org>
To: Marc Zyngier <maz@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Maulik Shah <quic_mkshah@quicinc.com>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Loic Poulain <loic.poulain@linaro.org>,
devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] irqchip: Add Qualcomm MPM controller driver
Date: Tue, 30 Nov 2021 17:17:08 +0800 [thread overview]
Message-ID: <20211130091708.GH10105@dragon> (raw)
In-Reply-To: <87lf16m3ua.wl-maz@kernel.org>
On Tue, Nov 30, 2021 at 08:42:53AM +0000, Marc Zyngier wrote:
> On Tue, 30 Nov 2021 02:31:52 +0000,
> Shawn Guo <shawn.guo@linaro.org> wrote:
> >
> > + Maulik
> >
> > On Mon, Nov 29, 2021 at 03:24:39PM +0000, Marc Zyngier wrote:
> > [...]
> > > > > > @@ -430,6 +430,14 @@ config QCOM_PDC
> > > > > > Power Domain Controller driver to manage and configure wakeup
> > > > > > IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
> > > > > >
> > > > > > +config QCOM_MPM
> > > > > > + bool "QCOM MPM"
> > > > >
> > > > > Can't be built as a module?
> > > >
> > > > The driver is implemented as a builtin_platform_driver().
> > >
> > > This, on its own, shouldn't preclude the driver from being built as a
> > > module. However, the config option only allows it to be built in. Why?
> >
> > I just tried to build it as a module, and it seems that "irq_to_desc" is
> > only available for built-in build.
>
> Yet another thing that you should not be using. The irqdomain code
> gives you everything you need without having to resort to the
> internals of the core IRQ infrastructure.
I see. I should use irq_get_irq_data() rather than &desc->irq_data.
>
> > > Furthermore, why would you look up anywhere other than the wake-up
> > > domain? My impression was that only these interrupts would require
> > > being re-triggered.
> >
> > Both domains have MPM pins that could wake up system.
>
> Then why do you need two domains?
This is basically the same situation as qcom-pdc, and I have some
description about that in the commit log:
- For given SoC, a fixed number of MPM pins are supported, e.g. 96 pins
on QCM2290. Each of these MPM pins can be either a MPM_GIC pin or
a MPM_GPIO pin. The mapping between MPM_GIC pin and GIC interrupt
is defined by SoC, as well as the mapping between MPM_GPIO pin and
GPIO number. The former mapping can be found as the SoC data in this
MPM driver, while the latter can be found as the msm_gpio_wakeirq_map[]
in TLMM driver.
- Two irq domains are created for a single irq_chip to handle MPM_GIC
and MPM_GPIO pins respectively, i.e. MPM_GIC domain and MPM_GPIO domain.
The former is a child domain of GIC irq domain, while the latter is
a parent domain of TLMM/GPIO irq domain.
Shawn
next prev parent reply other threads:[~2021-11-30 9:17 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-26 9:35 [PATCH v2 0/2] Add Qualcomm MPM irqchip driver support Shawn Guo
2021-11-26 9:35 ` [PATCH v2 1/2] dt-bindings: interrupt-controller: Add Qualcomm MPM support Shawn Guo
2021-12-01 23:02 ` Rob Herring
2021-11-26 9:35 ` [PATCH v2 2/2] irqchip: Add Qualcomm MPM controller driver Shawn Guo
2021-11-26 15:13 ` Marc Zyngier
2021-11-26 19:19 ` Marc Zyngier
2021-11-29 13:33 ` Shawn Guo
2021-11-29 15:24 ` Marc Zyngier
2021-11-30 2:31 ` Shawn Guo
2021-11-30 8:42 ` Marc Zyngier
2021-11-30 9:17 ` Shawn Guo [this message]
2021-11-30 10:44 ` Marc Zyngier
2021-12-01 7:36 ` Shawn Guo
[not found] ` <2e821841-a921-3fda-9ee6-3d5127653033@quicinc.com>
2021-11-30 8:31 ` Shawn Guo
2021-11-30 8:52 ` Marc Zyngier
2021-11-30 8:54 ` Maulik Shah
2021-11-30 8:47 ` Marc Zyngier
2021-11-27 7:49 ` kernel test robot
2021-11-29 7:23 ` Maulik Shah
2021-11-29 13:45 ` Shawn Guo
2021-11-30 8:26 ` Maulik Shah
2021-11-30 8:44 ` Shawn Guo
2021-11-30 9:04 ` Maulik Shah
2021-11-30 9:26 ` Shawn Guo
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