* [PATCH v3 0/4] Add ARTPEC-8 support to DWMMC controller
@ 2021-12-09 16:45 Mårten Lindahl
2021-12-09 16:45 ` [PATCH v3 1/4] dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8 Mårten Lindahl
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Mårten Lindahl @ 2021-12-09 16:45 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Jaehoon Chung
Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel,
linux-samsung-soc, Mårten Lindahl
Hi!
The ARTPEC-8 SoC has a DWMMC controller that is compatible with the
Exynos 7 version v2.70a. The main differences from Exynos 7 is that it
does not support HS400 and has an extended data read timeout. To run
this controller we need to add compatibility for ARTPEC-8, because we
need to separate the configuration of the TMOUT register from the non
ARTPEC-8 versions.
This patchset is dependent on 2 changes that has been added to the mmc
git next branch, but has not yet been merged to mainline:
Patch 2 of this patchset depends on commit 0e6f2c4c2072b ("mmc: dw_mmc:
add common capabilities to replace caps").
Patch 3 of this patchset depends on commit d5bc33487eab3 ("mmc: dw_mmc:
Allow lower TMOUT value than maximum").
Kind regards
Mårten Lindahl
Changes in v2:
- Change compatible string vendor prefix
- Removed unnecessary comment
- Change 1<<0 to BIT(0)
Changes in v3:
- Add callback for implementation specific control of data timeout
- Add callback for implementation specific read of cycle count for
data timeout.
- Move definition of DW_MMC_QUIRK_EXTENDED_TMOUT from patch 3/4 to
patch 4/4.
Mårten Lindahl (4):
dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8
mmc: dw_mmc-exynos: Add support for ARTPEC-8
mmc: dw_mmc: Add driver callbacks for data read timeout
mmc: dw_mmc: Do not wait for DTO in case of error
.../bindings/mmc/exynos-dw-mshc.txt | 2 +
drivers/mmc/host/dw_mmc-exynos.c | 101 ++++++++++++++++--
drivers/mmc/host/dw_mmc.c | 21 +++-
drivers/mmc/host/dw_mmc.h | 10 ++
4 files changed, 122 insertions(+), 12 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 1/4] dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8
2021-12-09 16:45 [PATCH v3 0/4] Add ARTPEC-8 support to DWMMC controller Mårten Lindahl
@ 2021-12-09 16:45 ` Mårten Lindahl
2021-12-09 18:27 ` Krzysztof Kozlowski
2021-12-09 16:45 ` [PATCH v3 2/4] mmc: dw_mmc-exynos: " Mårten Lindahl
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Mårten Lindahl @ 2021-12-09 16:45 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Jaehoon Chung
Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel,
linux-samsung-soc, Mårten Lindahl
The ARTPEC-8 SoC has a DWMMC controller that is compatible with the
Exynos 7 version v2.70a. The main differences from Exynos 7 is that it
does not support HS400 and has extended data read timeout.
Add compatibility string "axis,artpec8-dw-mshc" for ARTPEC-8.
Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com>
---
v2:
- Change compatible string vendor prefix
Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 0419a63f73a0..753e9d7d8956 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -22,6 +22,8 @@ Required Properties:
specific extensions.
- "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
specific extensions having an SMU.
+ - "axis,artpec8-dw-mshc": for controllers with ARTPEC-8 specific
+ extensions.
* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
--
2.20.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 2/4] mmc: dw_mmc-exynos: Add support for ARTPEC-8
2021-12-09 16:45 [PATCH v3 0/4] Add ARTPEC-8 support to DWMMC controller Mårten Lindahl
2021-12-09 16:45 ` [PATCH v3 1/4] dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8 Mårten Lindahl
@ 2021-12-09 16:45 ` Mårten Lindahl
2021-12-09 18:28 ` Krzysztof Kozlowski
2021-12-09 16:45 ` [PATCH v3 3/4] mmc: dw_mmc: Add driver callbacks for data read timeout Mårten Lindahl
2021-12-09 16:45 ` [PATCH v3 4/4] mmc: dw_mmc: Do not wait for DTO in case of error Mårten Lindahl
3 siblings, 1 reply; 9+ messages in thread
From: Mårten Lindahl @ 2021-12-09 16:45 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Jaehoon Chung
Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel,
linux-samsung-soc, Mårten Lindahl
The ARTPEC-8 SoC has a DWMMC controller that is compatible with the
Exynos 7 version v2.70a. The main differences from Exynos 7 is that it
does not support HS400 and has extended data read timeout.
This patch adds compatibility string "axis,artpec8-dw-mshc" for
ARTPEC-8, and DW_MCI_TYPE_ARTPEC8 is added to the dw_mci_exynos_type.
Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com>
---
v2:
- Change compatible string vendor prefix
drivers/mmc/host/dw_mmc-exynos.c | 47 ++++++++++++++++++++++++--------
1 file changed, 36 insertions(+), 11 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index f76eeeb0cc53..86486e6659de 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -28,6 +28,7 @@ enum dw_mci_exynos_type {
DW_MCI_TYPE_EXYNOS5420_SMU,
DW_MCI_TYPE_EXYNOS7,
DW_MCI_TYPE_EXYNOS7_SMU,
+ DW_MCI_TYPE_ARTPEC8,
};
/* Exynos implementation specific driver private data */
@@ -69,6 +70,9 @@ static struct dw_mci_exynos_compatible {
}, {
.compatible = "samsung,exynos7-dw-mshc-smu",
.ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU,
+ }, {
+ .compatible = "axis,artpec8-dw-mshc",
+ .ctrl_type = DW_MCI_TYPE_ARTPEC8,
},
};
@@ -81,7 +85,8 @@ static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host)
else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
return EXYNOS4210_FIXED_CIU_CLK_DIV;
else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
- priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
+ priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
+ priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1;
else
return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1;
@@ -133,7 +138,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
u32 clksel;
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
- priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
+ priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
+ priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
clksel = mci_readl(host, CLKSEL64);
else
clksel = mci_readl(host, CLKSEL);
@@ -141,7 +147,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing;
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
- priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
+ priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
+ priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
mci_writel(host, CLKSEL64, clksel);
else
mci_writel(host, CLKSEL, clksel);
@@ -210,14 +217,16 @@ static int dw_mci_exynos_resume_noirq(struct device *dev)
return ret;
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
- priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
+ priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
+ priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
clksel = mci_readl(host, CLKSEL64);
else
clksel = mci_readl(host, CLKSEL);
if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
- priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
+ priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
+ priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
mci_writel(host, CLKSEL64, clksel);
else
mci_writel(host, CLKSEL, clksel);
@@ -238,7 +247,8 @@ static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
* Not supported to configure register
* related to HS400
*/
- if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) {
+ if ((priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) ||
+ (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)) {
if (timing == MMC_TIMING_MMC_HS400)
dev_warn(host->dev,
"cannot configure HS400, unsupported chipset\n");
@@ -394,7 +404,8 @@ static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
struct dw_mci_exynos_priv_data *priv = host->priv;
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
- priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
+ priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
+ priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
else
return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
@@ -406,13 +417,15 @@ static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
struct dw_mci_exynos_priv_data *priv = host->priv;
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
- priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
+ priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
+ priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
clksel = mci_readl(host, CLKSEL64);
else
clksel = mci_readl(host, CLKSEL);
clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
- priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
+ priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
+ priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
mci_writel(host, CLKSEL64, clksel);
else
mci_writel(host, CLKSEL, clksel);
@@ -425,7 +438,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
u8 sample;
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
- priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
+ priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
+ priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
clksel = mci_readl(host, CLKSEL64);
else
clksel = mci_readl(host, CLKSEL);
@@ -434,7 +448,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
- priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
+ priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
+ priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
mci_writel(host, CLKSEL64, clksel);
else
mci_writel(host, CLKSEL, clksel);
@@ -543,6 +558,14 @@ static const struct dw_mci_drv_data exynos_drv_data = {
.prepare_hs400_tuning = dw_mci_exynos_prepare_hs400_tuning,
};
+static const struct dw_mci_drv_data artpec_drv_data = {
+ .common_caps = MMC_CAP_CMD23,
+ .init = dw_mci_exynos_priv_init,
+ .set_ios = dw_mci_exynos_set_ios,
+ .parse_dt = dw_mci_exynos_parse_dt,
+ .execute_tuning = dw_mci_exynos_execute_tuning,
+};
+
static const struct of_device_id dw_mci_exynos_match[] = {
{ .compatible = "samsung,exynos4412-dw-mshc",
.data = &exynos_drv_data, },
@@ -556,6 +579,8 @@ static const struct of_device_id dw_mci_exynos_match[] = {
.data = &exynos_drv_data, },
{ .compatible = "samsung,exynos7-dw-mshc-smu",
.data = &exynos_drv_data, },
+ { .compatible = "axis,artpec8-dw-mshc",
+ .data = &artpec_drv_data, },
{},
};
MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
--
2.20.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 3/4] mmc: dw_mmc: Add driver callbacks for data read timeout
2021-12-09 16:45 [PATCH v3 0/4] Add ARTPEC-8 support to DWMMC controller Mårten Lindahl
2021-12-09 16:45 ` [PATCH v3 1/4] dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8 Mårten Lindahl
2021-12-09 16:45 ` [PATCH v3 2/4] mmc: dw_mmc-exynos: " Mårten Lindahl
@ 2021-12-09 16:45 ` Mårten Lindahl
2021-12-09 16:45 ` [PATCH v3 4/4] mmc: dw_mmc: Do not wait for DTO in case of error Mårten Lindahl
3 siblings, 0 replies; 9+ messages in thread
From: Mårten Lindahl @ 2021-12-09 16:45 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Jaehoon Chung
Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel,
linux-samsung-soc, Mårten Lindahl
Current dw_mci driver supports a TMOUT register which consists of a 24
bit field (TMOUT[31:8]) for the DATA_TIMEOUT. The maximum value of this
field is 0xFFFFFF, which with a 200MHz clock will give a full DRTO of:
0xFFFFFF / 200000000 => ~84 ms
However, the ARTPEC-8 SoC DWMMC IP version has a TMOUT register with an
extended DATA_TIMEOUT field, which supports longer timers for the DRTO.
In this version the DATA_TIMEOUT field is split into two, which with the
same 200MHz clock as above will allow a maximum timeout of:
((TMOUT[10:8] -1) * 0xFFFFFF + TMOUT[31:11] * 8) / 200000000 => ~587 ms
Add driver callbacks for implementation specific data timeout, and
implement callback functions for the ARTPEC-8 SoC.
Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com>
---
v2:
- Removed unnecessary comment
- Change 1<<0 to BIT(0)
v3:
- Add callback for implementation specific control of data timeout
- Add callback for implementation specific read of cycle count for
data timeout.
- Remove definition and use of DW_MMC_QUIRK_EXTENDED_TMOUT.
drivers/mmc/host/dw_mmc-exynos.c | 49 ++++++++++++++++++++++++++++++++
drivers/mmc/host/dw_mmc.c | 12 +++++++-
drivers/mmc/host/dw_mmc.h | 5 ++++
3 files changed, 65 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 86486e6659de..4e5612d04504 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -539,6 +539,53 @@ static int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host,
return 0;
}
+static void dw_mci_exynos_set_data_timeout(struct dw_mci *host,
+ unsigned int timeout_ns)
+{
+ u32 clk_div, tmout;
+ u64 tmp;
+ unsigned int tmp2;
+
+ clk_div = (mci_readl(host, CLKDIV) & 0xFF) * 2;
+ if (clk_div == 0)
+ clk_div = 1;
+
+ tmp = DIV_ROUND_UP_ULL((u64)timeout_ns * host->bus_hz, NSEC_PER_SEC);
+ tmp = DIV_ROUND_UP_ULL(tmp, clk_div);
+
+ /* TMOUT[7:0] (RESPONSE_TIMEOUT) */
+ tmout = 0xFF; /* Set maximum */
+
+ /*
+ * Extended HW timer (max = 0x6FFFFF2):
+ * ((TMOUT[10:8] - 1) * 0xFFFFFF + TMOUT[31:11] * 8)
+ */
+ if (!tmp || tmp > 0x6FFFFF2)
+ tmout |= (0xFFFFFF << 8);
+ else {
+ /* TMOUT[10:8] */
+ tmp2 = (((unsigned int)tmp / 0xFFFFFF) + 1) & 0x7;
+ tmout |= tmp2 << 8;
+
+ /* TMOUT[31:11] */
+ tmp = tmp - ((tmp2 - 1) * 0xFFFFFF);
+ tmout |= (tmp & 0xFFFFF8) << 8;
+ }
+
+ mci_writel(host, TMOUT, tmout);
+ dev_dbg(host->dev, "timeout_ns: %u => TMOUT[31:8]: 0x%#08x",
+ timeout_ns, tmout >> 8);
+}
+
+static u32 dw_mci_exynos_get_drto_clks(struct dw_mci *host)
+{
+ u32 drto_clks;
+
+ drto_clks = mci_readl(host, TMOUT) >> 8;
+
+ return (((drto_clks & 0x7) - 1) * 0xFFFFFF) + ((drto_clks & 0xFFFFF8));
+}
+
/* Common capabilities of Exynos4/Exynos5 SoC */
static unsigned long exynos_dwmmc_caps[4] = {
MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA,
@@ -564,6 +611,8 @@ static const struct dw_mci_drv_data artpec_drv_data = {
.set_ios = dw_mci_exynos_set_ios,
.parse_dt = dw_mci_exynos_parse_dt,
.execute_tuning = dw_mci_exynos_execute_tuning,
+ .set_data_timeout = dw_mci_exynos_set_data_timeout,
+ .get_drto_clks = dw_mci_exynos_get_drto_clks,
};
static const struct of_device_id dw_mci_exynos_match[] = {
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index f2a14a434bef..a7745e193afa 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1287,9 +1287,13 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
static void dw_mci_set_data_timeout(struct dw_mci *host,
unsigned int timeout_ns)
{
+ const struct dw_mci_drv_data *drv_data = host->drv_data;
u32 clk_div, tmout;
u64 tmp;
+ if (drv_data && drv_data->set_data_timeout)
+ return drv_data->set_data_timeout(host, timeout_ns);
+
clk_div = (mci_readl(host, CLKDIV) & 0xFF) * 2;
if (clk_div == 0)
clk_div = 1;
@@ -1995,12 +1999,16 @@ static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
static void dw_mci_set_drto(struct dw_mci *host)
{
+ const struct dw_mci_drv_data *drv_data = host->drv_data;
unsigned int drto_clks;
unsigned int drto_div;
unsigned int drto_ms;
unsigned long irqflags;
- drto_clks = mci_readl(host, TMOUT) >> 8;
+ if (drv_data && drv_data->get_drto_clks)
+ drto_clks = drv_data->get_drto_clks(host);
+ else
+ drto_clks = mci_readl(host, TMOUT) >> 8;
drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
if (drto_div == 0)
drto_div = 1;
@@ -2008,6 +2016,8 @@ static void dw_mci_set_drto(struct dw_mci *host)
drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div,
host->bus_hz);
+ dev_dbg(host->dev, "drto_ms: %u\n", drto_ms);
+
/* add a bit spare time */
drto_ms += 10;
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 771d5afa3136..0a85d05eaf12 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -556,6 +556,8 @@ struct dw_mci_slot {
* @set_ios: handle bus specific extensions.
* @parse_dt: parse implementation specific device tree properties.
* @execute_tuning: implementation specific tuning procedure.
+ * @set_data_timeout: implementation specific timeout.
+ * @get_drto_clks: implementation specific cycle count for data read timeout.
*
* Provide controller implementation specific extensions. The usage of this
* data structure is fully optional and usage of each member in this structure
@@ -573,5 +575,8 @@ struct dw_mci_drv_data {
struct mmc_ios *ios);
int (*switch_voltage)(struct mmc_host *mmc,
struct mmc_ios *ios);
+ void (*set_data_timeout)(struct dw_mci *host,
+ unsigned int timeout_ns);
+ u32 (*get_drto_clks)(struct dw_mci *host);
};
#endif /* _DW_MMC_H_ */
--
2.20.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 4/4] mmc: dw_mmc: Do not wait for DTO in case of error
2021-12-09 16:45 [PATCH v3 0/4] Add ARTPEC-8 support to DWMMC controller Mårten Lindahl
` (2 preceding siblings ...)
2021-12-09 16:45 ` [PATCH v3 3/4] mmc: dw_mmc: Add driver callbacks for data read timeout Mårten Lindahl
@ 2021-12-09 16:45 ` Mårten Lindahl
3 siblings, 0 replies; 9+ messages in thread
From: Mårten Lindahl @ 2021-12-09 16:45 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Jaehoon Chung
Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel,
linux-samsung-soc, Mårten Lindahl
When running the ARTPEC-8 DWMMC IP version, and a data error interrupt
comes during a data read transfer, there is no guarantee for the data
transfer over interrupt (DTO) to come within the specified data timeout.
This case is handled by the dto_timer handler which will complete the
request with the comment:
/*
* If DTO interrupt does NOT come in sending data state,
* we should notify the driver to terminate current transfer
* and report a data timeout to the core.
*/
But since the ARTPEC-8 DWMMC IP version, supports an extended TMOUT
register which allows longer timeouts than the non ARTPEC-8 version
does, waiting for the dto_timer to complete the request in error cases
may cause the request to take significantly longer time than necessary.
This is specifically true for the failing steps during tuning of a
device.
Fix this by completing the request when the error interrupt comes. Since
this fix is specific for the ARTPEC-8, a quirk is added.
Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com>
---
v3:
- Define DW_MMC_QUIRK_EXTENDED_TMOUT.
- Implement DW_MMC_QUIRK_EXTENDED_TMOUT for the ARTPEC-8 SoC.
drivers/mmc/host/dw_mmc-exynos.c | 5 +++++
drivers/mmc/host/dw_mmc.c | 9 +++++++++
drivers/mmc/host/dw_mmc.h | 5 +++++
3 files changed, 19 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 4e5612d04504..70ff7597f2b0 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -127,6 +127,11 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl);
}
+ if (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) {
+ /* Quirk needed for the ARTPEC-8 SoC */
+ host->quirks |= DW_MMC_QUIRK_EXTENDED_TMOUT;
+ }
+
host->bus_hz /= (priv->ciu_div + 1);
return 0;
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index a7745e193afa..da09a06898c9 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2762,11 +2762,20 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
if (pending & DW_MCI_DATA_ERROR_FLAGS) {
spin_lock(&host->irq_lock);
+ if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT)
+ del_timer(&host->dto_timer);
+
/* if there is an error report DATA_ERROR */
mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
host->data_status = pending;
smp_wmb(); /* drain writebuffer */
set_bit(EVENT_DATA_ERROR, &host->pending_events);
+
+ if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT)
+ /* In case of error, we cannot expect a DTO */
+ set_bit(EVENT_DATA_COMPLETE,
+ &host->pending_events);
+
tasklet_schedule(&host->tasklet);
spin_unlock(&host->irq_lock);
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 0a85d05eaf12..7f1e38621d13 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -118,6 +118,7 @@ struct dw_mci_dma_slave {
* @part_buf: Simple buffer for partial fifo reads/writes.
* @push_data: Pointer to FIFO push function.
* @pull_data: Pointer to FIFO pull function.
+ * @quirks: Set of quirks that apply to specific versions of the IP.
* @vqmmc_enabled: Status of vqmmc, should be true or false.
* @irq_flags: The flags to be passed to request_irq.
* @irq: The irq value to be passed to request_irq.
@@ -223,6 +224,7 @@ struct dw_mci {
void (*push_data)(struct dw_mci *host, void *buf, int cnt);
void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
+ u32 quirks;
bool vqmmc_enabled;
unsigned long irq_flags; /* IRQ flags */
int irq;
@@ -274,6 +276,9 @@ struct dw_mci_board {
struct dma_pdata *data;
};
+/* Support for longer data read timeout */
+#define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0)
+
#define DW_MMC_240A 0x240a
#define DW_MMC_280A 0x280a
--
2.20.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8
2021-12-09 16:45 ` [PATCH v3 1/4] dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8 Mårten Lindahl
@ 2021-12-09 18:27 ` Krzysztof Kozlowski
2021-12-09 20:25 ` Marten Lindahl
0 siblings, 1 reply; 9+ messages in thread
From: Krzysztof Kozlowski @ 2021-12-09 18:27 UTC (permalink / raw)
To: Mårten Lindahl, Ulf Hansson, Rob Herring, Jaehoon Chung
Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel,
linux-samsung-soc
On 09/12/2021 17:45, Mårten Lindahl wrote:
> The ARTPEC-8 SoC has a DWMMC controller that is compatible with the
> Exynos 7 version v2.70a. The main differences from Exynos 7 is that it
> does not support HS400 and has extended data read timeout.
>
> Add compatibility string "axis,artpec8-dw-mshc" for ARTPEC-8.
>
> Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com>
> ---
>
> v2:
> - Change compatible string vendor prefix
>
> Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
> index 0419a63f73a0..753e9d7d8956 100644
> --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
> @@ -22,6 +22,8 @@ Required Properties:
> specific extensions.
> - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
> specific extensions having an SMU.
> + - "axis,artpec8-dw-mshc": for controllers with ARTPEC-8 specific
> + extensions.
>
Any reason why you ignored my tag?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 2/4] mmc: dw_mmc-exynos: Add support for ARTPEC-8
2021-12-09 16:45 ` [PATCH v3 2/4] mmc: dw_mmc-exynos: " Mårten Lindahl
@ 2021-12-09 18:28 ` Krzysztof Kozlowski
2021-12-09 20:27 ` Marten Lindahl
0 siblings, 1 reply; 9+ messages in thread
From: Krzysztof Kozlowski @ 2021-12-09 18:28 UTC (permalink / raw)
To: Mårten Lindahl, Ulf Hansson, Rob Herring, Jaehoon Chung
Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel,
linux-samsung-soc
On 09/12/2021 17:45, Mårten Lindahl wrote:
> The ARTPEC-8 SoC has a DWMMC controller that is compatible with the
> Exynos 7 version v2.70a. The main differences from Exynos 7 is that it
> does not support HS400 and has extended data read timeout.
>
> This patch adds compatibility string "axis,artpec8-dw-mshc" for
> ARTPEC-8, and DW_MCI_TYPE_ARTPEC8 is added to the dw_mci_exynos_type.
>
> Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com>
> ---
>
> v2:
> - Change compatible string vendor prefix
>
> drivers/mmc/host/dw_mmc-exynos.c | 47 ++++++++++++++++++++++++--------
> 1 file changed, 36 insertions(+), 11 deletions(-)
>
Here you dropped my tag as well.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8
2021-12-09 18:27 ` Krzysztof Kozlowski
@ 2021-12-09 20:25 ` Marten Lindahl
0 siblings, 0 replies; 9+ messages in thread
From: Marten Lindahl @ 2021-12-09 20:25 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Mårten Lindahl, Ulf Hansson, Rob Herring, Jaehoon Chung,
Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel,
linux-samsung-soc
On Thu, Dec 09, 2021 at 07:27:25PM +0100, Krzysztof Kozlowski wrote:
> On 09/12/2021 17:45, Mårten Lindahl wrote:
> > The ARTPEC-8 SoC has a DWMMC controller that is compatible with the
> > Exynos 7 version v2.70a. The main differences from Exynos 7 is that it
> > does not support HS400 and has extended data read timeout.
> >
> > Add compatibility string "axis,artpec8-dw-mshc" for ARTPEC-8.
> >
> > Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com>
> > ---
> >
> > v2:
> > - Change compatible string vendor prefix
> >
> > Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
> > index 0419a63f73a0..753e9d7d8956 100644
> > --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
> > +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
> > @@ -22,6 +22,8 @@ Required Properties:
> > specific extensions.
> > - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
> > specific extensions having an SMU.
> > + - "axis,artpec8-dw-mshc": for controllers with ARTPEC-8 specific
> > + extensions.
> >
Hi Krzysztof!
>
> Any reason why you ignored my tag?
I'm sorry. It was a misstake by me. I will of course add it right away.
Kind regards
Mårten
>
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 2/4] mmc: dw_mmc-exynos: Add support for ARTPEC-8
2021-12-09 18:28 ` Krzysztof Kozlowski
@ 2021-12-09 20:27 ` Marten Lindahl
0 siblings, 0 replies; 9+ messages in thread
From: Marten Lindahl @ 2021-12-09 20:27 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Mårten Lindahl, Ulf Hansson, Rob Herring, Jaehoon Chung,
Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel,
linux-samsung-soc
On Thu, Dec 09, 2021 at 07:28:12PM +0100, Krzysztof Kozlowski wrote:
> On 09/12/2021 17:45, Mårten Lindahl wrote:
> > The ARTPEC-8 SoC has a DWMMC controller that is compatible with the
> > Exynos 7 version v2.70a. The main differences from Exynos 7 is that it
> > does not support HS400 and has extended data read timeout.
> >
> > This patch adds compatibility string "axis,artpec8-dw-mshc" for
> > ARTPEC-8, and DW_MCI_TYPE_ARTPEC8 is added to the dw_mci_exynos_type.
> >
> > Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com>
> > ---
> >
> > v2:
> > - Change compatible string vendor prefix
> >
> > drivers/mmc/host/dw_mmc-exynos.c | 47 ++++++++++++++++++++++++--------
> > 1 file changed, 36 insertions(+), 11 deletions(-)
> >
Hi Krzysztof!
>
> Here you dropped my tag as well.
I'm very sorry. I will of course add it right away.
Kind regards
Mårten
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-12-09 20:28 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-09 16:45 [PATCH v3 0/4] Add ARTPEC-8 support to DWMMC controller Mårten Lindahl
2021-12-09 16:45 ` [PATCH v3 1/4] dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8 Mårten Lindahl
2021-12-09 18:27 ` Krzysztof Kozlowski
2021-12-09 20:25 ` Marten Lindahl
2021-12-09 16:45 ` [PATCH v3 2/4] mmc: dw_mmc-exynos: " Mårten Lindahl
2021-12-09 18:28 ` Krzysztof Kozlowski
2021-12-09 20:27 ` Marten Lindahl
2021-12-09 16:45 ` [PATCH v3 3/4] mmc: dw_mmc: Add driver callbacks for data read timeout Mårten Lindahl
2021-12-09 16:45 ` [PATCH v3 4/4] mmc: dw_mmc: Do not wait for DTO in case of error Mårten Lindahl
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