* [PATCH 04/11] dt-bindings: PCI: mvebu: Add num-lanes property [not found] <20220105150239.9628-1-pali@kernel.org> @ 2022-01-05 15:02 ` Pali Rohár 2022-01-12 1:29 ` Rob Herring 2022-01-05 15:02 ` [PATCH 09/11] dt-bindings: PCI: mvebu: Update information about intx interrupts Pali Rohár ` (2 subsequent siblings) 3 siblings, 1 reply; 13+ messages in thread From: Pali Rohár @ 2022-01-05 15:02 UTC (permalink / raw) To: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King, Andrew Lunn, Gregory Clement Cc: linux-pci, linux-kernel, linux-arm-kernel, devicetree Controller driver needs to correctly configure PCIe link if it contains 1 or 4 SerDes PCIe lanes. Therefore add a new 'num-lanes' DT property for mvebu PCIe controller. Property 'num-lanes' seems to be de-facto standard way how number of lanes is specified in other PCIe controllers. Signed-off-by: Pali Rohár <pali@kernel.org> --- Documentation/devicetree/bindings/pci/mvebu-pci.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt index 6173af6885f8..24225852bce0 100644 --- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt +++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt @@ -77,6 +77,7 @@ and the following optional properties: - marvell,pcie-lane: the physical PCIe lane number, for ports having multiple lanes. If this property is not found, we assume that the value is 0. +- num-lanes: number of SerDes PCIe lanes for this link (1 or 4) - reset-gpios: optional GPIO to PERST# - reset-delay-us: delay in us to wait after reset de-assertion, if not specified will default to 100ms, as required by the PCIe specification. @@ -141,6 +142,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; + num-lanes = <1>; /* low-active PERST# reset on GPIO 25 */ reset-gpios = <&gpio0 25 1>; /* wait 20ms for device settle after reset deassertion */ @@ -161,6 +163,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 59>; marvell,pcie-port = <0>; marvell,pcie-lane = <1>; + num-lanes = <1>; clocks = <&gateclk 6>; }; @@ -177,6 +180,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 60>; marvell,pcie-port = <0>; marvell,pcie-lane = <2>; + num-lanes = <1>; clocks = <&gateclk 7>; }; @@ -193,6 +197,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 61>; marvell,pcie-port = <0>; marvell,pcie-lane = <3>; + num-lanes = <1>; clocks = <&gateclk 8>; }; @@ -209,6 +214,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; + num-lanes = <1>; clocks = <&gateclk 9>; }; @@ -225,6 +231,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 63>; marvell,pcie-port = <1>; marvell,pcie-lane = <1>; + num-lanes = <1>; clocks = <&gateclk 10>; }; @@ -241,6 +248,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 64>; marvell,pcie-port = <1>; marvell,pcie-lane = <2>; + num-lanes = <1>; clocks = <&gateclk 11>; }; @@ -257,6 +265,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 65>; marvell,pcie-port = <1>; marvell,pcie-lane = <3>; + num-lanes = <1>; clocks = <&gateclk 12>; }; @@ -273,6 +282,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 99>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; + num-lanes = <1>; clocks = <&gateclk 26>; }; @@ -289,6 +299,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 103>; marvell,pcie-port = <3>; marvell,pcie-lane = <0>; + num-lanes = <1>; clocks = <&gateclk 27>; }; }; -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 04/11] dt-bindings: PCI: mvebu: Add num-lanes property 2022-01-05 15:02 ` [PATCH 04/11] dt-bindings: PCI: mvebu: Add num-lanes property Pali Rohár @ 2022-01-12 1:29 ` Rob Herring 0 siblings, 0 replies; 13+ messages in thread From: Rob Herring @ 2022-01-12 1:29 UTC (permalink / raw) To: Pali Rohár Cc: Krzysztof Wilczyński, Thomas Petazzoni, linux-arm-kernel, Rob Herring, Bjorn Helgaas, Marek Behún, linux-pci, linux-kernel, Russell King, devicetree, Andrew Lunn, Gregory Clement, Lorenzo Pieralisi On Wed, 05 Jan 2022 16:02:32 +0100, Pali Rohár wrote: > Controller driver needs to correctly configure PCIe link if it contains 1 > or 4 SerDes PCIe lanes. Therefore add a new 'num-lanes' DT property for > mvebu PCIe controller. Property 'num-lanes' seems to be de-facto standard > way how number of lanes is specified in other PCIe controllers. > > Signed-off-by: Pali Rohár <pali@kernel.org> > --- > Documentation/devicetree/bindings/pci/mvebu-pci.txt | 11 +++++++++++ > 1 file changed, 11 insertions(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 09/11] dt-bindings: PCI: mvebu: Update information about intx interrupts [not found] <20220105150239.9628-1-pali@kernel.org> 2022-01-05 15:02 ` [PATCH 04/11] dt-bindings: PCI: mvebu: Add num-lanes property Pali Rohár @ 2022-01-05 15:02 ` Pali Rohár 2022-01-12 1:30 ` Rob Herring 2022-01-05 15:02 ` [PATCH 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe legacy INTx interrupts Pali Rohár [not found] ` <20220112151814.24361-1-pali@kernel.org> 3 siblings, 1 reply; 13+ messages in thread From: Pali Rohár @ 2022-01-05 15:02 UTC (permalink / raw) To: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King, Andrew Lunn, Gregory Clement Cc: linux-pci, linux-kernel, linux-arm-kernel, devicetree Signed-off-by: Pali Rohár <pali@kernel.org> --- Documentation/devicetree/bindings/pci/mvebu-pci.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt index 24225852bce0..6d022a9d36ee 100644 --- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt +++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt @@ -81,6 +81,11 @@ and the following optional properties: - reset-gpios: optional GPIO to PERST# - reset-delay-us: delay in us to wait after reset de-assertion, if not specified will default to 100ms, as required by the PCIe specification. +- interrupt-names: list of interrupt names, supported are: + - "intx" - interrupt line triggered by one of the legacy interrupt +- interrupts or interrupts-extended: List of the interrupt sources which + corresponding to the "interrupt-names". If non-empty then also additional + 'interrupt-controller' subnode must be defined. Example: -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 09/11] dt-bindings: PCI: mvebu: Update information about intx interrupts 2022-01-05 15:02 ` [PATCH 09/11] dt-bindings: PCI: mvebu: Update information about intx interrupts Pali Rohár @ 2022-01-12 1:30 ` Rob Herring 0 siblings, 0 replies; 13+ messages in thread From: Rob Herring @ 2022-01-12 1:30 UTC (permalink / raw) To: Pali Rohár Cc: Russell King, Gregory Clement, devicetree, Rob Herring, linux-kernel, linux-pci, Krzysztof Wilczyński, Bjorn Helgaas, linux-arm-kernel, Marek Behún, Andrew Lunn, Thomas Petazzoni, Lorenzo Pieralisi On Wed, 05 Jan 2022 16:02:37 +0100, Pali Rohár wrote: > Signed-off-by: Pali Rohár <pali@kernel.org> > --- > Documentation/devicetree/bindings/pci/mvebu-pci.txt | 5 +++++ > 1 file changed, 5 insertions(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe legacy INTx interrupts [not found] <20220105150239.9628-1-pali@kernel.org> 2022-01-05 15:02 ` [PATCH 04/11] dt-bindings: PCI: mvebu: Add num-lanes property Pali Rohár 2022-01-05 15:02 ` [PATCH 09/11] dt-bindings: PCI: mvebu: Update information about intx interrupts Pali Rohár @ 2022-01-05 15:02 ` Pali Rohár [not found] ` <20220112151814.24361-1-pali@kernel.org> 3 siblings, 0 replies; 13+ messages in thread From: Pali Rohár @ 2022-01-05 15:02 UTC (permalink / raw) To: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King, Andrew Lunn, Gregory Clement Cc: linux-pci, linux-kernel, linux-arm-kernel, devicetree With this change legacy INTA, INTB, INTC and INTD interrupts are reported separately and not mixed into one Linux virq source anymore. Signed-off-by: Pali Rohár <pali@kernel.org> --- arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++----- 1 file changed, 44 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi index f0022d10c715..83392b92dae2 100644 --- a/arch/arm/boot/dts/armada-385.dtsi +++ b/arch/arm/boot/dts/armada-385.dtsi @@ -69,16 +69,25 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 8>; status = "disabled"; + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -88,16 +97,25 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -107,16 +125,25 @@ reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 6>; status = "disabled"; + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* @@ -129,16 +156,25 @@ reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; marvell,pcie-port = <3>; marvell,pcie-lane = <0>; clocks = <&gateclk 7>; status = "disabled"; + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; }; -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
[parent not found: <20220112151814.24361-1-pali@kernel.org>]
* [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe legacy INTx interrupts [not found] ` <20220112151814.24361-1-pali@kernel.org> @ 2022-01-12 15:18 ` Pali Rohár 2022-02-14 15:07 ` Gregory CLEMENT 0 siblings, 1 reply; 13+ messages in thread From: Pali Rohár @ 2022-01-12 15:18 UTC (permalink / raw) To: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King, Andrew Lunn, Gregory Clement Cc: linux-pci, linux-kernel, linux-arm-kernel, devicetree With this change legacy INTA, INTB, INTC and INTD interrupts are reported separately and not mixed into one Linux virq source anymore. Signed-off-by: Pali Rohár <pali@kernel.org> --- arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++----- 1 file changed, 44 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi index f0022d10c715..83392b92dae2 100644 --- a/arch/arm/boot/dts/armada-385.dtsi +++ b/arch/arm/boot/dts/armada-385.dtsi @@ -69,16 +69,25 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 8>; status = "disabled"; + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -88,16 +97,25 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -107,16 +125,25 @@ reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 6>; status = "disabled"; + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* @@ -129,16 +156,25 @@ reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; marvell,pcie-port = <3>; marvell,pcie-lane = <0>; clocks = <&gateclk 7>; status = "disabled"; + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; }; -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe legacy INTx interrupts 2022-01-12 15:18 ` [PATCH v2 " Pali Rohár @ 2022-02-14 15:07 ` Gregory CLEMENT 2022-02-14 15:09 ` Pali Rohár 0 siblings, 1 reply; 13+ messages in thread From: Gregory CLEMENT @ 2022-02-14 15:07 UTC (permalink / raw) To: Pali Rohár, Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King, Andrew Lunn Cc: linux-pci, linux-kernel, linux-arm-kernel, devicetree Hello Pali, > With this change legacy INTA, INTB, INTC and INTD interrupts are reported > separately and not mixed into one Linux virq source anymore. > > Signed-off-by: Pali Rohár <pali@kernel.org> > --- > arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++----- Is there any reason for not doing the same change in armada-380.dtsi ? Grégory > 1 file changed, 44 insertions(+), 8 deletions(-) > > diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi > index f0022d10c715..83392b92dae2 100644 > --- a/arch/arm/boot/dts/armada-385.dtsi > +++ b/arch/arm/boot/dts/armada-385.dtsi > @@ -69,16 +69,25 @@ > reg = <0x0800 0 0 0 0>; > #address-cells = <3>; > #size-cells = <2>; > + interrupt-names = "intx"; > + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <1>; > ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 > 0x81000000 0 0 0x81000000 0x1 0 1 0>; > bus-range = <0x00 0xff>; > - interrupt-map-mask = <0 0 0 0>; > - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie1_intc 0>, > + <0 0 0 2 &pcie1_intc 1>, > + <0 0 0 3 &pcie1_intc 2>, > + <0 0 0 4 &pcie1_intc 3>; > marvell,pcie-port = <0>; > marvell,pcie-lane = <0>; > clocks = <&gateclk 8>; > status = "disabled"; > + pcie1_intc: interrupt-controller { > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > }; > > /* x1 port */ > @@ -88,16 +97,25 @@ > reg = <0x1000 0 0 0 0>; > #address-cells = <3>; > #size-cells = <2>; > + interrupt-names = "intx"; > + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <1>; > ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 > 0x81000000 0 0 0x81000000 0x2 0 1 0>; > bus-range = <0x00 0xff>; > - interrupt-map-mask = <0 0 0 0>; > - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie2_intc 0>, > + <0 0 0 2 &pcie2_intc 1>, > + <0 0 0 3 &pcie2_intc 2>, > + <0 0 0 4 &pcie2_intc 3>; > marvell,pcie-port = <1>; > marvell,pcie-lane = <0>; > clocks = <&gateclk 5>; > status = "disabled"; > + pcie2_intc: interrupt-controller { > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > }; > > /* x1 port */ > @@ -107,16 +125,25 @@ > reg = <0x1800 0 0 0 0>; > #address-cells = <3>; > #size-cells = <2>; > + interrupt-names = "intx"; > + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <1>; > ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 > 0x81000000 0 0 0x81000000 0x3 0 1 0>; > bus-range = <0x00 0xff>; > - interrupt-map-mask = <0 0 0 0>; > - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie3_intc 0>, > + <0 0 0 2 &pcie3_intc 1>, > + <0 0 0 3 &pcie3_intc 2>, > + <0 0 0 4 &pcie3_intc 3>; > marvell,pcie-port = <2>; > marvell,pcie-lane = <0>; > clocks = <&gateclk 6>; > status = "disabled"; > + pcie3_intc: interrupt-controller { > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > }; > > /* > @@ -129,16 +156,25 @@ > reg = <0x2000 0 0 0 0>; > #address-cells = <3>; > #size-cells = <2>; > + interrupt-names = "intx"; > + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <1>; > ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 > 0x81000000 0 0 0x81000000 0x4 0 1 0>; > bus-range = <0x00 0xff>; > - interrupt-map-mask = <0 0 0 0>; > - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie4_intc 0>, > + <0 0 0 2 &pcie4_intc 1>, > + <0 0 0 3 &pcie4_intc 2>, > + <0 0 0 4 &pcie4_intc 3>; > marvell,pcie-port = <3>; > marvell,pcie-lane = <0>; > clocks = <&gateclk 7>; > status = "disabled"; > + pcie4_intc: interrupt-controller { > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > }; > }; > }; > -- > 2.20.1 > -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe legacy INTx interrupts 2022-02-14 15:07 ` Gregory CLEMENT @ 2022-02-14 15:09 ` Pali Rohár 2022-02-14 15:26 ` Gregory CLEMENT 0 siblings, 1 reply; 13+ messages in thread From: Pali Rohár @ 2022-02-14 15:09 UTC (permalink / raw) To: Gregory CLEMENT Cc: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King, Andrew Lunn, linux-pci, linux-kernel, linux-arm-kernel, devicetree On Monday 14 February 2022 16:07:13 Gregory CLEMENT wrote: > Hello Pali, > > > With this change legacy INTA, INTB, INTC and INTD interrupts are reported > > separately and not mixed into one Linux virq source anymore. > > > > Signed-off-by: Pali Rohár <pali@kernel.org> > > --- > > arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++----- > > Is there any reason for not doing the same change in armada-380.dtsi ? I do not have A380 HW, so I did this change only for A385 which I have tested. > Grégory > > > 1 file changed, 44 insertions(+), 8 deletions(-) > > > > diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi > > index f0022d10c715..83392b92dae2 100644 > > --- a/arch/arm/boot/dts/armada-385.dtsi > > +++ b/arch/arm/boot/dts/armada-385.dtsi > > @@ -69,16 +69,25 @@ > > reg = <0x0800 0 0 0 0>; > > #address-cells = <3>; > > #size-cells = <2>; > > + interrupt-names = "intx"; > > + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > > #interrupt-cells = <1>; > > ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 > > 0x81000000 0 0 0x81000000 0x1 0 1 0>; > > bus-range = <0x00 0xff>; > > - interrupt-map-mask = <0 0 0 0>; > > - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-map-mask = <0 0 0 7>; > > + interrupt-map = <0 0 0 1 &pcie1_intc 0>, > > + <0 0 0 2 &pcie1_intc 1>, > > + <0 0 0 3 &pcie1_intc 2>, > > + <0 0 0 4 &pcie1_intc 3>; > > marvell,pcie-port = <0>; > > marvell,pcie-lane = <0>; > > clocks = <&gateclk 8>; > > status = "disabled"; > > + pcie1_intc: interrupt-controller { > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > }; > > > > /* x1 port */ > > @@ -88,16 +97,25 @@ > > reg = <0x1000 0 0 0 0>; > > #address-cells = <3>; > > #size-cells = <2>; > > + interrupt-names = "intx"; > > + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > > #interrupt-cells = <1>; > > ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 > > 0x81000000 0 0 0x81000000 0x2 0 1 0>; > > bus-range = <0x00 0xff>; > > - interrupt-map-mask = <0 0 0 0>; > > - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-map-mask = <0 0 0 7>; > > + interrupt-map = <0 0 0 1 &pcie2_intc 0>, > > + <0 0 0 2 &pcie2_intc 1>, > > + <0 0 0 3 &pcie2_intc 2>, > > + <0 0 0 4 &pcie2_intc 3>; > > marvell,pcie-port = <1>; > > marvell,pcie-lane = <0>; > > clocks = <&gateclk 5>; > > status = "disabled"; > > + pcie2_intc: interrupt-controller { > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > }; > > > > /* x1 port */ > > @@ -107,16 +125,25 @@ > > reg = <0x1800 0 0 0 0>; > > #address-cells = <3>; > > #size-cells = <2>; > > + interrupt-names = "intx"; > > + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > > #interrupt-cells = <1>; > > ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 > > 0x81000000 0 0 0x81000000 0x3 0 1 0>; > > bus-range = <0x00 0xff>; > > - interrupt-map-mask = <0 0 0 0>; > > - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-map-mask = <0 0 0 7>; > > + interrupt-map = <0 0 0 1 &pcie3_intc 0>, > > + <0 0 0 2 &pcie3_intc 1>, > > + <0 0 0 3 &pcie3_intc 2>, > > + <0 0 0 4 &pcie3_intc 3>; > > marvell,pcie-port = <2>; > > marvell,pcie-lane = <0>; > > clocks = <&gateclk 6>; > > status = "disabled"; > > + pcie3_intc: interrupt-controller { > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > }; > > > > /* > > @@ -129,16 +156,25 @@ > > reg = <0x2000 0 0 0 0>; > > #address-cells = <3>; > > #size-cells = <2>; > > + interrupt-names = "intx"; > > + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > > #interrupt-cells = <1>; > > ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 > > 0x81000000 0 0 0x81000000 0x4 0 1 0>; > > bus-range = <0x00 0xff>; > > - interrupt-map-mask = <0 0 0 0>; > > - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-map-mask = <0 0 0 7>; > > + interrupt-map = <0 0 0 1 &pcie4_intc 0>, > > + <0 0 0 2 &pcie4_intc 1>, > > + <0 0 0 3 &pcie4_intc 2>, > > + <0 0 0 4 &pcie4_intc 3>; > > marvell,pcie-port = <3>; > > marvell,pcie-lane = <0>; > > clocks = <&gateclk 7>; > > status = "disabled"; > > + pcie4_intc: interrupt-controller { > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > }; > > }; > > }; > > -- > > 2.20.1 > > > > -- > Gregory Clement, Bootlin > Embedded Linux and Kernel engineering > http://bootlin.com ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe legacy INTx interrupts 2022-02-14 15:09 ` Pali Rohár @ 2022-02-14 15:26 ` Gregory CLEMENT [not found] ` <CAEzXK1qYKVk7QiSY_DwqkZ7WV6WU06WBtiqZx0JJCc+mOP-7Kg@mail.gmail.com> 0 siblings, 1 reply; 13+ messages in thread From: Gregory CLEMENT @ 2022-02-14 15:26 UTC (permalink / raw) To: Pali Rohár Cc: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King, Andrew Lunn, linux-pci, linux-kernel, linux-arm-kernel, devicetree Hello, > On Monday 14 February 2022 16:07:13 Gregory CLEMENT wrote: >> Hello Pali, >> >> > With this change legacy INTA, INTB, INTC and INTD interrupts are reported >> > separately and not mixed into one Linux virq source anymore. >> > >> > Signed-off-by: Pali Rohár <pali@kernel.org> >> > --- >> > arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++----- >> >> Is there any reason for not doing the same change in armada-380.dtsi ? > > I do not have A380 HW, so I did this change only for A385 which I have > tested. OK fair enough. So you can add my Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Moreover to keep biscetability this patch should be merged after the support in the driver. So the easier is to let merge it through the PCI subsystem with the other patches from this series. I do not think there will be any other changes in this file so there won't be any merge conflicts. Thanks, Grégory > >> Grégory >> >> > 1 file changed, 44 insertions(+), 8 deletions(-) >> > >> > diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi >> > index f0022d10c715..83392b92dae2 100644 >> > --- a/arch/arm/boot/dts/armada-385.dtsi >> > +++ b/arch/arm/boot/dts/armada-385.dtsi >> > @@ -69,16 +69,25 @@ >> > reg = <0x0800 0 0 0 0>; >> > #address-cells = <3>; >> > #size-cells = <2>; >> > + interrupt-names = "intx"; >> > + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; >> > #interrupt-cells = <1>; >> > ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 >> > 0x81000000 0 0 0x81000000 0x1 0 1 0>; >> > bus-range = <0x00 0xff>; >> > - interrupt-map-mask = <0 0 0 0>; >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; >> > + interrupt-map-mask = <0 0 0 7>; >> > + interrupt-map = <0 0 0 1 &pcie1_intc 0>, >> > + <0 0 0 2 &pcie1_intc 1>, >> > + <0 0 0 3 &pcie1_intc 2>, >> > + <0 0 0 4 &pcie1_intc 3>; >> > marvell,pcie-port = <0>; >> > marvell,pcie-lane = <0>; >> > clocks = <&gateclk 8>; >> > status = "disabled"; >> > + pcie1_intc: interrupt-controller { >> > + interrupt-controller; >> > + #interrupt-cells = <1>; >> > + }; >> > }; >> > >> > /* x1 port */ >> > @@ -88,16 +97,25 @@ >> > reg = <0x1000 0 0 0 0>; >> > #address-cells = <3>; >> > #size-cells = <2>; >> > + interrupt-names = "intx"; >> > + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; >> > #interrupt-cells = <1>; >> > ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 >> > 0x81000000 0 0 0x81000000 0x2 0 1 0>; >> > bus-range = <0x00 0xff>; >> > - interrupt-map-mask = <0 0 0 0>; >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; >> > + interrupt-map-mask = <0 0 0 7>; >> > + interrupt-map = <0 0 0 1 &pcie2_intc 0>, >> > + <0 0 0 2 &pcie2_intc 1>, >> > + <0 0 0 3 &pcie2_intc 2>, >> > + <0 0 0 4 &pcie2_intc 3>; >> > marvell,pcie-port = <1>; >> > marvell,pcie-lane = <0>; >> > clocks = <&gateclk 5>; >> > status = "disabled"; >> > + pcie2_intc: interrupt-controller { >> > + interrupt-controller; >> > + #interrupt-cells = <1>; >> > + }; >> > }; >> > >> > /* x1 port */ >> > @@ -107,16 +125,25 @@ >> > reg = <0x1800 0 0 0 0>; >> > #address-cells = <3>; >> > #size-cells = <2>; >> > + interrupt-names = "intx"; >> > + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; >> > #interrupt-cells = <1>; >> > ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 >> > 0x81000000 0 0 0x81000000 0x3 0 1 0>; >> > bus-range = <0x00 0xff>; >> > - interrupt-map-mask = <0 0 0 0>; >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; >> > + interrupt-map-mask = <0 0 0 7>; >> > + interrupt-map = <0 0 0 1 &pcie3_intc 0>, >> > + <0 0 0 2 &pcie3_intc 1>, >> > + <0 0 0 3 &pcie3_intc 2>, >> > + <0 0 0 4 &pcie3_intc 3>; >> > marvell,pcie-port = <2>; >> > marvell,pcie-lane = <0>; >> > clocks = <&gateclk 6>; >> > status = "disabled"; >> > + pcie3_intc: interrupt-controller { >> > + interrupt-controller; >> > + #interrupt-cells = <1>; >> > + }; >> > }; >> > >> > /* >> > @@ -129,16 +156,25 @@ >> > reg = <0x2000 0 0 0 0>; >> > #address-cells = <3>; >> > #size-cells = <2>; >> > + interrupt-names = "intx"; >> > + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; >> > #interrupt-cells = <1>; >> > ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 >> > 0x81000000 0 0 0x81000000 0x4 0 1 0>; >> > bus-range = <0x00 0xff>; >> > - interrupt-map-mask = <0 0 0 0>; >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; >> > + interrupt-map-mask = <0 0 0 7>; >> > + interrupt-map = <0 0 0 1 &pcie4_intc 0>, >> > + <0 0 0 2 &pcie4_intc 1>, >> > + <0 0 0 3 &pcie4_intc 2>, >> > + <0 0 0 4 &pcie4_intc 3>; >> > marvell,pcie-port = <3>; >> > marvell,pcie-lane = <0>; >> > clocks = <&gateclk 7>; >> > status = "disabled"; >> > + pcie4_intc: interrupt-controller { >> > + interrupt-controller; >> > + #interrupt-cells = <1>; >> > + }; >> > }; >> > }; >> > }; >> > -- >> > 2.20.1 >> > >> >> -- >> Gregory Clement, Bootlin >> Embedded Linux and Kernel engineering >> http://bootlin.com -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com ^ permalink raw reply [flat|nested] 13+ messages in thread
[parent not found: <CAEzXK1qYKVk7QiSY_DwqkZ7WV6WU06WBtiqZx0JJCc+mOP-7Kg@mail.gmail.com>]
* Re: [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe legacy INTx interrupts [not found] ` <CAEzXK1qYKVk7QiSY_DwqkZ7WV6WU06WBtiqZx0JJCc+mOP-7Kg@mail.gmail.com> @ 2022-02-15 10:48 ` Luís Mendes 2022-02-15 10:52 ` Pali Rohár 0 siblings, 1 reply; 13+ messages in thread From: Luís Mendes @ 2022-02-15 10:48 UTC (permalink / raw) To: Gregory CLEMENT Cc: Pali Rohár, Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King, Andrew Lunn, Linux PCI, Linux Kernel Mailing List, linux-arm-kernel, devicetree Hello, Sorry for jumping in the conversation, but I read this thread and I have an Armada A388 HW so I can test it, if desired. Luís On Tue, Feb 15, 2022 at 10:47 AM Luís Mendes <luis.p.mendes@gmail.com> wrote: > > Hello, > > Sorry for jumping in the conversation, but I read this thread and I have an Armada A388 HW so I can test it, if desired. > > Luís > > On Mon, Feb 14, 2022 at 7:57 PM Gregory CLEMENT <gregory.clement@bootlin.com> wrote: >> >> Hello, >> >> > On Monday 14 February 2022 16:07:13 Gregory CLEMENT wrote: >> >> Hello Pali, >> >> >> >> > With this change legacy INTA, INTB, INTC and INTD interrupts are reported >> >> > separately and not mixed into one Linux virq source anymore. >> >> > >> >> > Signed-off-by: Pali Rohár <pali@kernel.org> >> >> > --- >> >> > arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++----- >> >> >> >> Is there any reason for not doing the same change in armada-380.dtsi ? >> > >> > I do not have A380 HW, so I did this change only for A385 which I have >> > tested. >> >> OK fair enough. >> >> So you can add my >> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> >> >> Moreover to keep biscetability this patch should be merged after the >> support in the driver. So the easier is to let merge it through the PCI >> subsystem with the other patches from this series. I do not think there >> will be any other changes in this file so there won't be any merge >> conflicts. >> >> Thanks, >> >> Grégory >> >> >> > >> >> Grégory >> >> >> >> > 1 file changed, 44 insertions(+), 8 deletions(-) >> >> > >> >> > diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi >> >> > index f0022d10c715..83392b92dae2 100644 >> >> > --- a/arch/arm/boot/dts/armada-385.dtsi >> >> > +++ b/arch/arm/boot/dts/armada-385.dtsi >> >> > @@ -69,16 +69,25 @@ >> >> > reg = <0x0800 0 0 0 0>; >> >> > #address-cells = <3>; >> >> > #size-cells = <2>; >> >> > + interrupt-names = "intx"; >> >> > + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; >> >> > #interrupt-cells = <1>; >> >> > ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 >> >> > 0x81000000 0 0 0x81000000 0x1 0 1 0>; >> >> > bus-range = <0x00 0xff>; >> >> > - interrupt-map-mask = <0 0 0 0>; >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; >> >> > + interrupt-map-mask = <0 0 0 7>; >> >> > + interrupt-map = <0 0 0 1 &pcie1_intc 0>, >> >> > + <0 0 0 2 &pcie1_intc 1>, >> >> > + <0 0 0 3 &pcie1_intc 2>, >> >> > + <0 0 0 4 &pcie1_intc 3>; >> >> > marvell,pcie-port = <0>; >> >> > marvell,pcie-lane = <0>; >> >> > clocks = <&gateclk 8>; >> >> > status = "disabled"; >> >> > + pcie1_intc: interrupt-controller { >> >> > + interrupt-controller; >> >> > + #interrupt-cells = <1>; >> >> > + }; >> >> > }; >> >> > >> >> > /* x1 port */ >> >> > @@ -88,16 +97,25 @@ >> >> > reg = <0x1000 0 0 0 0>; >> >> > #address-cells = <3>; >> >> > #size-cells = <2>; >> >> > + interrupt-names = "intx"; >> >> > + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; >> >> > #interrupt-cells = <1>; >> >> > ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 >> >> > 0x81000000 0 0 0x81000000 0x2 0 1 0>; >> >> > bus-range = <0x00 0xff>; >> >> > - interrupt-map-mask = <0 0 0 0>; >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; >> >> > + interrupt-map-mask = <0 0 0 7>; >> >> > + interrupt-map = <0 0 0 1 &pcie2_intc 0>, >> >> > + <0 0 0 2 &pcie2_intc 1>, >> >> > + <0 0 0 3 &pcie2_intc 2>, >> >> > + <0 0 0 4 &pcie2_intc 3>; >> >> > marvell,pcie-port = <1>; >> >> > marvell,pcie-lane = <0>; >> >> > clocks = <&gateclk 5>; >> >> > status = "disabled"; >> >> > + pcie2_intc: interrupt-controller { >> >> > + interrupt-controller; >> >> > + #interrupt-cells = <1>; >> >> > + }; >> >> > }; >> >> > >> >> > /* x1 port */ >> >> > @@ -107,16 +125,25 @@ >> >> > reg = <0x1800 0 0 0 0>; >> >> > #address-cells = <3>; >> >> > #size-cells = <2>; >> >> > + interrupt-names = "intx"; >> >> > + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; >> >> > #interrupt-cells = <1>; >> >> > ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 >> >> > 0x81000000 0 0 0x81000000 0x3 0 1 0>; >> >> > bus-range = <0x00 0xff>; >> >> > - interrupt-map-mask = <0 0 0 0>; >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; >> >> > + interrupt-map-mask = <0 0 0 7>; >> >> > + interrupt-map = <0 0 0 1 &pcie3_intc 0>, >> >> > + <0 0 0 2 &pcie3_intc 1>, >> >> > + <0 0 0 3 &pcie3_intc 2>, >> >> > + <0 0 0 4 &pcie3_intc 3>; >> >> > marvell,pcie-port = <2>; >> >> > marvell,pcie-lane = <0>; >> >> > clocks = <&gateclk 6>; >> >> > status = "disabled"; >> >> > + pcie3_intc: interrupt-controller { >> >> > + interrupt-controller; >> >> > + #interrupt-cells = <1>; >> >> > + }; >> >> > }; >> >> > >> >> > /* >> >> > @@ -129,16 +156,25 @@ >> >> > reg = <0x2000 0 0 0 0>; >> >> > #address-cells = <3>; >> >> > #size-cells = <2>; >> >> > + interrupt-names = "intx"; >> >> > + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; >> >> > #interrupt-cells = <1>; >> >> > ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 >> >> > 0x81000000 0 0 0x81000000 0x4 0 1 0>; >> >> > bus-range = <0x00 0xff>; >> >> > - interrupt-map-mask = <0 0 0 0>; >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; >> >> > + interrupt-map-mask = <0 0 0 7>; >> >> > + interrupt-map = <0 0 0 1 &pcie4_intc 0>, >> >> > + <0 0 0 2 &pcie4_intc 1>, >> >> > + <0 0 0 3 &pcie4_intc 2>, >> >> > + <0 0 0 4 &pcie4_intc 3>; >> >> > marvell,pcie-port = <3>; >> >> > marvell,pcie-lane = <0>; >> >> > clocks = <&gateclk 7>; >> >> > status = "disabled"; >> >> > + pcie4_intc: interrupt-controller { >> >> > + interrupt-controller; >> >> > + #interrupt-cells = <1>; >> >> > + }; >> >> > }; >> >> > }; >> >> > }; >> >> > -- >> >> > 2.20.1 >> >> > >> >> >> >> -- >> >> Gregory Clement, Bootlin >> >> Embedded Linux and Kernel engineering >> >> http://bootlin.com >> >> -- >> Gregory Clement, Bootlin >> Embedded Linux and Kernel engineering >> http://bootlin.com ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe legacy INTx interrupts 2022-02-15 10:48 ` Luís Mendes @ 2022-02-15 10:52 ` Pali Rohár 2022-02-18 21:53 ` Luís Mendes 0 siblings, 1 reply; 13+ messages in thread From: Pali Rohár @ 2022-02-15 10:52 UTC (permalink / raw) To: Luís Mendes Cc: Gregory CLEMENT, Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King, Andrew Lunn, Linux PCI, Linux Kernel Mailing List, linux-arm-kernel, devicetree Hello! armada-388.dtsi file has #include "armada-385.dtsi" line and therefore is already covered by this my patch. Gregory's question was about A380. But if you want, you can test this patch series (which already covers A388) on your A388 HW. It is still better to do tests on more HW. On Tuesday 15 February 2022 10:48:17 Luís Mendes wrote: > Hello, > > Sorry for jumping in the conversation, but I read this thread and I > have an Armada A388 HW so I can test it, if desired. > > Luís > > > On Tue, Feb 15, 2022 at 10:47 AM Luís Mendes <luis.p.mendes@gmail.com> wrote: > > > > Hello, > > > > Sorry for jumping in the conversation, but I read this thread and I have an Armada A388 HW so I can test it, if desired. > > > > Luís > > > > On Mon, Feb 14, 2022 at 7:57 PM Gregory CLEMENT <gregory.clement@bootlin.com> wrote: > >> > >> Hello, > >> > >> > On Monday 14 February 2022 16:07:13 Gregory CLEMENT wrote: > >> >> Hello Pali, > >> >> > >> >> > With this change legacy INTA, INTB, INTC and INTD interrupts are reported > >> >> > separately and not mixed into one Linux virq source anymore. > >> >> > > >> >> > Signed-off-by: Pali Rohár <pali@kernel.org> > >> >> > --- > >> >> > arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++----- > >> >> > >> >> Is there any reason for not doing the same change in armada-380.dtsi ? > >> > > >> > I do not have A380 HW, so I did this change only for A385 which I have > >> > tested. > >> > >> OK fair enough. > >> > >> So you can add my > >> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> > >> > >> Moreover to keep biscetability this patch should be merged after the > >> support in the driver. So the easier is to let merge it through the PCI > >> subsystem with the other patches from this series. I do not think there > >> will be any other changes in this file so there won't be any merge > >> conflicts. > >> > >> Thanks, > >> > >> Grégory > >> > >> > >> > > >> >> Grégory > >> >> > >> >> > 1 file changed, 44 insertions(+), 8 deletions(-) > >> >> > > >> >> > diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi > >> >> > index f0022d10c715..83392b92dae2 100644 > >> >> > --- a/arch/arm/boot/dts/armada-385.dtsi > >> >> > +++ b/arch/arm/boot/dts/armada-385.dtsi > >> >> > @@ -69,16 +69,25 @@ > >> >> > reg = <0x0800 0 0 0 0>; > >> >> > #address-cells = <3>; > >> >> > #size-cells = <2>; > >> >> > + interrupt-names = "intx"; > >> >> > + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > >> >> > #interrupt-cells = <1>; > >> >> > ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 > >> >> > 0x81000000 0 0 0x81000000 0x1 0 1 0>; > >> >> > bus-range = <0x00 0xff>; > >> >> > - interrupt-map-mask = <0 0 0 0>; > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > >> >> > + interrupt-map-mask = <0 0 0 7>; > >> >> > + interrupt-map = <0 0 0 1 &pcie1_intc 0>, > >> >> > + <0 0 0 2 &pcie1_intc 1>, > >> >> > + <0 0 0 3 &pcie1_intc 2>, > >> >> > + <0 0 0 4 &pcie1_intc 3>; > >> >> > marvell,pcie-port = <0>; > >> >> > marvell,pcie-lane = <0>; > >> >> > clocks = <&gateclk 8>; > >> >> > status = "disabled"; > >> >> > + pcie1_intc: interrupt-controller { > >> >> > + interrupt-controller; > >> >> > + #interrupt-cells = <1>; > >> >> > + }; > >> >> > }; > >> >> > > >> >> > /* x1 port */ > >> >> > @@ -88,16 +97,25 @@ > >> >> > reg = <0x1000 0 0 0 0>; > >> >> > #address-cells = <3>; > >> >> > #size-cells = <2>; > >> >> > + interrupt-names = "intx"; > >> >> > + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > >> >> > #interrupt-cells = <1>; > >> >> > ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 > >> >> > 0x81000000 0 0 0x81000000 0x2 0 1 0>; > >> >> > bus-range = <0x00 0xff>; > >> >> > - interrupt-map-mask = <0 0 0 0>; > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > >> >> > + interrupt-map-mask = <0 0 0 7>; > >> >> > + interrupt-map = <0 0 0 1 &pcie2_intc 0>, > >> >> > + <0 0 0 2 &pcie2_intc 1>, > >> >> > + <0 0 0 3 &pcie2_intc 2>, > >> >> > + <0 0 0 4 &pcie2_intc 3>; > >> >> > marvell,pcie-port = <1>; > >> >> > marvell,pcie-lane = <0>; > >> >> > clocks = <&gateclk 5>; > >> >> > status = "disabled"; > >> >> > + pcie2_intc: interrupt-controller { > >> >> > + interrupt-controller; > >> >> > + #interrupt-cells = <1>; > >> >> > + }; > >> >> > }; > >> >> > > >> >> > /* x1 port */ > >> >> > @@ -107,16 +125,25 @@ > >> >> > reg = <0x1800 0 0 0 0>; > >> >> > #address-cells = <3>; > >> >> > #size-cells = <2>; > >> >> > + interrupt-names = "intx"; > >> >> > + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > >> >> > #interrupt-cells = <1>; > >> >> > ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 > >> >> > 0x81000000 0 0 0x81000000 0x3 0 1 0>; > >> >> > bus-range = <0x00 0xff>; > >> >> > - interrupt-map-mask = <0 0 0 0>; > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > >> >> > + interrupt-map-mask = <0 0 0 7>; > >> >> > + interrupt-map = <0 0 0 1 &pcie3_intc 0>, > >> >> > + <0 0 0 2 &pcie3_intc 1>, > >> >> > + <0 0 0 3 &pcie3_intc 2>, > >> >> > + <0 0 0 4 &pcie3_intc 3>; > >> >> > marvell,pcie-port = <2>; > >> >> > marvell,pcie-lane = <0>; > >> >> > clocks = <&gateclk 6>; > >> >> > status = "disabled"; > >> >> > + pcie3_intc: interrupt-controller { > >> >> > + interrupt-controller; > >> >> > + #interrupt-cells = <1>; > >> >> > + }; > >> >> > }; > >> >> > > >> >> > /* > >> >> > @@ -129,16 +156,25 @@ > >> >> > reg = <0x2000 0 0 0 0>; > >> >> > #address-cells = <3>; > >> >> > #size-cells = <2>; > >> >> > + interrupt-names = "intx"; > >> >> > + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > >> >> > #interrupt-cells = <1>; > >> >> > ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 > >> >> > 0x81000000 0 0 0x81000000 0x4 0 1 0>; > >> >> > bus-range = <0x00 0xff>; > >> >> > - interrupt-map-mask = <0 0 0 0>; > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > >> >> > + interrupt-map-mask = <0 0 0 7>; > >> >> > + interrupt-map = <0 0 0 1 &pcie4_intc 0>, > >> >> > + <0 0 0 2 &pcie4_intc 1>, > >> >> > + <0 0 0 3 &pcie4_intc 2>, > >> >> > + <0 0 0 4 &pcie4_intc 3>; > >> >> > marvell,pcie-port = <3>; > >> >> > marvell,pcie-lane = <0>; > >> >> > clocks = <&gateclk 7>; > >> >> > status = "disabled"; > >> >> > + pcie4_intc: interrupt-controller { > >> >> > + interrupt-controller; > >> >> > + #interrupt-cells = <1>; > >> >> > + }; > >> >> > }; > >> >> > }; > >> >> > }; > >> >> > -- > >> >> > 2.20.1 > >> >> > > >> >> > >> >> -- > >> >> Gregory Clement, Bootlin > >> >> Embedded Linux and Kernel engineering > >> >> http://bootlin.com > >> > >> -- > >> Gregory Clement, Bootlin > >> Embedded Linux and Kernel engineering > >> http://bootlin.com ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe legacy INTx interrupts 2022-02-15 10:52 ` Pali Rohár @ 2022-02-18 21:53 ` Luís Mendes 2022-02-19 13:36 ` Pali Rohár 0 siblings, 1 reply; 13+ messages in thread From: Luís Mendes @ 2022-02-18 21:53 UTC (permalink / raw) To: Pali Rohár Cc: Gregory CLEMENT, Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King, Andrew Lunn, Linux PCI, Linux Kernel Mailing List, linux-arm-kernel, devicetree Successfully tested on my custom A388 system with two PCI express slots. If you wish you can add a: Tested-by: Luis Mendes <luis.p.mendes@gmail.com> On Tue, Feb 15, 2022 at 10:52 AM Pali Rohár <pali@kernel.org> wrote: > > Hello! armada-388.dtsi file has #include "armada-385.dtsi" line and > therefore is already covered by this my patch. > > Gregory's question was about A380. > > But if you want, you can test this patch series (which already covers > A388) on your A388 HW. It is still better to do tests on more HW. > > On Tuesday 15 February 2022 10:48:17 Luís Mendes wrote: > > Hello, > > > > Sorry for jumping in the conversation, but I read this thread and I > > have an Armada A388 HW so I can test it, if desired. > > > > Luís > > > > > > On Tue, Feb 15, 2022 at 10:47 AM Luís Mendes <luis.p.mendes@gmail.com> wrote: > > > > > > Hello, > > > > > > Sorry for jumping in the conversation, but I read this thread and I have an Armada A388 HW so I can test it, if desired. > > > > > > Luís > > > > > > On Mon, Feb 14, 2022 at 7:57 PM Gregory CLEMENT <gregory.clement@bootlin.com> wrote: > > >> > > >> Hello, > > >> > > >> > On Monday 14 February 2022 16:07:13 Gregory CLEMENT wrote: > > >> >> Hello Pali, > > >> >> > > >> >> > With this change legacy INTA, INTB, INTC and INTD interrupts are reported > > >> >> > separately and not mixed into one Linux virq source anymore. > > >> >> > > > >> >> > Signed-off-by: Pali Rohár <pali@kernel.org> > > >> >> > --- > > >> >> > arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++----- > > >> >> > > >> >> Is there any reason for not doing the same change in armada-380.dtsi ? > > >> > > > >> > I do not have A380 HW, so I did this change only for A385 which I have > > >> > tested. > > >> > > >> OK fair enough. > > >> > > >> So you can add my > > >> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> > > >> > > >> Moreover to keep biscetability this patch should be merged after the > > >> support in the driver. So the easier is to let merge it through the PCI > > >> subsystem with the other patches from this series. I do not think there > > >> will be any other changes in this file so there won't be any merge > > >> conflicts. > > >> > > >> Thanks, > > >> > > >> Grégory > > >> > > >> > > >> > > > >> >> Grégory > > >> >> > > >> >> > 1 file changed, 44 insertions(+), 8 deletions(-) > > >> >> > > > >> >> > diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi > > >> >> > index f0022d10c715..83392b92dae2 100644 > > >> >> > --- a/arch/arm/boot/dts/armada-385.dtsi > > >> >> > +++ b/arch/arm/boot/dts/armada-385.dtsi > > >> >> > @@ -69,16 +69,25 @@ > > >> >> > reg = <0x0800 0 0 0 0>; > > >> >> > #address-cells = <3>; > > >> >> > #size-cells = <2>; > > >> >> > + interrupt-names = "intx"; > > >> >> > + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > > >> >> > #interrupt-cells = <1>; > > >> >> > ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 > > >> >> > 0x81000000 0 0 0x81000000 0x1 0 1 0>; > > >> >> > bus-range = <0x00 0xff>; > > >> >> > - interrupt-map-mask = <0 0 0 0>; > > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > > >> >> > + interrupt-map-mask = <0 0 0 7>; > > >> >> > + interrupt-map = <0 0 0 1 &pcie1_intc 0>, > > >> >> > + <0 0 0 2 &pcie1_intc 1>, > > >> >> > + <0 0 0 3 &pcie1_intc 2>, > > >> >> > + <0 0 0 4 &pcie1_intc 3>; > > >> >> > marvell,pcie-port = <0>; > > >> >> > marvell,pcie-lane = <0>; > > >> >> > clocks = <&gateclk 8>; > > >> >> > status = "disabled"; > > >> >> > + pcie1_intc: interrupt-controller { > > >> >> > + interrupt-controller; > > >> >> > + #interrupt-cells = <1>; > > >> >> > + }; > > >> >> > }; > > >> >> > > > >> >> > /* x1 port */ > > >> >> > @@ -88,16 +97,25 @@ > > >> >> > reg = <0x1000 0 0 0 0>; > > >> >> > #address-cells = <3>; > > >> >> > #size-cells = <2>; > > >> >> > + interrupt-names = "intx"; > > >> >> > + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > > >> >> > #interrupt-cells = <1>; > > >> >> > ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 > > >> >> > 0x81000000 0 0 0x81000000 0x2 0 1 0>; > > >> >> > bus-range = <0x00 0xff>; > > >> >> > - interrupt-map-mask = <0 0 0 0>; > > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > > >> >> > + interrupt-map-mask = <0 0 0 7>; > > >> >> > + interrupt-map = <0 0 0 1 &pcie2_intc 0>, > > >> >> > + <0 0 0 2 &pcie2_intc 1>, > > >> >> > + <0 0 0 3 &pcie2_intc 2>, > > >> >> > + <0 0 0 4 &pcie2_intc 3>; > > >> >> > marvell,pcie-port = <1>; > > >> >> > marvell,pcie-lane = <0>; > > >> >> > clocks = <&gateclk 5>; > > >> >> > status = "disabled"; > > >> >> > + pcie2_intc: interrupt-controller { > > >> >> > + interrupt-controller; > > >> >> > + #interrupt-cells = <1>; > > >> >> > + }; > > >> >> > }; > > >> >> > > > >> >> > /* x1 port */ > > >> >> > @@ -107,16 +125,25 @@ > > >> >> > reg = <0x1800 0 0 0 0>; > > >> >> > #address-cells = <3>; > > >> >> > #size-cells = <2>; > > >> >> > + interrupt-names = "intx"; > > >> >> > + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > > >> >> > #interrupt-cells = <1>; > > >> >> > ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 > > >> >> > 0x81000000 0 0 0x81000000 0x3 0 1 0>; > > >> >> > bus-range = <0x00 0xff>; > > >> >> > - interrupt-map-mask = <0 0 0 0>; > > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > > >> >> > + interrupt-map-mask = <0 0 0 7>; > > >> >> > + interrupt-map = <0 0 0 1 &pcie3_intc 0>, > > >> >> > + <0 0 0 2 &pcie3_intc 1>, > > >> >> > + <0 0 0 3 &pcie3_intc 2>, > > >> >> > + <0 0 0 4 &pcie3_intc 3>; > > >> >> > marvell,pcie-port = <2>; > > >> >> > marvell,pcie-lane = <0>; > > >> >> > clocks = <&gateclk 6>; > > >> >> > status = "disabled"; > > >> >> > + pcie3_intc: interrupt-controller { > > >> >> > + interrupt-controller; > > >> >> > + #interrupt-cells = <1>; > > >> >> > + }; > > >> >> > }; > > >> >> > > > >> >> > /* > > >> >> > @@ -129,16 +156,25 @@ > > >> >> > reg = <0x2000 0 0 0 0>; > > >> >> > #address-cells = <3>; > > >> >> > #size-cells = <2>; > > >> >> > + interrupt-names = "intx"; > > >> >> > + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > > >> >> > #interrupt-cells = <1>; > > >> >> > ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 > > >> >> > 0x81000000 0 0 0x81000000 0x4 0 1 0>; > > >> >> > bus-range = <0x00 0xff>; > > >> >> > - interrupt-map-mask = <0 0 0 0>; > > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > > >> >> > + interrupt-map-mask = <0 0 0 7>; > > >> >> > + interrupt-map = <0 0 0 1 &pcie4_intc 0>, > > >> >> > + <0 0 0 2 &pcie4_intc 1>, > > >> >> > + <0 0 0 3 &pcie4_intc 2>, > > >> >> > + <0 0 0 4 &pcie4_intc 3>; > > >> >> > marvell,pcie-port = <3>; > > >> >> > marvell,pcie-lane = <0>; > > >> >> > clocks = <&gateclk 7>; > > >> >> > status = "disabled"; > > >> >> > + pcie4_intc: interrupt-controller { > > >> >> > + interrupt-controller; > > >> >> > + #interrupt-cells = <1>; > > >> >> > + }; > > >> >> > }; > > >> >> > }; > > >> >> > }; > > >> >> > -- > > >> >> > 2.20.1 > > >> >> > > > >> >> > > >> >> -- > > >> >> Gregory Clement, Bootlin > > >> >> Embedded Linux and Kernel engineering > > >> >> http://bootlin.com > > >> > > >> -- > > >> Gregory Clement, Bootlin > > >> Embedded Linux and Kernel engineering > > >> http://bootlin.com ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe legacy INTx interrupts 2022-02-18 21:53 ` Luís Mendes @ 2022-02-19 13:36 ` Pali Rohár 0 siblings, 0 replies; 13+ messages in thread From: Pali Rohár @ 2022-02-19 13:36 UTC (permalink / raw) To: Luís Mendes Cc: Gregory CLEMENT, Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Thomas Petazzoni, Krzysztof Wilczyński, Marek Behún, Russell King, Andrew Lunn, Linux PCI, Linux Kernel Mailing List, linux-arm-kernel, devicetree Perfect, thanks! On Friday 18 February 2022 21:53:43 Luís Mendes wrote: > Successfully tested on my custom A388 system with two PCI express slots. > > If you wish you can add a: > Tested-by: Luis Mendes <luis.p.mendes@gmail.com> > > On Tue, Feb 15, 2022 at 10:52 AM Pali Rohár <pali@kernel.org> wrote: > > > > Hello! armada-388.dtsi file has #include "armada-385.dtsi" line and > > therefore is already covered by this my patch. > > > > Gregory's question was about A380. > > > > But if you want, you can test this patch series (which already covers > > A388) on your A388 HW. It is still better to do tests on more HW. > > > > On Tuesday 15 February 2022 10:48:17 Luís Mendes wrote: > > > Hello, > > > > > > Sorry for jumping in the conversation, but I read this thread and I > > > have an Armada A388 HW so I can test it, if desired. > > > > > > Luís > > > > > > > > > On Tue, Feb 15, 2022 at 10:47 AM Luís Mendes <luis.p.mendes@gmail.com> wrote: > > > > > > > > Hello, > > > > > > > > Sorry for jumping in the conversation, but I read this thread and I have an Armada A388 HW so I can test it, if desired. > > > > > > > > Luís > > > > > > > > On Mon, Feb 14, 2022 at 7:57 PM Gregory CLEMENT <gregory.clement@bootlin.com> wrote: > > > >> > > > >> Hello, > > > >> > > > >> > On Monday 14 February 2022 16:07:13 Gregory CLEMENT wrote: > > > >> >> Hello Pali, > > > >> >> > > > >> >> > With this change legacy INTA, INTB, INTC and INTD interrupts are reported > > > >> >> > separately and not mixed into one Linux virq source anymore. > > > >> >> > > > > >> >> > Signed-off-by: Pali Rohár <pali@kernel.org> > > > >> >> > --- > > > >> >> > arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++----- > > > >> >> > > > >> >> Is there any reason for not doing the same change in armada-380.dtsi ? > > > >> > > > > >> > I do not have A380 HW, so I did this change only for A385 which I have > > > >> > tested. > > > >> > > > >> OK fair enough. > > > >> > > > >> So you can add my > > > >> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> > > > >> > > > >> Moreover to keep biscetability this patch should be merged after the > > > >> support in the driver. So the easier is to let merge it through the PCI > > > >> subsystem with the other patches from this series. I do not think there > > > >> will be any other changes in this file so there won't be any merge > > > >> conflicts. > > > >> > > > >> Thanks, > > > >> > > > >> Grégory > > > >> > > > >> > > > >> > > > > >> >> Grégory > > > >> >> > > > >> >> > 1 file changed, 44 insertions(+), 8 deletions(-) > > > >> >> > > > > >> >> > diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi > > > >> >> > index f0022d10c715..83392b92dae2 100644 > > > >> >> > --- a/arch/arm/boot/dts/armada-385.dtsi > > > >> >> > +++ b/arch/arm/boot/dts/armada-385.dtsi > > > >> >> > @@ -69,16 +69,25 @@ > > > >> >> > reg = <0x0800 0 0 0 0>; > > > >> >> > #address-cells = <3>; > > > >> >> > #size-cells = <2>; > > > >> >> > + interrupt-names = "intx"; > > > >> >> > + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > > > >> >> > #interrupt-cells = <1>; > > > >> >> > ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 > > > >> >> > 0x81000000 0 0 0x81000000 0x1 0 1 0>; > > > >> >> > bus-range = <0x00 0xff>; > > > >> >> > - interrupt-map-mask = <0 0 0 0>; > > > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > > > >> >> > + interrupt-map-mask = <0 0 0 7>; > > > >> >> > + interrupt-map = <0 0 0 1 &pcie1_intc 0>, > > > >> >> > + <0 0 0 2 &pcie1_intc 1>, > > > >> >> > + <0 0 0 3 &pcie1_intc 2>, > > > >> >> > + <0 0 0 4 &pcie1_intc 3>; > > > >> >> > marvell,pcie-port = <0>; > > > >> >> > marvell,pcie-lane = <0>; > > > >> >> > clocks = <&gateclk 8>; > > > >> >> > status = "disabled"; > > > >> >> > + pcie1_intc: interrupt-controller { > > > >> >> > + interrupt-controller; > > > >> >> > + #interrupt-cells = <1>; > > > >> >> > + }; > > > >> >> > }; > > > >> >> > > > > >> >> > /* x1 port */ > > > >> >> > @@ -88,16 +97,25 @@ > > > >> >> > reg = <0x1000 0 0 0 0>; > > > >> >> > #address-cells = <3>; > > > >> >> > #size-cells = <2>; > > > >> >> > + interrupt-names = "intx"; > > > >> >> > + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > > > >> >> > #interrupt-cells = <1>; > > > >> >> > ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 > > > >> >> > 0x81000000 0 0 0x81000000 0x2 0 1 0>; > > > >> >> > bus-range = <0x00 0xff>; > > > >> >> > - interrupt-map-mask = <0 0 0 0>; > > > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > > > >> >> > + interrupt-map-mask = <0 0 0 7>; > > > >> >> > + interrupt-map = <0 0 0 1 &pcie2_intc 0>, > > > >> >> > + <0 0 0 2 &pcie2_intc 1>, > > > >> >> > + <0 0 0 3 &pcie2_intc 2>, > > > >> >> > + <0 0 0 4 &pcie2_intc 3>; > > > >> >> > marvell,pcie-port = <1>; > > > >> >> > marvell,pcie-lane = <0>; > > > >> >> > clocks = <&gateclk 5>; > > > >> >> > status = "disabled"; > > > >> >> > + pcie2_intc: interrupt-controller { > > > >> >> > + interrupt-controller; > > > >> >> > + #interrupt-cells = <1>; > > > >> >> > + }; > > > >> >> > }; > > > >> >> > > > > >> >> > /* x1 port */ > > > >> >> > @@ -107,16 +125,25 @@ > > > >> >> > reg = <0x1800 0 0 0 0>; > > > >> >> > #address-cells = <3>; > > > >> >> > #size-cells = <2>; > > > >> >> > + interrupt-names = "intx"; > > > >> >> > + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > > > >> >> > #interrupt-cells = <1>; > > > >> >> > ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 > > > >> >> > 0x81000000 0 0 0x81000000 0x3 0 1 0>; > > > >> >> > bus-range = <0x00 0xff>; > > > >> >> > - interrupt-map-mask = <0 0 0 0>; > > > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > > > >> >> > + interrupt-map-mask = <0 0 0 7>; > > > >> >> > + interrupt-map = <0 0 0 1 &pcie3_intc 0>, > > > >> >> > + <0 0 0 2 &pcie3_intc 1>, > > > >> >> > + <0 0 0 3 &pcie3_intc 2>, > > > >> >> > + <0 0 0 4 &pcie3_intc 3>; > > > >> >> > marvell,pcie-port = <2>; > > > >> >> > marvell,pcie-lane = <0>; > > > >> >> > clocks = <&gateclk 6>; > > > >> >> > status = "disabled"; > > > >> >> > + pcie3_intc: interrupt-controller { > > > >> >> > + interrupt-controller; > > > >> >> > + #interrupt-cells = <1>; > > > >> >> > + }; > > > >> >> > }; > > > >> >> > > > > >> >> > /* > > > >> >> > @@ -129,16 +156,25 @@ > > > >> >> > reg = <0x2000 0 0 0 0>; > > > >> >> > #address-cells = <3>; > > > >> >> > #size-cells = <2>; > > > >> >> > + interrupt-names = "intx"; > > > >> >> > + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > > > >> >> > #interrupt-cells = <1>; > > > >> >> > ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 > > > >> >> > 0x81000000 0 0 0x81000000 0x4 0 1 0>; > > > >> >> > bus-range = <0x00 0xff>; > > > >> >> > - interrupt-map-mask = <0 0 0 0>; > > > >> >> > - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > > > >> >> > + interrupt-map-mask = <0 0 0 7>; > > > >> >> > + interrupt-map = <0 0 0 1 &pcie4_intc 0>, > > > >> >> > + <0 0 0 2 &pcie4_intc 1>, > > > >> >> > + <0 0 0 3 &pcie4_intc 2>, > > > >> >> > + <0 0 0 4 &pcie4_intc 3>; > > > >> >> > marvell,pcie-port = <3>; > > > >> >> > marvell,pcie-lane = <0>; > > > >> >> > clocks = <&gateclk 7>; > > > >> >> > status = "disabled"; > > > >> >> > + pcie4_intc: interrupt-controller { > > > >> >> > + interrupt-controller; > > > >> >> > + #interrupt-cells = <1>; > > > >> >> > + }; > > > >> >> > }; > > > >> >> > }; > > > >> >> > }; > > > >> >> > -- > > > >> >> > 2.20.1 > > > >> >> > > > > >> >> > > > >> >> -- > > > >> >> Gregory Clement, Bootlin > > > >> >> Embedded Linux and Kernel engineering > > > >> >> http://bootlin.com > > > >> > > > >> -- > > > >> Gregory Clement, Bootlin > > > >> Embedded Linux and Kernel engineering > > > >> http://bootlin.com ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2022-02-19 13:36 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
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[not found] <20220105150239.9628-1-pali@kernel.org>
2022-01-05 15:02 ` [PATCH 04/11] dt-bindings: PCI: mvebu: Add num-lanes property Pali Rohár
2022-01-12 1:29 ` Rob Herring
2022-01-05 15:02 ` [PATCH 09/11] dt-bindings: PCI: mvebu: Update information about intx interrupts Pali Rohár
2022-01-12 1:30 ` Rob Herring
2022-01-05 15:02 ` [PATCH 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe legacy INTx interrupts Pali Rohár
[not found] ` <20220112151814.24361-1-pali@kernel.org>
2022-01-12 15:18 ` [PATCH v2 " Pali Rohár
2022-02-14 15:07 ` Gregory CLEMENT
2022-02-14 15:09 ` Pali Rohár
2022-02-14 15:26 ` Gregory CLEMENT
[not found] ` <CAEzXK1qYKVk7QiSY_DwqkZ7WV6WU06WBtiqZx0JJCc+mOP-7Kg@mail.gmail.com>
2022-02-15 10:48 ` Luís Mendes
2022-02-15 10:52 ` Pali Rohár
2022-02-18 21:53 ` Luís Mendes
2022-02-19 13:36 ` Pali Rohár
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