* [PATCH 0/6] drm/msm: add support for SM8450
@ 2023-01-04 9:08 Neil Armstrong
2023-01-04 9:08 ` [PATCH 1/6] dt-bindings: display/msm: document the SM8550 DSI PHY Neil Armstrong
` (6 more replies)
0 siblings, 7 replies; 23+ messages in thread
From: Neil Armstrong @ 2023-01-04 9:08 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Neil Armstrong
This adds support for the MDSS/DPU/DSI on the Qualcomm SM8550 platform.
This patchset is based on the SM8450 display support serie at [1].
In order to work, the following patchsets are required:
- PM8550 LDO fix at [2]
- DISPCC driver at [3]
+ the DT changes.
[1] https://lore.kernel.org/all/20221207012231.112059-1-dmitry.baryshkov@linaro.org/
[2] https://lore.kernel.org/all/20230102-topic-sm8550-upstream-fixes-reg-l11b-nldo-v1-1-d97def246338@linaro.org/
[3] https://lore.kernel.org/all/20230103-topic-sm8550-upstream-dispcc-v1-0-81bfcc26b2dc@linaro.org/
To: Rob Clark <robdclark@gmail.com>
To: Abhinav Kumar <quic_abhinavk@quicinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Sean Paul <sean@poorly.run>
To: David Airlie <airlied@gmail.com>
To: Daniel Vetter <daniel@ffwll.ch>
To: Rob Herring <robh+dt@kernel.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
To: Jonathan Marek <jonathan@marek.ca>
Cc: linux-arm-msm@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Cc: freedreno@lists.freedesktop.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Neil Armstrong (6):
dt-bindings: display/msm: document the SM8550 DSI PHY
dt-bindings: display/msm: document the display hardware for SM8550
drm/msm/dpu: add support for SM8550
drm/msm: mdss: add support for SM8550
drm/msm/dsi: add support for DSI-PHY on SM8550
drm/msm/dsi: add support for DSI 2.7.0
.../bindings/display/msm/dsi-phy-7nm.yaml | 1 +
.../bindings/display/msm/qcom,sm8550-dpu.yaml | 134 +++++++++
.../bindings/display/msm/qcom,sm8550-mdss.yaml | 331 +++++++++++++++++++++
drivers/gpu/drm/msm/Kconfig | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197 ++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 16 +
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 102 +++++--
drivers/gpu/drm/msm/msm_mdss.c | 2 +
14 files changed, 775 insertions(+), 20 deletions(-)
---
base-commit: d862fd95b9c924bd0a257f7708a6e3868d39ff43
change-id: 20230103-topic-sm8550-upstream-mdss-dsi-35ca8acea529
Best regards,
--
Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 1/6] dt-bindings: display/msm: document the SM8550 DSI PHY
2023-01-04 9:08 [PATCH 0/6] drm/msm: add support for SM8450 Neil Armstrong
@ 2023-01-04 9:08 ` Neil Armstrong
2023-01-06 15:41 ` Krzysztof Kozlowski
2023-01-04 9:08 ` [PATCH 2/6] dt-bindings: display/msm: document the display hardware for SM8550 Neil Armstrong
` (5 subsequent siblings)
6 siblings, 1 reply; 23+ messages in thread
From: Neil Armstrong @ 2023-01-04 9:08 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Neil Armstrong
Document the SM8550 DSI PHY which is very close from the 7nm
and 5nm DSI PHYs found in earlier platforms.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
index bffd161fedfd..f72727f81076 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
@@ -15,6 +15,7 @@ allOf:
properties:
compatible:
enum:
+ - qcom,dsi-phy-4nm-8550
- qcom,dsi-phy-5nm-8350
- qcom,dsi-phy-5nm-8450
- qcom,dsi-phy-7nm
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 2/6] dt-bindings: display/msm: document the display hardware for SM8550
2023-01-04 9:08 [PATCH 0/6] drm/msm: add support for SM8450 Neil Armstrong
2023-01-04 9:08 ` [PATCH 1/6] dt-bindings: display/msm: document the SM8550 DSI PHY Neil Armstrong
@ 2023-01-04 9:08 ` Neil Armstrong
2023-01-05 2:53 ` Rob Herring
2023-01-08 23:11 ` Dmitry Baryshkov
2023-01-04 9:08 ` [PATCH 3/6] drm/msm/dpu: add support " Neil Armstrong
` (4 subsequent siblings)
6 siblings, 2 replies; 23+ messages in thread
From: Neil Armstrong @ 2023-01-04 9:08 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Neil Armstrong
Document the MDSS and DPU blocks found on the Qualcomm SM8550
platform.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
.../bindings/display/msm/qcom,sm8550-dpu.yaml | 134 +++++++++
.../bindings/display/msm/qcom,sm8550-mdss.yaml | 331 +++++++++++++++++++++
2 files changed, 465 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml
new file mode 100644
index 000000000000..c3d5a98fe3c0
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8550 Display DPU
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,sm8550-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display AHB
+ - description: Display hf axi
+ - description: Display MDSS ahb
+ - description: Display lut
+ - description: Display core
+ - description: Display vsync
+
+ clock-names:
+ items:
+ - const: bus
+ - const: nrt_bus
+ - const: iface
+ - const: lut
+ - const: core
+ - const: vsync
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
+ #include <dt-bindings/clock/qcom,sm8550-gcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interconnect/qcom,sm8550.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm8550-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM8550_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-325000000 {
+ opp-hz = /bits/ 64 <325000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-514000000 {
+ opp-hz = /bits/ 64 <514000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml
new file mode 100644
index 000000000000..71b5b5f75969
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml
@@ -0,0 +1,331 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8550 Display MDSS
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+
+description:
+ SM8550 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
+ DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,sm8550-mdss
+
+ clocks:
+ items:
+ - description: Display MDSS AHB
+ - description: Display AHB
+ - description: Display hf AXI
+ - description: Display core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm8550-dpu
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,dsi-phy-4nm-8550
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
+ #include <dt-bindings/clock/qcom,sm8550-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interconnect/qcom,sm8550.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-subsystem@ae00000 {
+ compatible = "qcom,sm8550-mdss";
+ reg = <0x0ae00000 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
+ <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "nrt_bus", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x1c00 0x2>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm8550-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM8550_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-325000000 {
+ opp-hz = /bits/ 64 <325000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-514000000 {
+ opp-hz = /bits/ 64 <514000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ dsi@ae94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SM8550_MMCX>;
+
+ phys = <&dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+
+ dsi_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ dsi0_phy: phy@ae94400 {
+ compatible = "qcom,dsi-phy-4nm-8550";
+ reg = <0x0ae95000 0x200>,
+ <0x0ae95200 0x280>,
+ <0x0ae95500 0x400>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+
+ dsi@ae96000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae96000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <5>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC1_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SM8550_MMCX>;
+
+ phys = <&dsi1_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi1_in: endpoint {
+ remote-endpoint = <&dpu_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi1_phy: phy@ae96400 {
+ compatible = "qcom,dsi-phy-4nm-8550";
+ reg = <0x0ae97000 0x200>,
+ <0x0ae97200 0x280>,
+ <0x0ae97500 0x400>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+ };
+...
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 3/6] drm/msm/dpu: add support for SM8550
2023-01-04 9:08 [PATCH 0/6] drm/msm: add support for SM8450 Neil Armstrong
2023-01-04 9:08 ` [PATCH 1/6] dt-bindings: display/msm: document the SM8550 DSI PHY Neil Armstrong
2023-01-04 9:08 ` [PATCH 2/6] dt-bindings: display/msm: document the display hardware for SM8550 Neil Armstrong
@ 2023-01-04 9:08 ` Neil Armstrong
2023-01-04 9:45 ` Dmitry Baryshkov
2023-01-08 23:12 ` Dmitry Baryshkov
2023-01-04 9:08 ` [PATCH 4/6] drm/msm: mdss: " Neil Armstrong
` (3 subsequent siblings)
6 siblings, 2 replies; 23+ messages in thread
From: Neil Armstrong @ 2023-01-04 9:08 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Neil Armstrong
Add definitions for the display hardware used on Qualcomm SM8550
platform.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197 +++++++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
4 files changed, 201 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index b4ca123d8e69..adf5e25269dc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -402,6 +402,20 @@ static const struct dpu_caps sm8450_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
+static const struct dpu_caps sm8550_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_40,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 5120,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
static const struct dpu_caps sc7280_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
@@ -579,6 +593,37 @@ static const struct dpu_mdp_cfg sm8450_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sm8550_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0, .len = 0x494,
+ .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
+ .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x4330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+ .reg_off = 0x6330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+ .reg_off = 0x8330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+ .reg_off = 0xa330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x24330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+ .reg_off = 0x26330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA2] = {
+ .reg_off = 0x28330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA3] = {
+ .reg_off = 0x2a330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+ .reg_off = 0x2c330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+ .reg_off = 0x2e330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
+ .reg_off = 0x2bc, .bit_off = 20},
+ },
+};
+
static const struct dpu_mdp_cfg sc7280_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -776,6 +821,45 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = {
},
};
+static const struct dpu_ctl_cfg sm8550_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+ {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
static const struct dpu_ctl_cfg sc7280_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
@@ -1032,6 +1116,40 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
};
+static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 =
+ _VIG_SBLK("0", 7, DPU_SSPP_SCALER_QSEED3LITE);
+static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 =
+ _VIG_SBLK("1", 8, DPU_SSPP_SCALER_QSEED3LITE);
+static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 =
+ _VIG_SBLK("2", 9, DPU_SSPP_SCALER_QSEED3LITE);
+static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 =
+ _VIG_SBLK("3", 10, DPU_SSPP_SCALER_QSEED3LITE);
+static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK("12", 5);
+static const struct dpu_sspp_sub_blks sd8550_dma_sblk_5 = _DMA_SBLK("13", 6);
+
+static const struct dpu_sspp_cfg sm8550_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
+ sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK,
+ sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
+ SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK,
+ sm8550_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
+ SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK,
+ sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
+ sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_SDM845_MASK,
+ sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
+ SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_SDM845_MASK,
+ sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+ SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, DMA_CURSOR_SDM845_MASK,
+ sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
+ SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, DMA_CURSOR_SDM845_MASK,
+ sd8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
+};
+
static const struct dpu_sspp_cfg sc7280_sspp[] = {
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK,
sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
@@ -1268,6 +1386,16 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
.len = 0x20, .version = 0x20000},
};
+#define PP_BLK_DIPHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
+ {\
+ .name = _name, .id = _id, \
+ .base = _base, .len = 0, \
+ .features = BIT(DPU_PINGPONG_DITHER), \
+ .merge_3d = _merge_3d, \
+ .sblk = &_sblk, \
+ .intr_done = _done, \
+ .intr_rdptr = _rdptr, \
+ }
#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
{\
.name = _name, .id = _id, \
@@ -1371,6 +1499,33 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = {
-1),
};
+static const struct dpu_pingpong_cfg sm8550_pp[] = {
+ PP_BLK_DIPHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ -1),
+ PP_BLK_DIPHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ -1),
+ PP_BLK_DIPHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ -1),
+ PP_BLK_DIPHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ -1),
+ PP_BLK_DIPHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+ -1),
+ PP_BLK_DIPHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
+ -1),
+ PP_BLK_DIPHER("pingpong_6", PINGPONG_6, 0x66000, MERGE_3D_3, sc7280_pp_sblk,
+ -1,
+ -1),
+ PP_BLK_DIPHER("pingpong_7", PINGPONG_7, 0x66400, MERGE_3D_3, sc7280_pp_sblk,
+ -1,
+ -1),
+};
+
/*************************************************************
* MERGE_3D sub blocks config
*************************************************************/
@@ -1395,6 +1550,13 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00),
};
+static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = {
+ MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
+ MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
+ MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
+ MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x66700),
+};
+
/*************************************************************
* DSC sub blocks config
*************************************************************/
@@ -1481,6 +1643,14 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
};
+static const struct dpu_intf_cfg sm8550_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ /* TODO TE sub-blocks for intf1 & intf2 */
+ INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+ INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+};
+
/*************************************************************
* Writeback blocks config
*************************************************************/
@@ -2188,6 +2358,32 @@ static const struct dpu_mdss_cfg sm8450_dpu_cfg = {
.mdss_irqs = IRQ_SM8450_MASK,
};
+static const struct dpu_mdss_cfg sm8550_dpu_cfg = {
+ .caps = &sm8550_dpu_caps,
+ .mdp_count = ARRAY_SIZE(sm8550_mdp),
+ .mdp = sm8550_mdp,
+ .ctl_count = ARRAY_SIZE(sm8550_ctl),
+ .ctl = sm8550_ctl,
+ .sspp_count = ARRAY_SIZE(sm8550_sspp),
+ .sspp = sm8550_sspp,
+ .mixer_count = ARRAY_SIZE(sm8150_lm),
+ .mixer = sm8150_lm,
+ .dspp_count = ARRAY_SIZE(sm8150_dspp),
+ .dspp = sm8150_dspp,
+ .pingpong_count = ARRAY_SIZE(sm8550_pp),
+ .pingpong = sm8550_pp,
+ .merge_3d_count = ARRAY_SIZE(sm8550_merge_3d),
+ .merge_3d = sm8550_merge_3d,
+ .intf_count = ARRAY_SIZE(sm8550_intf),
+ .intf = sm8550_intf,
+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
+ .vbif = sdm845_vbif,
+ .reg_dma_count = 1,
+ .dma_cfg = &sm8450_regdma,
+ .perf = &sm8450_perf_data,
+ .mdss_irqs = IRQ_SM8450_MASK,
+};
+
static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
.caps = &sc7280_dpu_caps,
.mdp_count = ARRAY_SIZE(sc7280_mdp),
@@ -2248,6 +2444,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
{ .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
{ .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
{ .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg},
+ { .hw_rev = DPU_HW_VER_900, .dpu_cfg = &sm8550_dpu_cfg},
};
const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 29e7ea5840a2..7a8380f5c643 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -48,6 +48,7 @@
#define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
#define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
#define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */
+#define DPU_HW_VER_900 DPU_HW_VER(9, 0, 0) /* sm8550 */
#define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170)
#define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index 6d8e1bb3b3cc..dccad33532a9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -120,6 +120,8 @@ enum dpu_sspp {
SSPP_DMA1,
SSPP_DMA2,
SSPP_DMA3,
+ SSPP_DMA4,
+ SSPP_DMA5,
SSPP_CURSOR0,
SSPP_CURSOR1,
SSPP_MAX
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 0434cad511a4..18fefa116a56 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1303,6 +1303,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sm8150-dpu", },
{ .compatible = "qcom,sm8250-dpu", },
{ .compatible = "qcom,sm8450-dpu", },
+ { .compatible = "qcom,sm8550-dpu", },
{}
};
MODULE_DEVICE_TABLE(of, dpu_dt_match);
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 4/6] drm/msm: mdss: add support for SM8550
2023-01-04 9:08 [PATCH 0/6] drm/msm: add support for SM8450 Neil Armstrong
` (2 preceding siblings ...)
2023-01-04 9:08 ` [PATCH 3/6] drm/msm/dpu: add support " Neil Armstrong
@ 2023-01-04 9:08 ` Neil Armstrong
2023-01-04 9:46 ` Dmitry Baryshkov
2023-01-04 9:08 ` [PATCH 5/6] drm/msm/dsi: add support for DSI-PHY on SM8550 Neil Armstrong
` (2 subsequent siblings)
6 siblings, 1 reply; 23+ messages in thread
From: Neil Armstrong @ 2023-01-04 9:08 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Neil Armstrong
Add support for the MDSS block on SM8550 platform.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/gpu/drm/msm/msm_mdss.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 144c8dd82be1..54483fe30ffd 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -288,6 +288,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
break;
case DPU_HW_VER_810:
+ case DPU_HW_VER_900:
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1);
break;
@@ -521,6 +522,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sm8450-mdss" },
+ { .compatible = "qcom,sm8550-mdss" },
{}
};
MODULE_DEVICE_TABLE(of, mdss_dt_match);
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 5/6] drm/msm/dsi: add support for DSI-PHY on SM8550
2023-01-04 9:08 [PATCH 0/6] drm/msm: add support for SM8450 Neil Armstrong
` (3 preceding siblings ...)
2023-01-04 9:08 ` [PATCH 4/6] drm/msm: mdss: " Neil Armstrong
@ 2023-01-04 9:08 ` Neil Armstrong
2023-01-04 9:53 ` Dmitry Baryshkov
2023-01-04 9:08 ` [PATCH 6/6] drm/msm/dsi: add support for DSI 2.7.0 Neil Armstrong
2023-01-08 23:09 ` [PATCH 0/6] drm/msm: add support for SM8450 Dmitry Baryshkov
6 siblings, 1 reply; 23+ messages in thread
From: Neil Armstrong @ 2023-01-04 9:08 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Neil Armstrong
SM8550 use a 4nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle
4nm variant inside the common 5+7nm driver.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/gpu/drm/msm/Kconfig | 4 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 102 ++++++++++++++++++++++++------
4 files changed, 89 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index e7b100d97f88..949b18a29a55 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -140,11 +140,11 @@ config DRM_MSM_DSI_10NM_PHY
Choose this option if DSI PHY on SDM845 is used on the platform.
config DRM_MSM_DSI_7NM_PHY
- bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
+ bool "Enable DSI 7nm/5nm/4nm PHY driver in MSM DRM"
depends on DRM_MSM_DSI
default y
help
- Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280
+ Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SM8550/SC7280
is used on the platform.
config DRM_MSM_HDMI
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 0c956fdab23e..54e03cc9fbe7 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -573,6 +573,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
.data = &dsi_phy_5nm_8350_cfgs },
{ .compatible = "qcom,dsi-phy-5nm-8450",
.data = &dsi_phy_5nm_8450_cfgs },
+ { .compatible = "qcom,dsi-phy-4nm-8550",
+ .data = &dsi_phy_4nm_8550_cfgs },
#endif
{}
};
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index f7a907ed2b4b..58f9e09f5224 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -59,6 +59,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
struct msm_dsi_dphy_timing {
u32 clk_zero;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 7b2c16b3a36c..11629c431c30 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -47,6 +47,8 @@
#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2)
/* Hardware is V4.3 */
#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3)
+/* Hardware is V5.2 */
+#define DSI_PHY_7NM_QUIRK_V5_2 BIT(4)
struct dsi_pll_config {
bool enable_ssc;
@@ -124,14 +126,25 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config
if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
config->pll_clock_inverters = 0x28;
- else if (pll_freq <= 1000000000ULL)
- config->pll_clock_inverters = 0xa0;
- else if (pll_freq <= 2500000000ULL)
- config->pll_clock_inverters = 0x20;
- else if (pll_freq <= 3020000000ULL)
- config->pll_clock_inverters = 0x00;
- else
- config->pll_clock_inverters = 0x40;
+ else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
+ if (pll_freq <= 1300000000ULL)
+ config->pll_clock_inverters = 0xa0;
+ else if (pll_freq <= 2500000000ULL)
+ config->pll_clock_inverters = 0x20;
+ else if (pll_freq <= 4000000000ULL)
+ config->pll_clock_inverters = 0x00;
+ else
+ config->pll_clock_inverters = 0x40;
+ } else {
+ if (pll_freq <= 1000000000ULL)
+ config->pll_clock_inverters = 0xa0;
+ else if (pll_freq <= 2500000000ULL)
+ config->pll_clock_inverters = 0x20;
+ else if (pll_freq <= 3020000000ULL)
+ config->pll_clock_inverters = 0x00;
+ else
+ config->pll_clock_inverters = 0x40;
+ }
config->decimal_div_start = dec;
config->frac_div_start = frac;
@@ -222,6 +235,13 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
vco_config_1 = 0x01;
}
+ if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
+ if (pll->vco_current_rate < 1557000000ULL)
+ vco_config_1 = 0x08;
+ else
+ vco_config_1 = 0x01;
+ }
+
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
analog_controls_five_1);
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
@@ -860,7 +880,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
pr_warn("PLL turned on before configuring PHY\n");
/* Request for REFGEN READY */
- if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
+ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
+ (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
dsi_phy_write(phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1);
udelay(500);
}
@@ -881,20 +902,38 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
glbl_str_swi_cal_sel_ctrl = 0x00;
if (phy->cphy_mode) {
- vreg_ctrl_0 = 0x51;
- vreg_ctrl_1 = 0x55;
+ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
+ vreg_ctrl_0 = 0x45;
+ vreg_ctrl_1 = 0x45;
+ } else {
+ vreg_ctrl_0 = 0x51;
+ vreg_ctrl_1 = 0x55;
+ }
glbl_hstx_str_ctrl_0 = 0x00;
glbl_pemph_ctrl_0 = 0x11;
lane_ctrl0 = 0x17;
} else {
- vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
- vreg_ctrl_1 = 0x5c;
+ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
+ vreg_ctrl_0 = 0x44;
+ vreg_ctrl_1 = 0x19;
+ } else {
+ vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
+ vreg_ctrl_1 = 0x5c;
+ }
glbl_hstx_str_ctrl_0 = 0x88;
glbl_pemph_ctrl_0 = 0x00;
lane_ctrl0 = 0x1f;
}
- if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
+ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
+ if (phy->cphy_mode) {
+ glbl_rescode_top_ctrl = 0x00;
+ glbl_rescode_bot_ctrl = 0x00;
+ } else {
+ glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x03;
+ glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3c;
+ }
+ } else if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
if (phy->cphy_mode) {
glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b;
@@ -943,9 +982,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0x00);
/* program CMN_CTRL_4 for minor_ver 2 chipsets*/
- data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0);
- data = data & (0xf0);
- if (data == 0x20)
+ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
+ (dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) == 0x20)
dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_4, 0x04);
/* Configure PHY lane swap (TODO: we need to calculate this) */
@@ -1058,7 +1096,8 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
dsi_phy_hw_v4_0_config_lpcdrx(phy, false);
/* Turn off REFGEN Vote */
- if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
+ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
+ (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0);
wmb();
/* Delay to ensure HW removes vote before PHY shut down */
@@ -1092,6 +1131,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = {
{ .supply = "vdds", .init_load_uA = 97800 },
};
+static const struct regulator_bulk_data dsi_phy_7nm_98400uA_regulators[] = {
+ { .supply = "vdds", .init_load_uA = 98400 },
+};
+
const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
.has_phy_lane = true,
.regulator_data = dsi_phy_7nm_36mA_regulators,
@@ -1201,3 +1244,26 @@ const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = {
.num_dsi_phy = 2,
.quirks = DSI_PHY_7NM_QUIRK_V4_3,
};
+
+const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = {
+ .has_phy_lane = true,
+ .regulator_data = dsi_phy_7nm_98400uA_regulators,
+ .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98400uA_regulators),
+ .ops = {
+ .enable = dsi_7nm_phy_enable,
+ .disable = dsi_7nm_phy_disable,
+ .pll_init = dsi_pll_7nm_init,
+ .save_pll_state = dsi_7nm_pll_save_state,
+ .restore_pll_state = dsi_7nm_pll_restore_state,
+ .set_continuous_clock = dsi_7nm_set_continuous_clock,
+ },
+ .min_pll_rate = 600000000UL,
+#ifdef CONFIG_64BIT
+ .max_pll_rate = 5000000000UL,
+#else
+ .max_pll_rate = ULONG_MAX,
+#endif
+ .io_start = { 0xae95000, 0xae97000 },
+ .num_dsi_phy = 2,
+ .quirks = DSI_PHY_7NM_QUIRK_V5_2,
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 6/6] drm/msm/dsi: add support for DSI 2.7.0
2023-01-04 9:08 [PATCH 0/6] drm/msm: add support for SM8450 Neil Armstrong
` (4 preceding siblings ...)
2023-01-04 9:08 ` [PATCH 5/6] drm/msm/dsi: add support for DSI-PHY on SM8550 Neil Armstrong
@ 2023-01-04 9:08 ` Neil Armstrong
2023-01-04 9:54 ` Dmitry Baryshkov
2023-01-08 23:09 ` [PATCH 0/6] drm/msm: add support for SM8450 Dmitry Baryshkov
6 siblings, 1 reply; 23+ messages in thread
From: Neil Armstrong @ 2023-01-04 9:08 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Neil Armstrong
Add support for DSI 2.7.0 (block used on sm8550).
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 16 ++++++++++++++++
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 59a4cc95a251..33884ebd2f86 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -181,6 +181,20 @@ static const struct msm_dsi_config sdm845_dsi_cfg = {
.num_dsi = 2,
};
+static const struct regulator_bulk_data sm8550_dsi_regulators[] = {
+ { .supply = "vdda", .init_load_uA = 16800 }, /* 1.2 V */
+};
+
+static const struct msm_dsi_config sm8550_dsi_cfg = {
+ .io_offset = DSI_6G_REG_SHIFT,
+ .regulator_data = sm8550_dsi_regulators,
+ .num_regulators = ARRAY_SIZE(sm8550_dsi_regulators),
+ .bus_clk_names = dsi_sdm845_bus_clk_names,
+ .num_bus_clks = ARRAY_SIZE(dsi_sdm845_bus_clk_names),
+ .io_start = { 0xae94000, 0xae96000 },
+ .num_dsi = 2,
+};
+
static const struct regulator_bulk_data sc7180_dsi_regulators[] = {
{ .supply = "vdda", .init_load_uA = 21800 }, /* 1.2 V */
};
@@ -302,6 +316,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
&sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0,
&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
+ {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_7_0,
+ &sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops},
};
const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 95957fab499d..44be4a88aa83 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -26,6 +26,7 @@
#define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001
#define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000
#define MSM_DSI_6G_VER_MINOR_V2_6_0 0x20060000
+#define MSM_DSI_6G_VER_MINOR_V2_7_0 0x20070000
#define MSM_DSI_V2_VER_MINOR_8064 0x0
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 3/6] drm/msm/dpu: add support for SM8550
2023-01-04 9:08 ` [PATCH 3/6] drm/msm/dpu: add support " Neil Armstrong
@ 2023-01-04 9:45 ` Dmitry Baryshkov
2023-01-04 10:08 ` Neil Armstrong
2023-01-08 23:12 ` Dmitry Baryshkov
1 sibling, 1 reply; 23+ messages in thread
From: Dmitry Baryshkov @ 2023-01-04 9:45 UTC (permalink / raw)
To: Neil Armstrong, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 04/01/2023 11:08, Neil Armstrong wrote:
> Add definitions for the display hardware used on Qualcomm SM8550
> platform.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197 +++++++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 4 files changed, 201 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index b4ca123d8e69..adf5e25269dc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -402,6 +402,20 @@ static const struct dpu_caps sm8450_dpu_caps = {
> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> };
>
> +static const struct dpu_caps sm8550_dpu_caps = {
> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .max_mixer_blendstages = 0xb,
> + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
> + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> + .ubwc_version = DPU_HW_UBWC_VER_40,
> + .has_src_split = true,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .has_3d_merge = true,
> + .max_linewidth = 5120,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> static const struct dpu_caps sc7280_dpu_caps = {
> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> .max_mixer_blendstages = 0x7,
> @@ -579,6 +593,37 @@ static const struct dpu_mdp_cfg sm8450_mdp[] = {
> },
> };
>
> +static const struct dpu_mdp_cfg sm8550_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0, .len = 0x494,
> + .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
> + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> + .reg_off = 0x4330, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
> + .reg_off = 0x6330, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
> + .reg_off = 0x8330, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
> + .reg_off = 0xa330, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> + .reg_off = 0x24330, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
> + .reg_off = 0x26330, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_DMA2] = {
> + .reg_off = 0x28330, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_DMA3] = {
> + .reg_off = 0x2a330, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
> + .reg_off = 0x2c330, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
> + .reg_off = 0x2e330, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
> + .reg_off = 0x2bc, .bit_off = 20},
> + },
> +};
> +
> static const struct dpu_mdp_cfg sc7280_mdp[] = {
> {
> .name = "top_0", .id = MDP_TOP,
> @@ -776,6 +821,45 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = {
> },
> };
>
> +static const struct dpu_ctl_cfg sm8550_ctl[] = {
> + {
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x15000, .len = 0x290,?
> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE),
CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY) ?
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + },
> + {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x16000, .len = 0x290,
> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + },
> + {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x17000, .len = 0x290,
> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
CTL_SC7280_MASK?
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + },
> + {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x18000, .len = 0x290,
> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + },
> + {
> + .name = "ctl_4", .id = CTL_4,
> + .base = 0x19000, .len = 0x290,
> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> + },
> + {
> + .name = "ctl_5", .id = CTL_5,
> + .base = 0x1a000, .len = 0x290,
> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> + },
> +};
> +
> static const struct dpu_ctl_cfg sc7280_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> @@ -1032,6 +1116,40 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
> };
>
> +static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 =
> + _VIG_SBLK("0", 7, DPU_SSPP_SCALER_QSEED3LITE);
> +static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 =
> + _VIG_SBLK("1", 8, DPU_SSPP_SCALER_QSEED3LITE);
> +static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 =
> + _VIG_SBLK("2", 9, DPU_SSPP_SCALER_QSEED3LITE);
> +static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 =
> + _VIG_SBLK("3", 10, DPU_SSPP_SCALER_QSEED3LITE);
> +static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK("12", 5);
> +static const struct dpu_sspp_sub_blks sd8550_dma_sblk_5 = _DMA_SBLK("13", 6);
> +
> +static const struct dpu_sspp_cfg sm8550_sspp[] = {
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
> + sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK,
> + sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK,
> + sm8550_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK,
> + sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_SDM845_MASK,
> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_SDM845_MASK,
> + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> + SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, DMA_CURSOR_SDM845_MASK,
> + sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
> + SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, DMA_CURSOR_SDM845_MASK,
> + sd8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
> +};
> +
> static const struct dpu_sspp_cfg sc7280_sspp[] = {
> SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK,
> sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> @@ -1268,6 +1386,16 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
> .len = 0x20, .version = 0x20000},
> };
>
> +#define PP_BLK_DIPHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
> + {\
> + .name = _name, .id = _id, \
> + .base = _base, .len = 0, \
len = 0 looks incorrect. Any particular reason why can't we use plain
PP_BLK here?
> + .features = BIT(DPU_PINGPONG_DITHER), \
> + .merge_3d = _merge_3d, \
> + .sblk = &_sblk, \
> + .intr_done = _done, \
> + .intr_rdptr = _rdptr, \
> + }
> #define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
> {\
> .name = _name, .id = _id, \
> @@ -1371,6 +1499,33 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = {
> -1),
> };
>
> +static const struct dpu_pingpong_cfg sm8550_pp[] = {
> + PP_BLK_DIPHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + -1),
> + PP_BLK_DIPHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + -1),
> + PP_BLK_DIPHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> + -1),
> + PP_BLK_DIPHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> + -1),
> + PP_BLK_DIPHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> + -1),
> + PP_BLK_DIPHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> + -1),
> + PP_BLK_DIPHER("pingpong_6", PINGPONG_6, 0x66000, MERGE_3D_3, sc7280_pp_sblk,
> + -1,
> + -1),
> + PP_BLK_DIPHER("pingpong_7", PINGPONG_7, 0x66400, MERGE_3D_3, sc7280_pp_sblk,
> + -1,
> + -1),
> +};
> +
> /*************************************************************
> * MERGE_3D sub blocks config
> *************************************************************/
> @@ -1395,6 +1550,13 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
> MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00),
> };
>
> +static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = {
> + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
> + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
> + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
> + MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x66700),
> +};
> +
> /*************************************************************
> * DSC sub blocks config
> *************************************************************/
> @@ -1481,6 +1643,14 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
> INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> };
>
> +static const struct dpu_intf_cfg sm8550_intf[] = {
> + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> + /* TODO TE sub-blocks for intf1 & intf2 */
> + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> +};
> +
> /*************************************************************
> * Writeback blocks config
> *************************************************************/
> @@ -2188,6 +2358,32 @@ static const struct dpu_mdss_cfg sm8450_dpu_cfg = {
> .mdss_irqs = IRQ_SM8450_MASK,
> };
>
> +static const struct dpu_mdss_cfg sm8550_dpu_cfg = {
> + .caps = &sm8550_dpu_caps,
> + .mdp_count = ARRAY_SIZE(sm8550_mdp),
> + .mdp = sm8550_mdp,
> + .ctl_count = ARRAY_SIZE(sm8550_ctl),
> + .ctl = sm8550_ctl,
> + .sspp_count = ARRAY_SIZE(sm8550_sspp),
> + .sspp = sm8550_sspp,
> + .mixer_count = ARRAY_SIZE(sm8150_lm),
> + .mixer = sm8150_lm,
> + .dspp_count = ARRAY_SIZE(sm8150_dspp),
> + .dspp = sm8150_dspp,
> + .pingpong_count = ARRAY_SIZE(sm8550_pp),
> + .pingpong = sm8550_pp,
> + .merge_3d_count = ARRAY_SIZE(sm8550_merge_3d),
> + .merge_3d = sm8550_merge_3d,
> + .intf_count = ARRAY_SIZE(sm8550_intf),
> + .intf = sm8550_intf,
> + .vbif_count = ARRAY_SIZE(sdm845_vbif),
> + .vbif = sdm845_vbif,
> + .reg_dma_count = 1,
> + .dma_cfg = &sm8450_regdma,
> + .perf = &sm8450_perf_data,
> + .mdss_irqs = IRQ_SM8450_MASK,
> +};
> +
> static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
> .caps = &sc7280_dpu_caps,
> .mdp_count = ARRAY_SIZE(sc7280_mdp),
> @@ -2248,6 +2444,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
> { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
> { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
> { .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg},
> + { .hw_rev = DPU_HW_VER_900, .dpu_cfg = &sm8550_dpu_cfg},
> };
>
> const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 29e7ea5840a2..7a8380f5c643 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -48,6 +48,7 @@
> #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
> #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
> #define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */
> +#define DPU_HW_VER_900 DPU_HW_VER(9, 0, 0) /* sm8550 */
>
> #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170)
> #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> index 6d8e1bb3b3cc..dccad33532a9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> @@ -120,6 +120,8 @@ enum dpu_sspp {
> SSPP_DMA1,
> SSPP_DMA2,
> SSPP_DMA3,
> + SSPP_DMA4,
> + SSPP_DMA5,
> SSPP_CURSOR0,
> SSPP_CURSOR1,
> SSPP_MAX
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 0434cad511a4..18fefa116a56 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1303,6 +1303,7 @@ static const struct of_device_id dpu_dt_match[] = {
> { .compatible = "qcom,sm8150-dpu", },
> { .compatible = "qcom,sm8250-dpu", },
> { .compatible = "qcom,sm8450-dpu", },
> + { .compatible = "qcom,sm8550-dpu", },
> {}
> };
> MODULE_DEVICE_TABLE(of, dpu_dt_match);
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 4/6] drm/msm: mdss: add support for SM8550
2023-01-04 9:08 ` [PATCH 4/6] drm/msm: mdss: " Neil Armstrong
@ 2023-01-04 9:46 ` Dmitry Baryshkov
0 siblings, 0 replies; 23+ messages in thread
From: Dmitry Baryshkov @ 2023-01-04 9:46 UTC (permalink / raw)
To: Neil Armstrong, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 04/01/2023 11:08, Neil Armstrong wrote:
> Add support for the MDSS block on SM8550 platform.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index 144c8dd82be1..54483fe30ffd 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -288,6 +288,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
> msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
> break;
> case DPU_HW_VER_810:
> + case DPU_HW_VER_900:
> /* TODO: highest_bank_bit = 2 for LP_DDR4 */
> msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1);
> break;
> @@ -521,6 +522,7 @@ static const struct of_device_id mdss_dt_match[] = {
> { .compatible = "qcom,sm8150-mdss" },
> { .compatible = "qcom,sm8250-mdss" },
> { .compatible = "qcom,sm8450-mdss" },
> + { .compatible = "qcom,sm8550-mdss" },
> {}
> };
> MODULE_DEVICE_TABLE(of, mdss_dt_match);
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 5/6] drm/msm/dsi: add support for DSI-PHY on SM8550
2023-01-04 9:08 ` [PATCH 5/6] drm/msm/dsi: add support for DSI-PHY on SM8550 Neil Armstrong
@ 2023-01-04 9:53 ` Dmitry Baryshkov
2023-01-04 10:11 ` Neil Armstrong
0 siblings, 1 reply; 23+ messages in thread
From: Dmitry Baryshkov @ 2023-01-04 9:53 UTC (permalink / raw)
To: Neil Armstrong, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 04/01/2023 11:08, Neil Armstrong wrote:
> SM8550 use a 4nm DSI PHYs, which share register definitions
> with 7nm DSI PHYs. Rather than duplicating the driver, handle
> 4nm variant inside the common 5+7nm driver.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> drivers/gpu/drm/msm/Kconfig | 4 +-
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 102 ++++++++++++++++++++++++------
> 4 files changed, 89 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
> index e7b100d97f88..949b18a29a55 100644
> --- a/drivers/gpu/drm/msm/Kconfig
> +++ b/drivers/gpu/drm/msm/Kconfig
> @@ -140,11 +140,11 @@ config DRM_MSM_DSI_10NM_PHY
> Choose this option if DSI PHY on SDM845 is used on the platform.
>
> config DRM_MSM_DSI_7NM_PHY
> - bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
> + bool "Enable DSI 7nm/5nm/4nm PHY driver in MSM DRM"
> depends on DRM_MSM_DSI
> default y
> help
> - Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280
> + Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SM8550/SC7280
> is used on the platform.
>
> config DRM_MSM_HDMI
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index 0c956fdab23e..54e03cc9fbe7 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -573,6 +573,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
> .data = &dsi_phy_5nm_8350_cfgs },
> { .compatible = "qcom,dsi-phy-5nm-8450",
> .data = &dsi_phy_5nm_8450_cfgs },
> + { .compatible = "qcom,dsi-phy-4nm-8550",
> + .data = &dsi_phy_4nm_8550_cfgs },
> #endif
> {}
> };
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index f7a907ed2b4b..58f9e09f5224 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -59,6 +59,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
> +extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
>
> struct msm_dsi_dphy_timing {
> u32 clk_zero;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index 7b2c16b3a36c..11629c431c30 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -47,6 +47,8 @@
> #define DSI_PHY_7NM_QUIRK_V4_2 BIT(2)
> /* Hardware is V4.3 */
> #define DSI_PHY_7NM_QUIRK_V4_3 BIT(3)
> +/* Hardware is V5.2 */
> +#define DSI_PHY_7NM_QUIRK_V5_2 BIT(4)
>
> struct dsi_pll_config {
> bool enable_ssc;
> @@ -124,14 +126,25 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config
>
> if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
> config->pll_clock_inverters = 0x28;
> - else if (pll_freq <= 1000000000ULL)
> - config->pll_clock_inverters = 0xa0;
> - else if (pll_freq <= 2500000000ULL)
> - config->pll_clock_inverters = 0x20;
> - else if (pll_freq <= 3020000000ULL)
> - config->pll_clock_inverters = 0x00;
> - else
> - config->pll_clock_inverters = 0x40;
> + else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> + if (pll_freq <= 1300000000ULL)
> + config->pll_clock_inverters = 0xa0;
> + else if (pll_freq <= 2500000000ULL)
> + config->pll_clock_inverters = 0x20;
> + else if (pll_freq <= 4000000000ULL)
> + config->pll_clock_inverters = 0x00;
> + else
> + config->pll_clock_inverters = 0x40;
> + } else {
> + if (pll_freq <= 1000000000ULL)
> + config->pll_clock_inverters = 0xa0;
> + else if (pll_freq <= 2500000000ULL)
> + config->pll_clock_inverters = 0x20;
> + else if (pll_freq <= 3020000000ULL)
> + config->pll_clock_inverters = 0x00;
> + else
> + config->pll_clock_inverters = 0x40;
> + }
>
> config->decimal_div_start = dec;
> config->frac_div_start = frac;
> @@ -222,6 +235,13 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
> vco_config_1 = 0x01;
> }
>
> + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> + if (pll->vco_current_rate < 1557000000ULL)
> + vco_config_1 = 0x08;
> + else
> + vco_config_1 = 0x01;
> + }
> +
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
> analog_controls_five_1);
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
> @@ -860,7 +880,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
> pr_warn("PLL turned on before configuring PHY\n");
>
> /* Request for REFGEN READY */
> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
> + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
> + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> dsi_phy_write(phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1);
> udelay(500);
> }
> @@ -881,20 +902,38 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
>
> glbl_str_swi_cal_sel_ctrl = 0x00;
> if (phy->cphy_mode) {
> - vreg_ctrl_0 = 0x51;
> - vreg_ctrl_1 = 0x55;
> + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> + vreg_ctrl_0 = 0x45;
> + vreg_ctrl_1 = 0x45;
> + } else {
> + vreg_ctrl_0 = 0x51;
> + vreg_ctrl_1 = 0x55;
> + }
Please move these quirk-specific values down, to the rest of if
(QUIRK_5_2) statement.
> glbl_hstx_str_ctrl_0 = 0x00;
> glbl_pemph_ctrl_0 = 0x11;
> lane_ctrl0 = 0x17;
> } else {
> - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
> - vreg_ctrl_1 = 0x5c;
> + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> + vreg_ctrl_0 = 0x44;
> + vreg_ctrl_1 = 0x19;
> + } else {
> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
> + vreg_ctrl_1 = 0x5c;
> + }
> glbl_hstx_str_ctrl_0 = 0x88;
> glbl_pemph_ctrl_0 = 0x00;
> lane_ctrl0 = 0x1f;
> }
>
> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
> + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> + if (phy->cphy_mode) {
> + glbl_rescode_top_ctrl = 0x00;
> + glbl_rescode_bot_ctrl = 0x00;
> + } else {
> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x03;
> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3c;
> + }
> + } else if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
> if (phy->cphy_mode) {
> glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
> glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b;
> @@ -943,9 +982,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
> dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0x00);
>
> /* program CMN_CTRL_4 for minor_ver 2 chipsets*/
> - data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0);
> - data = data & (0xf0);
> - if (data == 0x20)
> + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
> + (dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) == 0x20)
> dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_4, 0x04);
Ugh. I should change this statement to use quirks too.
>
> /* Configure PHY lane swap (TODO: we need to calculate this) */
> @@ -1058,7 +1096,8 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
> dsi_phy_hw_v4_0_config_lpcdrx(phy, false);
>
> /* Turn off REFGEN Vote */
> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
> + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
> + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0);
> wmb();
> /* Delay to ensure HW removes vote before PHY shut down */
> @@ -1092,6 +1131,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = {
> { .supply = "vdds", .init_load_uA = 97800 },
> };
>
> +static const struct regulator_bulk_data dsi_phy_7nm_98400uA_regulators[] = {
> + { .supply = "vdds", .init_load_uA = 98400 },
> +};
> +
> const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
> .has_phy_lane = true,
> .regulator_data = dsi_phy_7nm_36mA_regulators,
> @@ -1201,3 +1244,26 @@ const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = {
> .num_dsi_phy = 2,
> .quirks = DSI_PHY_7NM_QUIRK_V4_3,
> };
> +
> +const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = {
> + .has_phy_lane = true,
> + .regulator_data = dsi_phy_7nm_98400uA_regulators,
> + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98400uA_regulators),
> + .ops = {
> + .enable = dsi_7nm_phy_enable,
> + .disable = dsi_7nm_phy_disable,
> + .pll_init = dsi_pll_7nm_init,
> + .save_pll_state = dsi_7nm_pll_save_state,
> + .restore_pll_state = dsi_7nm_pll_restore_state,
> + .set_continuous_clock = dsi_7nm_set_continuous_clock,
> + },
> + .min_pll_rate = 600000000UL,
> +#ifdef CONFIG_64BIT
> + .max_pll_rate = 5000000000UL,
> +#else
> + .max_pll_rate = ULONG_MAX,
> +#endif
> + .io_start = { 0xae95000, 0xae97000 },
> + .num_dsi_phy = 2,
> + .quirks = DSI_PHY_7NM_QUIRK_V5_2,
> +};
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 6/6] drm/msm/dsi: add support for DSI 2.7.0
2023-01-04 9:08 ` [PATCH 6/6] drm/msm/dsi: add support for DSI 2.7.0 Neil Armstrong
@ 2023-01-04 9:54 ` Dmitry Baryshkov
0 siblings, 0 replies; 23+ messages in thread
From: Dmitry Baryshkov @ 2023-01-04 9:54 UTC (permalink / raw)
To: Neil Armstrong, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 04/01/2023 11:08, Neil Armstrong wrote:
> Add support for DSI 2.7.0 (block used on sm8550).
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 16 ++++++++++++++++
> drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
> 2 files changed, 17 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/6] drm/msm/dpu: add support for SM8550
2023-01-04 9:45 ` Dmitry Baryshkov
@ 2023-01-04 10:08 ` Neil Armstrong
2023-01-04 17:48 ` Dmitry Baryshkov
0 siblings, 1 reply; 23+ messages in thread
From: Neil Armstrong @ 2023-01-04 10:08 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 04/01/2023 10:45, Dmitry Baryshkov wrote:
> On 04/01/2023 11:08, Neil Armstrong wrote:
>> Add definitions for the display hardware used on Qualcomm SM8550
>> platform.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197 +++++++++++++++++++++++++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +
>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
>> 4 files changed, 201 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index b4ca123d8e69..adf5e25269dc 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
<snip>
>> @@ -776,6 +821,45 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = {
>> },
>> };
>> +static const struct dpu_ctl_cfg sm8550_ctl[] = {
>> + {
>> + .name = "ctl_0", .id = CTL_0,
>> + .base = 0x15000, .len = 0x290,?
>> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE),
>
> CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY) ?
Indeed DPU_CTL_VM_CFG is missing, will switch to that.
>
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> + },
>> + {
>> + .name = "ctl_1", .id = CTL_1,
>> + .base = 0x16000, .len = 0x290,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>> + },
>> + {
>> + .name = "ctl_2", .id = CTL_2,
>> + .base = 0x17000, .len = 0x290,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
>
> CTL_SC7280_MASK?
Ack
>
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>> + },
>> + {
>> + .name = "ctl_3", .id = CTL_3,
>> + .base = 0x18000, .len = 0x290,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>> + },
>> + {
>> + .name = "ctl_4", .id = CTL_4,
>> + .base = 0x19000, .len = 0x290,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
>> + },
>> + {
>> + .name = "ctl_5", .id = CTL_5,
>> + .base = 0x1a000, .len = 0x290,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
>> + },
>> +};
>> +
>> static const struct dpu_ctl_cfg sc7280_ctl[] = {
>> {
>> .name = "ctl_0", .id = CTL_0,
<snip>
>> @@ -1268,6 +1386,16 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
>> .len = 0x20, .version = 0x20000},
>> };
>> +#define PP_BLK_DIPHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
>> + {\
>> + .name = _name, .id = _id, \
>> + .base = _base, .len = 0, \
>
> len = 0 looks incorrect. Any particular reason why can't we use plain PP_BLK here?
The TE block has been moved to the DSI INTF blocks since SM8350 I think, or earlier.
This removes the DPU_PINGPONG_DITHER feature used downstream to enable the PP TE callbacks.
Since there's only the DIPHER sub-block remaining, this is why I set len to 0.
>
>> + .features = BIT(DPU_PINGPONG_DITHER), \
>> + .merge_3d = _merge_3d, \
>> + .sblk = &_sblk, \
>> + .intr_done = _done, \
>> + .intr_rdptr = _rdptr, \
>> + }
>> #define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
>> {\
>> .name = _name, .id = _id, \
<snip>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 5/6] drm/msm/dsi: add support for DSI-PHY on SM8550
2023-01-04 9:53 ` Dmitry Baryshkov
@ 2023-01-04 10:11 ` Neil Armstrong
2023-01-04 17:20 ` Dmitry Baryshkov
0 siblings, 1 reply; 23+ messages in thread
From: Neil Armstrong @ 2023-01-04 10:11 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 04/01/2023 10:53, Dmitry Baryshkov wrote:
> On 04/01/2023 11:08, Neil Armstrong wrote:
>> SM8550 use a 4nm DSI PHYs, which share register definitions
>> with 7nm DSI PHYs. Rather than duplicating the driver, handle
>> 4nm variant inside the common 5+7nm driver.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>> drivers/gpu/drm/msm/Kconfig | 4 +-
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 +
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 102 ++++++++++++++++++++++++------
>> 4 files changed, 89 insertions(+), 20 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
>> index e7b100d97f88..949b18a29a55 100644
>> --- a/drivers/gpu/drm/msm/Kconfig
>> +++ b/drivers/gpu/drm/msm/Kconfig
>> @@ -140,11 +140,11 @@ config DRM_MSM_DSI_10NM_PHY
>> Choose this option if DSI PHY on SDM845 is used on the platform.
>> config DRM_MSM_DSI_7NM_PHY
>> - bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
>> + bool "Enable DSI 7nm/5nm/4nm PHY driver in MSM DRM"
>> depends on DRM_MSM_DSI
>> default y
>> help
>> - Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280
>> + Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SM8550/SC7280
>> is used on the platform.
>> config DRM_MSM_HDMI
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>> index 0c956fdab23e..54e03cc9fbe7 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>> @@ -573,6 +573,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
>> .data = &dsi_phy_5nm_8350_cfgs },
>> { .compatible = "qcom,dsi-phy-5nm-8450",
>> .data = &dsi_phy_5nm_8450_cfgs },
>> + { .compatible = "qcom,dsi-phy-4nm-8550",
>> + .data = &dsi_phy_4nm_8550_cfgs },
>> #endif
>> {}
>> };
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> index f7a907ed2b4b..58f9e09f5224 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> @@ -59,6 +59,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
>> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
>> extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
>> extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
>> +extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
>> struct msm_dsi_dphy_timing {
>> u32 clk_zero;
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> index 7b2c16b3a36c..11629c431c30 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> @@ -47,6 +47,8 @@
>> #define DSI_PHY_7NM_QUIRK_V4_2 BIT(2)
>> /* Hardware is V4.3 */
>> #define DSI_PHY_7NM_QUIRK_V4_3 BIT(3)
>> +/* Hardware is V5.2 */
>> +#define DSI_PHY_7NM_QUIRK_V5_2 BIT(4)
>> struct dsi_pll_config {
>> bool enable_ssc;
>> @@ -124,14 +126,25 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config
>> if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
>> config->pll_clock_inverters = 0x28;
>> - else if (pll_freq <= 1000000000ULL)
>> - config->pll_clock_inverters = 0xa0;
>> - else if (pll_freq <= 2500000000ULL)
>> - config->pll_clock_inverters = 0x20;
>> - else if (pll_freq <= 3020000000ULL)
>> - config->pll_clock_inverters = 0x00;
>> - else
>> - config->pll_clock_inverters = 0x40;
>> + else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
>> + if (pll_freq <= 1300000000ULL)
>> + config->pll_clock_inverters = 0xa0;
>> + else if (pll_freq <= 2500000000ULL)
>> + config->pll_clock_inverters = 0x20;
>> + else if (pll_freq <= 4000000000ULL)
>> + config->pll_clock_inverters = 0x00;
>> + else
>> + config->pll_clock_inverters = 0x40;
>> + } else {
>> + if (pll_freq <= 1000000000ULL)
>> + config->pll_clock_inverters = 0xa0;
>> + else if (pll_freq <= 2500000000ULL)
>> + config->pll_clock_inverters = 0x20;
>> + else if (pll_freq <= 3020000000ULL)
>> + config->pll_clock_inverters = 0x00;
>> + else
>> + config->pll_clock_inverters = 0x40;
>> + }
>> config->decimal_div_start = dec;
>> config->frac_div_start = frac;
>> @@ -222,6 +235,13 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
>> vco_config_1 = 0x01;
>> }
>> + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
>> + if (pll->vco_current_rate < 1557000000ULL)
>> + vco_config_1 = 0x08;
>> + else
>> + vco_config_1 = 0x01;
>> + }
>> +
>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
>> analog_controls_five_1);
>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
>> @@ -860,7 +880,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
>> pr_warn("PLL turned on before configuring PHY\n");
>> /* Request for REFGEN READY */
>> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
>> + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
>> + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
>> dsi_phy_write(phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1);
>> udelay(500);
>> }
>> @@ -881,20 +902,38 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
>> glbl_str_swi_cal_sel_ctrl = 0x00;
>> if (phy->cphy_mode) {
>> - vreg_ctrl_0 = 0x51;
>> - vreg_ctrl_1 = 0x55;
>> + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
>> + vreg_ctrl_0 = 0x45;
>> + vreg_ctrl_1 = 0x45;
>> + } else {
>> + vreg_ctrl_0 = 0x51;
>> + vreg_ctrl_1 = 0x55;
>> + }
>
> Please move these quirk-specific values down, to the rest of if (QUIRK_5_2) statement.
Ok
>
>> glbl_hstx_str_ctrl_0 = 0x00;
>> glbl_pemph_ctrl_0 = 0x11;
>> lane_ctrl0 = 0x17;
>> } else {
>> - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
>> - vreg_ctrl_1 = 0x5c;
>> + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
>> + vreg_ctrl_0 = 0x44;
>> + vreg_ctrl_1 = 0x19;
>> + } else {
>> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
>> + vreg_ctrl_1 = 0x5c;
>> + }
>> glbl_hstx_str_ctrl_0 = 0x88;
>> glbl_pemph_ctrl_0 = 0x00;
>> lane_ctrl0 = 0x1f;
>> }
>> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
>> + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
>> + if (phy->cphy_mode) {
>> + glbl_rescode_top_ctrl = 0x00;
>> + glbl_rescode_bot_ctrl = 0x00;
>> + } else {
>> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x03;
>> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3c;
>> + }
>> + } else if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
>> if (phy->cphy_mode) {
>> glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
>> glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b;
>> @@ -943,9 +982,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
>> dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0x00);
>> /* program CMN_CTRL_4 for minor_ver 2 chipsets*/
>> - data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0);
>> - data = data & (0xf0);
>> - if (data == 0x20)
>> + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
>> + (dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) == 0x20)
>> dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_4, 0x04);
>
> Ugh. I should change this statement to use quirks too.
Sorrt I don't see what you mean, should I change the original REVISION_ID0 to a proper quirk ?
>
>> /* Configure PHY lane swap (TODO: we need to calculate this) */
>> @@ -1058,7 +1096,8 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
>> dsi_phy_hw_v4_0_config_lpcdrx(phy, false);
>> /* Turn off REFGEN Vote */
>> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
>> + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
>> + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
>> dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0);
>> wmb();
>> /* Delay to ensure HW removes vote before PHY shut down */
>> @@ -1092,6 +1131,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = {
>> { .supply = "vdds", .init_load_uA = 97800 },
>> };
>> +static const struct regulator_bulk_data dsi_phy_7nm_98400uA_regulators[] = {
>> + { .supply = "vdds", .init_load_uA = 98400 },
>> +};
>> +
>> const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
>> .has_phy_lane = true,
>> .regulator_data = dsi_phy_7nm_36mA_regulators,
>> @@ -1201,3 +1244,26 @@ const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = {
>> .num_dsi_phy = 2,
>> .quirks = DSI_PHY_7NM_QUIRK_V4_3,
>> };
>> +
>> +const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = {
>> + .has_phy_lane = true,
>> + .regulator_data = dsi_phy_7nm_98400uA_regulators,
>> + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98400uA_regulators),
>> + .ops = {
>> + .enable = dsi_7nm_phy_enable,
>> + .disable = dsi_7nm_phy_disable,
>> + .pll_init = dsi_pll_7nm_init,
>> + .save_pll_state = dsi_7nm_pll_save_state,
>> + .restore_pll_state = dsi_7nm_pll_restore_state,
>> + .set_continuous_clock = dsi_7nm_set_continuous_clock,
>> + },
>> + .min_pll_rate = 600000000UL,
>> +#ifdef CONFIG_64BIT
>> + .max_pll_rate = 5000000000UL,
>> +#else
>> + .max_pll_rate = ULONG_MAX,
>> +#endif
>> + .io_start = { 0xae95000, 0xae97000 },
>> + .num_dsi_phy = 2,
>> + .quirks = DSI_PHY_7NM_QUIRK_V5_2,
>> +};
>>
>
Thanks,
Neil
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 5/6] drm/msm/dsi: add support for DSI-PHY on SM8550
2023-01-04 10:11 ` Neil Armstrong
@ 2023-01-04 17:20 ` Dmitry Baryshkov
0 siblings, 0 replies; 23+ messages in thread
From: Dmitry Baryshkov @ 2023-01-04 17:20 UTC (permalink / raw)
To: neil.armstrong
Cc: Rob Clark, Abhinav Kumar, Sean Paul, David Airlie, Daniel Vetter,
Rob Herring, Krzysztof Kozlowski, Jonathan Marek, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel
On Wed, 4 Jan 2023 at 12:11, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
> On 04/01/2023 10:53, Dmitry Baryshkov wrote:
> > On 04/01/2023 11:08, Neil Armstrong wrote:
> >> SM8550 use a 4nm DSI PHYs, which share register definitions
> >> with 7nm DSI PHYs. Rather than duplicating the driver, handle
> >> 4nm variant inside the common 5+7nm driver.
> >>
> >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> >> ---
> >> drivers/gpu/drm/msm/Kconfig | 4 +-
> >> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 +
> >> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
> >> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 102 ++++++++++++++++++++++++------
> >> 4 files changed, 89 insertions(+), 20 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
> >> index e7b100d97f88..949b18a29a55 100644
> >> --- a/drivers/gpu/drm/msm/Kconfig
> >> +++ b/drivers/gpu/drm/msm/Kconfig
> >> @@ -140,11 +140,11 @@ config DRM_MSM_DSI_10NM_PHY
> >> Choose this option if DSI PHY on SDM845 is used on the platform.
> >> config DRM_MSM_DSI_7NM_PHY
> >> - bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
> >> + bool "Enable DSI 7nm/5nm/4nm PHY driver in MSM DRM"
> >> depends on DRM_MSM_DSI
> >> default y
> >> help
> >> - Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280
> >> + Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SM8550/SC7280
> >> is used on the platform.
> >> config DRM_MSM_HDMI
> >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> >> index 0c956fdab23e..54e03cc9fbe7 100644
> >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> >> @@ -573,6 +573,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
> >> .data = &dsi_phy_5nm_8350_cfgs },
> >> { .compatible = "qcom,dsi-phy-5nm-8450",
> >> .data = &dsi_phy_5nm_8450_cfgs },
> >> + { .compatible = "qcom,dsi-phy-4nm-8550",
> >> + .data = &dsi_phy_4nm_8550_cfgs },
> >> #endif
> >> {}
> >> };
> >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> >> index f7a907ed2b4b..58f9e09f5224 100644
> >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> >> @@ -59,6 +59,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
> >> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
> >> extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
> >> extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
> >> +extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
> >> struct msm_dsi_dphy_timing {
> >> u32 clk_zero;
> >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> >> index 7b2c16b3a36c..11629c431c30 100644
> >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> >> @@ -47,6 +47,8 @@
> >> #define DSI_PHY_7NM_QUIRK_V4_2 BIT(2)
> >> /* Hardware is V4.3 */
> >> #define DSI_PHY_7NM_QUIRK_V4_3 BIT(3)
> >> +/* Hardware is V5.2 */
> >> +#define DSI_PHY_7NM_QUIRK_V5_2 BIT(4)
> >> struct dsi_pll_config {
> >> bool enable_ssc;
> >> @@ -124,14 +126,25 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config
> >> if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
> >> config->pll_clock_inverters = 0x28;
> >> - else if (pll_freq <= 1000000000ULL)
> >> - config->pll_clock_inverters = 0xa0;
> >> - else if (pll_freq <= 2500000000ULL)
> >> - config->pll_clock_inverters = 0x20;
> >> - else if (pll_freq <= 3020000000ULL)
> >> - config->pll_clock_inverters = 0x00;
> >> - else
> >> - config->pll_clock_inverters = 0x40;
> >> + else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> >> + if (pll_freq <= 1300000000ULL)
> >> + config->pll_clock_inverters = 0xa0;
> >> + else if (pll_freq <= 2500000000ULL)
> >> + config->pll_clock_inverters = 0x20;
> >> + else if (pll_freq <= 4000000000ULL)
> >> + config->pll_clock_inverters = 0x00;
> >> + else
> >> + config->pll_clock_inverters = 0x40;
> >> + } else {
> >> + if (pll_freq <= 1000000000ULL)
> >> + config->pll_clock_inverters = 0xa0;
> >> + else if (pll_freq <= 2500000000ULL)
> >> + config->pll_clock_inverters = 0x20;
> >> + else if (pll_freq <= 3020000000ULL)
> >> + config->pll_clock_inverters = 0x00;
> >> + else
> >> + config->pll_clock_inverters = 0x40;
> >> + }
> >> config->decimal_div_start = dec;
> >> config->frac_div_start = frac;
> >> @@ -222,6 +235,13 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
> >> vco_config_1 = 0x01;
> >> }
> >> + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> >> + if (pll->vco_current_rate < 1557000000ULL)
> >> + vco_config_1 = 0x08;
> >> + else
> >> + vco_config_1 = 0x01;
> >> + }
> >> +
> >> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
> >> analog_controls_five_1);
> >> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
> >> @@ -860,7 +880,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
> >> pr_warn("PLL turned on before configuring PHY\n");
> >> /* Request for REFGEN READY */
> >> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
> >> + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
> >> + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> >> dsi_phy_write(phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1);
> >> udelay(500);
> >> }
> >> @@ -881,20 +902,38 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
> >> glbl_str_swi_cal_sel_ctrl = 0x00;
> >> if (phy->cphy_mode) {
> >> - vreg_ctrl_0 = 0x51;
> >> - vreg_ctrl_1 = 0x55;
> >> + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> >> + vreg_ctrl_0 = 0x45;
> >> + vreg_ctrl_1 = 0x45;
> >> + } else {
> >> + vreg_ctrl_0 = 0x51;
> >> + vreg_ctrl_1 = 0x55;
> >> + }
> >
> > Please move these quirk-specific values down, to the rest of if (QUIRK_5_2) statement.
>
> Ok
>
> >
> >> glbl_hstx_str_ctrl_0 = 0x00;
> >> glbl_pemph_ctrl_0 = 0x11;
> >> lane_ctrl0 = 0x17;
> >> } else {
> >> - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
> >> - vreg_ctrl_1 = 0x5c;
> >> + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> >> + vreg_ctrl_0 = 0x44;
> >> + vreg_ctrl_1 = 0x19;
> >> + } else {
> >> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
> >> + vreg_ctrl_1 = 0x5c;
> >> + }
> >> glbl_hstx_str_ctrl_0 = 0x88;
> >> glbl_pemph_ctrl_0 = 0x00;
> >> lane_ctrl0 = 0x1f;
> >> }
> >> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
> >> + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> >> + if (phy->cphy_mode) {
> >> + glbl_rescode_top_ctrl = 0x00;
> >> + glbl_rescode_bot_ctrl = 0x00;
> >> + } else {
> >> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x03;
> >> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3c;
> >> + }
> >> + } else if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
> >> if (phy->cphy_mode) {
> >> glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
> >> glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b;
> >> @@ -943,9 +982,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
> >> dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0x00);
> >> /* program CMN_CTRL_4 for minor_ver 2 chipsets*/
> >> - data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0);
> >> - data = data & (0xf0);
> >> - if (data == 0x20)
> >> + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
> >> + (dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) == 0x20)
> >> dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_4, 0x04);
> >
> > Ugh. I should change this statement to use quirks too.
>
> Sorrt I don't see what you mean, should I change the original REVISION_ID0 to a proper quirk ?
>
No, I'll do this. For now you can leave this piece code as is (reading
rev + your quirk).
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/6] drm/msm/dpu: add support for SM8550
2023-01-04 10:08 ` Neil Armstrong
@ 2023-01-04 17:48 ` Dmitry Baryshkov
2023-01-05 9:59 ` neil.armstrong
0 siblings, 1 reply; 23+ messages in thread
From: Dmitry Baryshkov @ 2023-01-04 17:48 UTC (permalink / raw)
To: neil.armstrong
Cc: Rob Clark, Abhinav Kumar, Sean Paul, David Airlie, Daniel Vetter,
Rob Herring, Krzysztof Kozlowski, Jonathan Marek, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel
On Wed, 4 Jan 2023 at 12:08, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
> On 04/01/2023 10:45, Dmitry Baryshkov wrote:
> > On 04/01/2023 11:08, Neil Armstrong wrote:
> >> Add definitions for the display hardware used on Qualcomm SM8550
> >> platform.
> >>
> >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> >> ---
> >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197 +++++++++++++++++++++++++
> >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +
> >> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> >> 4 files changed, 201 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >> index b4ca123d8e69..adf5e25269dc 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>
> <snip>
>
> >> @@ -776,6 +821,45 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = {
> >> },
> >> };
> >> +static const struct dpu_ctl_cfg sm8550_ctl[] = {
> >> + {
> >> + .name = "ctl_0", .id = CTL_0,
> >> + .base = 0x15000, .len = 0x290,?
> >> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE),
> >
> > CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY) ?
>
> Indeed DPU_CTL_VM_CFG is missing, will switch to that.
>
> >
> >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> >> + },
> >> + {
> >> + .name = "ctl_1", .id = CTL_1,
> >> + .base = 0x16000, .len = 0x290,
> >> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE),
> >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> >> + },
> >> + {
> >> + .name = "ctl_2", .id = CTL_2,
> >> + .base = 0x17000, .len = 0x290,
> >> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
> >
> > CTL_SC7280_MASK?
>
> Ack
>
> >
> >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> >> + },
> >> + {
> >> + .name = "ctl_3", .id = CTL_3,
> >> + .base = 0x18000, .len = 0x290,
> >> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
> >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> >> + },
> >> + {
> >> + .name = "ctl_4", .id = CTL_4,
> >> + .base = 0x19000, .len = 0x290,
> >> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
> >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> >> + },
> >> + {
> >> + .name = "ctl_5", .id = CTL_5,
> >> + .base = 0x1a000, .len = 0x290,
> >> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
> >> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> >> + },
> >> +};
> >> +
> >> static const struct dpu_ctl_cfg sc7280_ctl[] = {
> >> {
> >> .name = "ctl_0", .id = CTL_0,
>
> <snip>
>
> >> @@ -1268,6 +1386,16 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
> >> .len = 0x20, .version = 0x20000},
> >> };
> >> +#define PP_BLK_DIPHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
> >> + {\
> >> + .name = _name, .id = _id, \
> >> + .base = _base, .len = 0, \
> >
> > len = 0 looks incorrect. Any particular reason why can't we use plain PP_BLK here?
>
> The TE block has been moved to the DSI INTF blocks since SM8350 I think, or earlier.
I think, 8150. Marijn has been working on adding support for INTF-based TE.
> This removes the DPU_PINGPONG_DITHER feature used downstream to enable the PP TE callbacks.
> Since there's only the DIPHER sub-block remaining, this is why I set len to 0.
I went on with some research. Usually PP len is 0xd4. However it seems
since 8350 (since the change of DSC block) the PP size should be 0x0),
despite dowsnstream DTs having sde-pp-size=0xd4 for sm8350 and sm8450
(or 0x4 for neo, DPU 9.1.0).
So, it looks like you are correct here (and we should fix 8350/8450
patches instead).
>
> >
> >> + .features = BIT(DPU_PINGPONG_DITHER), \
> >> + .merge_3d = _merge_3d, \
> >> + .sblk = &_sblk, \
> >> + .intr_done = _done, \
> >> + .intr_rdptr = _rdptr, \
> >> + }
> >> #define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
> >> {\
> >> .name = _name, .id = _id, \
>
> <snip>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/6] dt-bindings: display/msm: document the display hardware for SM8550
2023-01-04 9:08 ` [PATCH 2/6] dt-bindings: display/msm: document the display hardware for SM8550 Neil Armstrong
@ 2023-01-05 2:53 ` Rob Herring
2023-01-08 23:11 ` Dmitry Baryshkov
1 sibling, 0 replies; 23+ messages in thread
From: Rob Herring @ 2023-01-05 2:53 UTC (permalink / raw)
To: Neil Armstrong
Cc: Abhinav Kumar, freedreno, Krzysztof Kozlowski, David Airlie,
devicetree, linux-arm-msm, Sean Paul, dri-devel, Rob Clark,
Daniel Vetter, Dmitry Baryshkov, linux-kernel, Rob Herring,
Jonathan Marek
On Wed, 04 Jan 2023 10:08:44 +0100, Neil Armstrong wrote:
> Document the MDSS and DPU blocks found on the Qualcomm SM8550
> platform.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> .../bindings/display/msm/qcom,sm8550-dpu.yaml | 134 +++++++++
> .../bindings/display/msm/qcom,sm8550-mdss.yaml | 331 +++++++++++++++++++++
> 2 files changed, 465 insertions(+)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.example.dts:21:18: fatal error: dt-bindings/clock/qcom,sm8550-dispcc.h: No such file or directory
21 | #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:434: Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1508: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230103-topic-sm8550-upstream-mdss-dsi-v1-2-9ccd7e652fcd@linaro.org
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/6] drm/msm/dpu: add support for SM8550
2023-01-04 17:48 ` Dmitry Baryshkov
@ 2023-01-05 9:59 ` neil.armstrong
0 siblings, 0 replies; 23+ messages in thread
From: neil.armstrong @ 2023-01-05 9:59 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Abhinav Kumar, Sean Paul, David Airlie, Daniel Vetter,
Rob Herring, Krzysztof Kozlowski, Jonathan Marek, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel
On 04/01/2023 18:48, Dmitry Baryshkov wrote:
> On Wed, 4 Jan 2023 at 12:08, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>>
>> On 04/01/2023 10:45, Dmitry Baryshkov wrote:
>>> On 04/01/2023 11:08, Neil Armstrong wrote:
>>>> Add definitions for the display hardware used on Qualcomm SM8550
>>>> platform.
>>>>
>>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>>>> ---
>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197 +++++++++++++++++++++++++
>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +
>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
>>>> 4 files changed, 201 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>> index b4ca123d8e69..adf5e25269dc 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>
>> <snip>
>>
>>>> @@ -776,6 +821,45 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = {
>>>> },
>>>> };
>>>> +static const struct dpu_ctl_cfg sm8550_ctl[] = {
>>>> + {
>>>> + .name = "ctl_0", .id = CTL_0,
>>>> + .base = 0x15000, .len = 0x290,?
>>>> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE),
>>>
>>> CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY) ?
>>
>> Indeed DPU_CTL_VM_CFG is missing, will switch to that.
>>
>>>
>>>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>>>> + },
>>>> + {
>>>> + .name = "ctl_1", .id = CTL_1,
>>>> + .base = 0x16000, .len = 0x290,
>>>> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE),
>>>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>>>> + },
>>>> + {
>>>> + .name = "ctl_2", .id = CTL_2,
>>>> + .base = 0x17000, .len = 0x290,
>>>> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
>>>
>>> CTL_SC7280_MASK?
>>
>> Ack
>>
>>>
>>>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>>>> + },
>>>> + {
>>>> + .name = "ctl_3", .id = CTL_3,
>>>> + .base = 0x18000, .len = 0x290,
>>>> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
>>>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>>>> + },
>>>> + {
>>>> + .name = "ctl_4", .id = CTL_4,
>>>> + .base = 0x19000, .len = 0x290,
>>>> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
>>>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
>>>> + },
>>>> + {
>>>> + .name = "ctl_5", .id = CTL_5,
>>>> + .base = 0x1a000, .len = 0x290,
>>>> + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
>>>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
>>>> + },
>>>> +};
>>>> +
>>>> static const struct dpu_ctl_cfg sc7280_ctl[] = {
>>>> {
>>>> .name = "ctl_0", .id = CTL_0,
>>
>> <snip>
>>
>>>> @@ -1268,6 +1386,16 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
>>>> .len = 0x20, .version = 0x20000},
>>>> };
>>>> +#define PP_BLK_DIPHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
>>>> + {\
>>>> + .name = _name, .id = _id, \
>>>> + .base = _base, .len = 0, \
>>>
>>> len = 0 looks incorrect. Any particular reason why can't we use plain PP_BLK here?
>>
>> The TE block has been moved to the DSI INTF blocks since SM8350 I think, or earlier.
>
> I think, 8150. Marijn has been working on adding support for INTF-based TE.
>
>> This removes the DPU_PINGPONG_DITHER feature used downstream to enable the PP TE callbacks.
>> Since there's only the DIPHER sub-block remaining, this is why I set len to 0.
>
> I went on with some research. Usually PP len is 0xd4. However it seems
> since 8350 (since the change of DSC block) the PP size should be 0x0),
> despite dowsnstream DTs having sde-pp-size=0xd4 for sm8350 and sm8450
> (or 0x4 for neo, DPU 9.1.0).
Perhaps neo has a single register at PP base address, on 8550 there's none.
> So, it looks like you are correct here (and we should fix 8350/8450
> patches instead).
Yes it must be because with the new DSC block, the PP DCE_DATA_XX_SWAP/DSC_MODE registers were removed,
so I expect they are still present in 8150 & 8250.
Neil
>
>>
>>>
>>>> + .features = BIT(DPU_PINGPONG_DITHER), \
>>>> + .merge_3d = _merge_3d, \
>>>> + .sblk = &_sblk, \
>>>> + .intr_done = _done, \
>>>> + .intr_rdptr = _rdptr, \
>>>> + }
>>>> #define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
>>>> {\
>>>> .name = _name, .id = _id, \
>>
>> <snip>
>>
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/6] dt-bindings: display/msm: document the SM8550 DSI PHY
2023-01-04 9:08 ` [PATCH 1/6] dt-bindings: display/msm: document the SM8550 DSI PHY Neil Armstrong
@ 2023-01-06 15:41 ` Krzysztof Kozlowski
2023-01-08 23:09 ` Dmitry Baryshkov
0 siblings, 1 reply; 23+ messages in thread
From: Krzysztof Kozlowski @ 2023-01-06 15:41 UTC (permalink / raw)
To: Neil Armstrong, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Sean Paul, David Airlie, Daniel Vetter, Rob Herring,
Krzysztof Kozlowski, Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 04/01/2023 10:08, Neil Armstrong wrote:
> Document the SM8550 DSI PHY which is very close from the 7nm
> and 5nm DSI PHYs found in earlier platforms.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
> index bffd161fedfd..f72727f81076 100644
> --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
> @@ -15,6 +15,7 @@ allOf:
> properties:
> compatible:
> enum:
> + - qcom,dsi-phy-4nm-8550
> - qcom,dsi-phy-5nm-8350
> - qcom,dsi-phy-5nm-8450
Poor patterns once allowed like to keep growing... I commented here:
https://lore.kernel.org/all/ccbb47e4-d780-0b1d-814e-27e86b6c369c@linaro.org/
so let's wait for response about other compatibles.
> - qcom,dsi-phy-7nm
>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/6] dt-bindings: display/msm: document the SM8550 DSI PHY
2023-01-06 15:41 ` Krzysztof Kozlowski
@ 2023-01-08 23:09 ` Dmitry Baryshkov
2023-01-09 8:20 ` Neil Armstrong
0 siblings, 1 reply; 23+ messages in thread
From: Dmitry Baryshkov @ 2023-01-08 23:09 UTC (permalink / raw)
To: Krzysztof Kozlowski, Neil Armstrong, Rob Clark, Abhinav Kumar,
Sean Paul, David Airlie, Daniel Vetter, Rob Herring,
Krzysztof Kozlowski, Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 06/01/2023 17:41, Krzysztof Kozlowski wrote:
> On 04/01/2023 10:08, Neil Armstrong wrote:
>> Document the SM8550 DSI PHY which is very close from the 7nm
>> and 5nm DSI PHYs found in earlier platforms.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>> Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
>> index bffd161fedfd..f72727f81076 100644
>> --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
>> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
>> @@ -15,6 +15,7 @@ allOf:
>> properties:
>> compatible:
>> enum:
>> + - qcom,dsi-phy-4nm-8550
>> - qcom,dsi-phy-5nm-8350
>> - qcom,dsi-phy-5nm-8450
>
> Poor patterns once allowed like to keep growing... I commented here:
> https://lore.kernel.org/all/ccbb47e4-d780-0b1d-814e-27e86b6c369c@linaro.org/
>
> so let's wait for response about other compatibles.
I have fixed 8350 & 8450 while applying. Please rebase on top of
msm-next-lumag-next with fixed compatibles.
Note: the DPU changes are not yet part of the msm-lumag-next.
>
>> - qcom,dsi-phy-7nm
>>
>
> Best regards,
> Krzysztof
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 0/6] drm/msm: add support for SM8450
2023-01-04 9:08 [PATCH 0/6] drm/msm: add support for SM8450 Neil Armstrong
` (5 preceding siblings ...)
2023-01-04 9:08 ` [PATCH 6/6] drm/msm/dsi: add support for DSI 2.7.0 Neil Armstrong
@ 2023-01-08 23:09 ` Dmitry Baryshkov
6 siblings, 0 replies; 23+ messages in thread
From: Dmitry Baryshkov @ 2023-01-08 23:09 UTC (permalink / raw)
To: Neil Armstrong, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 04/01/2023 11:08, Neil Armstrong wrote:
> This adds support for the MDSS/DPU/DSI on the Qualcomm SM8550 platform.
Nit: please change the subject for v2. It's 8550, not 8450.
>
> This patchset is based on the SM8450 display support serie at [1].
>
> In order to work, the following patchsets are required:
> - PM8550 LDO fix at [2]
> - DISPCC driver at [3]
>
> + the DT changes.
>
> [1] https://lore.kernel.org/all/20221207012231.112059-1-dmitry.baryshkov@linaro.org/
> [2] https://lore.kernel.org/all/20230102-topic-sm8550-upstream-fixes-reg-l11b-nldo-v1-1-d97def246338@linaro.org/
> [3] https://lore.kernel.org/all/20230103-topic-sm8550-upstream-dispcc-v1-0-81bfcc26b2dc@linaro.org/
>
> To: Rob Clark <robdclark@gmail.com>
> To: Abhinav Kumar <quic_abhinavk@quicinc.com>
> To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> To: Sean Paul <sean@poorly.run>
> To: David Airlie <airlied@gmail.com>
> To: Daniel Vetter <daniel@ffwll.ch>
> To: Rob Herring <robh+dt@kernel.org>
> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> To: Jonathan Marek <jonathan@marek.ca>
> Cc: linux-arm-msm@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org
> Cc: freedreno@lists.freedesktop.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>
> ---
> Neil Armstrong (6):
> dt-bindings: display/msm: document the SM8550 DSI PHY
> dt-bindings: display/msm: document the display hardware for SM8550
> drm/msm/dpu: add support for SM8550
> drm/msm: mdss: add support for SM8550
> drm/msm/dsi: add support for DSI-PHY on SM8550
> drm/msm/dsi: add support for DSI 2.7.0
>
> .../bindings/display/msm/dsi-phy-7nm.yaml | 1 +
> .../bindings/display/msm/qcom,sm8550-dpu.yaml | 134 +++++++++
> .../bindings/display/msm/qcom,sm8550-mdss.yaml | 331 +++++++++++++++++++++
> drivers/gpu/drm/msm/Kconfig | 4 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197 ++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 16 +
> drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 102 +++++--
> drivers/gpu/drm/msm/msm_mdss.c | 2 +
> 14 files changed, 775 insertions(+), 20 deletions(-)
> ---
> base-commit: d862fd95b9c924bd0a257f7708a6e3868d39ff43
> change-id: 20230103-topic-sm8550-upstream-mdss-dsi-35ca8acea529
>
> Best regards,
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/6] dt-bindings: display/msm: document the display hardware for SM8550
2023-01-04 9:08 ` [PATCH 2/6] dt-bindings: display/msm: document the display hardware for SM8550 Neil Armstrong
2023-01-05 2:53 ` Rob Herring
@ 2023-01-08 23:11 ` Dmitry Baryshkov
1 sibling, 0 replies; 23+ messages in thread
From: Dmitry Baryshkov @ 2023-01-08 23:11 UTC (permalink / raw)
To: Neil Armstrong, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 04/01/2023 11:08, Neil Armstrong wrote:
> Document the MDSS and DPU blocks found on the Qualcomm SM8550
> platform.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Please split this into two patches: one for mdss, one for dpu.
> ---
> .../bindings/display/msm/qcom,sm8550-dpu.yaml | 134 +++++++++
> .../bindings/display/msm/qcom,sm8550-mdss.yaml | 331 +++++++++++++++++++++
> 2 files changed, 465 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml
> new file mode 100644
> index 000000000000..c3d5a98fe3c0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml
> @@ -0,0 +1,134 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM8550 Display DPU
> +
> +maintainers:
> + - Neil Armstrong <neil.armstrong@linaro.org>
> +
> +$ref: /schemas/display/msm/dpu-common.yaml#
> +
> +properties:
> + compatible:
> + const: qcom,sm8550-dpu
> +
> + reg:
> + items:
> + - description: Address offset and size for mdp register set
> + - description: Address offset and size for vbif register set
> +
> + reg-names:
> + items:
> + - const: mdp
> + - const: vbif
> +
> + clocks:
> + items:
> + - description: Display AHB
> + - description: Display hf axi
> + - description: Display MDSS ahb
> + - description: Display lut
> + - description: Display core
> + - description: Display vsync
> +
> + clock-names:
> + items:
> + - const: bus
> + - const: nrt_bus
> + - const: iface
> + - const: lut
> + - const: core
> + - const: vsync
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
> + #include <dt-bindings/clock/qcom,sm8550-gcc.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interconnect/qcom,sm8550.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + display-controller@ae01000 {
> + compatible = "qcom,sm8550-dpu";
> + reg = <0x0ae01000 0x8f000>,
> + <0x0aeb0000 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&gcc GCC_DISP_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus",
> + "nrt_bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + operating-points-v2 = <&mdp_opp_table>;
> + power-domains = <&rpmhpd SM8550_MMCX>;
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dpu_intf2_out: endpoint {
> + remote-endpoint = <&dsi1_in>;
> + };
> + };
> + };
> +
> + mdp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-325000000 {
> + opp-hz = /bits/ 64 <325000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-375000000 {
> + opp-hz = /bits/ 64 <375000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-514000000 {
> + opp-hz = /bits/ 64 <514000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +...
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml
> new file mode 100644
> index 000000000000..71b5b5f75969
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml
> @@ -0,0 +1,331 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mdss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM8550 Display MDSS
> +
> +maintainers:
> + - Neil Armstrong <neil.armstrong@linaro.org>
> +
> +description:
> + SM8550 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
> + DPU display controller, DSI and DP interfaces etc.
> +
> +$ref: /schemas/display/msm/mdss-common.yaml#
> +
> +properties:
> + compatible:
> + const: qcom,sm8550-mdss
> +
> + clocks:
> + items:
> + - description: Display MDSS AHB
> + - description: Display AHB
> + - description: Display hf AXI
> + - description: Display core
> +
> + iommus:
> + maxItems: 1
> +
> + interconnects:
> + maxItems: 2
> +
> + interconnect-names:
> + maxItems: 2
> +
> +patternProperties:
> + "^display-controller@[0-9a-f]+$":
> + type: object
> + properties:
> + compatible:
> + const: qcom,sm8550-dpu
> +
> + "^dsi@[0-9a-f]+$":
> + type: object
> + properties:
> + compatible:
> + const: qcom,mdss-dsi-ctrl
> +
> + "^phy@[0-9a-f]+$":
> + type: object
> + properties:
> + compatible:
> + const: qcom,dsi-phy-4nm-8550
qcom,sm8550-dsi-phy-4nm
> +
> +required:
> + - compatible
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
> + #include <dt-bindings/clock/qcom,sm8550-gcc.h>
> + #include <dt-bindings/clock/qcom,rpmh.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interconnect/qcom,sm8550.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + display-subsystem@ae00000 {
> + compatible = "qcom,sm8550-mdss";
> + reg = <0x0ae00000 0x1000>;
> + reg-names = "mdss";
> +
> + interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
> + <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>
> + interconnect-names = "mdp0-mem", "mdp1-mem";
> +
> + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> +
> + power-domains = <&dispcc MDSS_GDSC>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface", "bus", "nrt_bus", "core";
> +
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + iommus = <&apps_smmu 0x1c00 0x2>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + display-controller@ae01000 {
> + compatible = "qcom,sm8550-dpu";
> + reg = <0x0ae01000 0x8f000>,
> + <0x0aeb0000 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&gcc GCC_DISP_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus",
> + "nrt_bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + operating-points-v2 = <&mdp_opp_table>;
> + power-domains = <&rpmhpd SM8550_MMCX>;
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dpu_intf2_out: endpoint {
> + remote-endpoint = <&dsi1_in>;
> + };
> + };
> + };
> +
> + mdp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-325000000 {
> + opp-hz = /bits/ 64 <325000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-375000000 {
> + opp-hz = /bits/ 64 <375000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-514000000 {
> + opp-hz = /bits/ 64 <514000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +
> + dsi@ae94000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0x0ae94000 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <4>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
> +
> + operating-points-v2 = <&dsi_opp_table>;
> + power-domains = <&rpmhpd SM8550_MMCX>;
> +
> + phys = <&dsi0_phy>;
> + phy-names = "dsi";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&dpu_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> +
> + dsi_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-187500000 {
> + opp-hz = /bits/ 64 <187500000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-358000000 {
> + opp-hz = /bits/ 64 <358000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> + };
> + };
> +
> + dsi0_phy: phy@ae94400 {
> + compatible = "qcom,dsi-phy-4nm-8550";
> + reg = <0x0ae95000 0x200>,
> + <0x0ae95200 0x280>,
> + <0x0ae95500 0x400>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
> + };
> +
> + dsi@ae96000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0x0ae96000 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <5>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
> + <&dispcc DISP_CC_MDSS_ESC1_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
> + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
> +
> + operating-points-v2 = <&dsi_opp_table>;
> + power-domains = <&rpmhpd SM8550_MMCX>;
> +
> + phys = <&dsi1_phy>;
> + phy-names = "dsi";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi1_in: endpoint {
> + remote-endpoint = <&dpu_intf2_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi1_out: endpoint {
> + };
> + };
> + };
> + };
> +
> + dsi1_phy: phy@ae96400 {
> + compatible = "qcom,dsi-phy-4nm-8550";
> + reg = <0x0ae97000 0x200>,
> + <0x0ae97200 0x280>,
> + <0x0ae97500 0x400>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
> + };
> + };
> +...
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/6] drm/msm/dpu: add support for SM8550
2023-01-04 9:08 ` [PATCH 3/6] drm/msm/dpu: add support " Neil Armstrong
2023-01-04 9:45 ` Dmitry Baryshkov
@ 2023-01-08 23:12 ` Dmitry Baryshkov
1 sibling, 0 replies; 23+ messages in thread
From: Dmitry Baryshkov @ 2023-01-08 23:12 UTC (permalink / raw)
To: Neil Armstrong, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 04/01/2023 11:08, Neil Armstrong wrote:
> Add definitions for the display hardware used on Qualcomm SM8550
> platform.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197 +++++++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 4 files changed, 201 insertions(+)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/6] dt-bindings: display/msm: document the SM8550 DSI PHY
2023-01-08 23:09 ` Dmitry Baryshkov
@ 2023-01-09 8:20 ` Neil Armstrong
0 siblings, 0 replies; 23+ messages in thread
From: Neil Armstrong @ 2023-01-09 8:20 UTC (permalink / raw)
To: Dmitry Baryshkov, Krzysztof Kozlowski, Rob Clark, Abhinav Kumar,
Sean Paul, David Airlie, Daniel Vetter, Rob Herring,
Krzysztof Kozlowski, Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 09/01/2023 00:09, Dmitry Baryshkov wrote:
> On 06/01/2023 17:41, Krzysztof Kozlowski wrote:
>> On 04/01/2023 10:08, Neil Armstrong wrote:
>>> Document the SM8550 DSI PHY which is very close from the 7nm
>>> and 5nm DSI PHYs found in earlier platforms.
>>>
>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>>> ---
>>> Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
>>> index bffd161fedfd..f72727f81076 100644
>>> --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
>>> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
>>> @@ -15,6 +15,7 @@ allOf:
>>> properties:
>>> compatible:
>>> enum:
>>> + - qcom,dsi-phy-4nm-8550
>>> - qcom,dsi-phy-5nm-8350
>>> - qcom,dsi-phy-5nm-8450
>>
>> Poor patterns once allowed like to keep growing... I commented here:
>> https://lore.kernel.org/all/ccbb47e4-d780-0b1d-814e-27e86b6c369c@linaro.org/
>>
>> so let's wait for response about other compatibles.
>
> I have fixed 8350 & 8450 while applying. Please rebase on top of msm-next-lumag-next with fixed compatibles.
Ack
Thanks,
Neil
>
> Note: the DPU changes are not yet part of the msm-lumag-next.
>
>>
>>> - qcom,dsi-phy-7nm
>>>
>>
>> Best regards,
>> Krzysztof
>>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2023-01-09 8:20 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-01-04 9:08 [PATCH 0/6] drm/msm: add support for SM8450 Neil Armstrong
2023-01-04 9:08 ` [PATCH 1/6] dt-bindings: display/msm: document the SM8550 DSI PHY Neil Armstrong
2023-01-06 15:41 ` Krzysztof Kozlowski
2023-01-08 23:09 ` Dmitry Baryshkov
2023-01-09 8:20 ` Neil Armstrong
2023-01-04 9:08 ` [PATCH 2/6] dt-bindings: display/msm: document the display hardware for SM8550 Neil Armstrong
2023-01-05 2:53 ` Rob Herring
2023-01-08 23:11 ` Dmitry Baryshkov
2023-01-04 9:08 ` [PATCH 3/6] drm/msm/dpu: add support " Neil Armstrong
2023-01-04 9:45 ` Dmitry Baryshkov
2023-01-04 10:08 ` Neil Armstrong
2023-01-04 17:48 ` Dmitry Baryshkov
2023-01-05 9:59 ` neil.armstrong
2023-01-08 23:12 ` Dmitry Baryshkov
2023-01-04 9:08 ` [PATCH 4/6] drm/msm: mdss: " Neil Armstrong
2023-01-04 9:46 ` Dmitry Baryshkov
2023-01-04 9:08 ` [PATCH 5/6] drm/msm/dsi: add support for DSI-PHY on SM8550 Neil Armstrong
2023-01-04 9:53 ` Dmitry Baryshkov
2023-01-04 10:11 ` Neil Armstrong
2023-01-04 17:20 ` Dmitry Baryshkov
2023-01-04 9:08 ` [PATCH 6/6] drm/msm/dsi: add support for DSI 2.7.0 Neil Armstrong
2023-01-04 9:54 ` Dmitry Baryshkov
2023-01-08 23:09 ` [PATCH 0/6] drm/msm: add support for SM8450 Dmitry Baryshkov
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