* [PATCH v4 1/3] dt-bindings: usb: cdns-imx8qm: add imx8qm cdns3 glue layer
2023-03-23 16:31 [PATCH v4 0/3] dts: imx8qxp add cdns usb3 port Frank Li
@ 2023-03-23 16:31 ` Frank Li
2023-03-26 12:13 ` Krzysztof Kozlowski
2023-03-27 13:12 ` Rob Herring
2023-03-23 16:31 ` [PATCH v4 2/3] arm64: dts: imx8qxp: add cadence usb3 support Frank Li
2023-03-23 16:31 ` [PATCH v4 3/3] arm64: dts: freescale: imx8qxp-mek: enable cadence usb3 Frank Li
2 siblings, 2 replies; 6+ messages in thread
From: Frank Li @ 2023-03-23 16:31 UTC (permalink / raw)
To: frank.li
Cc: devicetree, festevam, imx, kernel, krzysztof.kozlowski+dt,
krzysztof.kozlowski, linux-arm-kernel, linux-imx, linux-kernel,
robh+dt, s.hauer, shawnguo
NXP imx8qm integrates 1 cdns3 IP. This is glue layer device bindings.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Change from v3 to v4
- Drop all clock-assign
Change from v2 to v3
- Drop two fixed frequency clocks, it is system reset value, no need set now.
If need, futher work/discuss on driver or dts change. It will not block this
basic enablement work.
- Drop lable
- Drop some descriptions
- Reg as second property.
Change from v1 to v2.
- new add binding doc
.../bindings/usb/fsl,imx8qm-cdns3.yaml | 104 ++++++++++++++++++
1 file changed, 104 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/fsl,imx8qm-cdns3.yaml
diff --git a/Documentation/devicetree/bindings/usb/fsl,imx8qm-cdns3.yaml b/Documentation/devicetree/bindings/usb/fsl,imx8qm-cdns3.yaml
new file mode 100644
index 000000000000..654d8704aa6f
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/fsl,imx8qm-cdns3.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 NXP
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/fsl,imx8qm-cdns3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP iMX8QM Soc USB Controller
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+properties:
+ compatible:
+ const: fsl,imx8qm-usb3
+
+ reg:
+ items:
+ - description: Register set for iMX USB3 Platform Control
+
+ "#address-cells":
+ enum: [ 1, 2 ]
+
+ "#size-cells":
+ enum: [ 1, 2 ]
+
+ ranges: true
+
+ clocks:
+ items:
+ - description: Standby clock. Used during ultra low power states.
+ - description: USB bus clock for usb3 controller.
+ - description: AXI clock for AXI interface.
+ - description: ipg clock for register access.
+ - description: Core clock for usb3 controller.
+
+ clock-names:
+ items:
+ - const: usb3_lpm_clk
+ - const: usb3_bus_clk
+ - const: usb3_aclk
+ - const: usb3_ipg_clk
+ - const: usb3_core_pclk
+
+ power-domains:
+ maxItems: 1
+
+# Required child node:
+
+patternProperties:
+ "^usb@[0-9a-f]+$":
+ $ref: cdns,usb3.yaml#
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ - clocks
+ - clock-names
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ usb@5b110000 {
+ compatible = "fsl,imx8qm-usb3";
+ reg = <0x5b110000 0x10000>;
+ ranges;
+ clocks = <&usb3_lpcg IMX_LPCG_CLK_1>,
+ <&usb3_lpcg IMX_LPCG_CLK_0>,
+ <&usb3_lpcg IMX_LPCG_CLK_7>,
+ <&usb3_lpcg IMX_LPCG_CLK_4>,
+ <&usb3_lpcg IMX_LPCG_CLK_5>;
+ clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk",
+ "usb3_ipg_clk", "usb3_core_pclk";
+ assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
+ assigned-clock-rates = <250000000>;
+ power-domains = <&pd IMX_SC_R_USB_2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ usb@5b120000 {
+ compatible = "cdns,usb3";
+ reg = <0x5b120000 0x10000>, /* memory area for OTG/DRD registers */
+ <0x5b130000 0x10000>, /* memory area for HOST registers */
+ <0x5b140000 0x10000>; /* memory area for DEVICE registers */
+ reg-names = "otg", "xhci", "dev";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host", "peripheral", "otg", "wakeup";
+ phys = <&usb3_phy>;
+ phy-names = "cdns3,usb3-phy";
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v4 1/3] dt-bindings: usb: cdns-imx8qm: add imx8qm cdns3 glue layer
2023-03-23 16:31 ` [PATCH v4 1/3] dt-bindings: usb: cdns-imx8qm: add imx8qm cdns3 glue layer Frank Li
@ 2023-03-26 12:13 ` Krzysztof Kozlowski
2023-03-27 13:12 ` Rob Herring
1 sibling, 0 replies; 6+ messages in thread
From: Krzysztof Kozlowski @ 2023-03-26 12:13 UTC (permalink / raw)
To: Frank Li
Cc: devicetree, festevam, imx, kernel, krzysztof.kozlowski+dt,
linux-arm-kernel, linux-imx, linux-kernel, robh+dt, s.hauer,
shawnguo
On 23/03/2023 17:31, Frank Li wrote:
> NXP imx8qm integrates 1 cdns3 IP. This is glue layer device bindings.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> Change from v3 to v4
> - Drop all clock-assign
>
> Change from v2 to v3
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 1/3] dt-bindings: usb: cdns-imx8qm: add imx8qm cdns3 glue layer
2023-03-23 16:31 ` [PATCH v4 1/3] dt-bindings: usb: cdns-imx8qm: add imx8qm cdns3 glue layer Frank Li
2023-03-26 12:13 ` Krzysztof Kozlowski
@ 2023-03-27 13:12 ` Rob Herring
1 sibling, 0 replies; 6+ messages in thread
From: Rob Herring @ 2023-03-27 13:12 UTC (permalink / raw)
To: Frank Li
Cc: devicetree, festevam, imx, kernel, krzysztof.kozlowski+dt,
krzysztof.kozlowski, linux-arm-kernel, linux-imx, linux-kernel,
s.hauer, shawnguo
On Thu, Mar 23, 2023 at 12:31:14PM -0400, Frank Li wrote:
> NXP imx8qm integrates 1 cdns3 IP. This is glue layer device bindings.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> Change from v3 to v4
> - Drop all clock-assign
>
> Change from v2 to v3
> - Drop two fixed frequency clocks, it is system reset value, no need set now.
> If need, futher work/discuss on driver or dts change. It will not block this
> basic enablement work.
> - Drop lable
> - Drop some descriptions
> - Reg as second property.
>
> Change from v1 to v2.
> - new add binding doc
>
> .../bindings/usb/fsl,imx8qm-cdns3.yaml | 104 ++++++++++++++++++
> 1 file changed, 104 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/fsl,imx8qm-cdns3.yaml
>
> diff --git a/Documentation/devicetree/bindings/usb/fsl,imx8qm-cdns3.yaml b/Documentation/devicetree/bindings/usb/fsl,imx8qm-cdns3.yaml
> new file mode 100644
> index 000000000000..654d8704aa6f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/fsl,imx8qm-cdns3.yaml
> @@ -0,0 +1,104 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 NXP
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/fsl,imx8qm-cdns3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP iMX8QM Soc USB Controller
> +
> +maintainers:
> + - Frank Li <Frank.Li@nxp.com>
> +
> +properties:
> + compatible:
> + const: fsl,imx8qm-usb3
> +
> + reg:
> + items:
> + - description: Register set for iMX USB3 Platform Control
> +
> + "#address-cells":
> + enum: [ 1, 2 ]
> +
> + "#size-cells":
> + enum: [ 1, 2 ]
> +
> + ranges: true
> +
> + clocks:
> + items:
> + - description: Standby clock. Used during ultra low power states.
> + - description: USB bus clock for usb3 controller.
> + - description: AXI clock for AXI interface.
> + - description: ipg clock for register access.
> + - description: Core clock for usb3 controller.
> +
> + clock-names:
> + items:
> + - const: usb3_lpm_clk
> + - const: usb3_bus_clk
> + - const: usb3_aclk
> + - const: usb3_ipg_clk
> + - const: usb3_core_pclk
lpm, bus, aclk, ipg, core (or core_pclk) are sufficient.
> +
> + power-domains:
> + maxItems: 1
> +
> +# Required child node:
> +
> +patternProperties:
> + "^usb@[0-9a-f]+$":
> + $ref: cdns,usb3.yaml#
> +
> +required:
> + - compatible
> + - reg
> + - "#address-cells"
> + - "#size-cells"
> + - ranges
> + - clocks
> + - clock-names
> + - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx8-lpcg.h>
> + #include <dt-bindings/firmware/imx/rsrc.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + usb@5b110000 {
> + compatible = "fsl,imx8qm-usb3";
> + reg = <0x5b110000 0x10000>;
> + ranges;
> + clocks = <&usb3_lpcg IMX_LPCG_CLK_1>,
> + <&usb3_lpcg IMX_LPCG_CLK_0>,
> + <&usb3_lpcg IMX_LPCG_CLK_7>,
> + <&usb3_lpcg IMX_LPCG_CLK_4>,
> + <&usb3_lpcg IMX_LPCG_CLK_5>;
> + clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk",
> + "usb3_ipg_clk", "usb3_core_pclk";
> + assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
> + assigned-clock-rates = <250000000>;
> + power-domains = <&pd IMX_SC_R_USB_2>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + usb@5b120000 {
> + compatible = "cdns,usb3";
> + reg = <0x5b120000 0x10000>, /* memory area for OTG/DRD registers */
> + <0x5b130000 0x10000>, /* memory area for HOST registers */
> + <0x5b140000 0x10000>; /* memory area for DEVICE registers */
> + reg-names = "otg", "xhci", "dev";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "host", "peripheral", "otg", "wakeup";
> + phys = <&usb3_phy>;
> + phy-names = "cdns3,usb3-phy";
> + };
> + };
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 2/3] arm64: dts: imx8qxp: add cadence usb3 support
2023-03-23 16:31 [PATCH v4 0/3] dts: imx8qxp add cdns usb3 port Frank Li
2023-03-23 16:31 ` [PATCH v4 1/3] dt-bindings: usb: cdns-imx8qm: add imx8qm cdns3 glue layer Frank Li
@ 2023-03-23 16:31 ` Frank Li
2023-03-23 16:31 ` [PATCH v4 3/3] arm64: dts: freescale: imx8qxp-mek: enable cadence usb3 Frank Li
2 siblings, 0 replies; 6+ messages in thread
From: Frank Li @ 2023-03-23 16:31 UTC (permalink / raw)
To: frank.li
Cc: devicetree, festevam, imx, kernel, krzysztof.kozlowski+dt,
krzysztof.kozlowski, linux-arm-kernel, linux-imx, linux-kernel,
robh+dt, s.hauer, shawnguo
There are cadence usb3.0 controller in 8qxp and 8qm.
Add usb3 node at common connect subsystem.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Change from v3 to v4
- none
Change from v2 to v3:
- Drop fixed frequency clock. See binding doc patch.
- move req as second property
Change from v1 to v2
- fix shawn's comments
.../boot/dts/freescale/imx8-ss-conn.dtsi | 70 +++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index 4852760adeee..a08608312f16 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -138,6 +138,54 @@ fec2: ethernet@5b050000 {
status = "disabled";
};
+ usbotg3: usb@5b110000 {
+ compatible = "fsl,imx8qm-usb3";
+ reg = <0x5b110000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&usb3_lpcg IMX_LPCG_CLK_1>,
+ <&usb3_lpcg IMX_LPCG_CLK_0>,
+ <&usb3_lpcg IMX_LPCG_CLK_7>,
+ <&usb3_lpcg IMX_LPCG_CLK_4>,
+ <&usb3_lpcg IMX_LPCG_CLK_5>;
+ clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk",
+ "usb3_ipg_clk", "usb3_core_pclk";
+ assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
+ assigned-clock-rates = <250000000>;
+ power-domains = <&pd IMX_SC_R_USB_2>;
+ status = "disabled";
+
+ usbotg3_cdns3: usb@5b120000 {
+ compatible = "cdns,usb3";
+ reg = <0x5b130000 0x10000>, /* memory area for HOST registers */
+ <0x5b140000 0x10000>, /* memory area for DEVICE registers */
+ <0x5b120000 0x10000>; /* memory area for OTG/DRD registers */
+ reg-names = "xhci", "dev", "otg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host", "peripheral", "otg", "wakeup";
+ phys = <&usb3_phy>;
+ phy-names = "cdns3,usb3-phy";
+ status = "disabled";
+ };
+ };
+
+ usb3_phy: usb-phy@5b160000 {
+ compatible = "nxp,salvo-phy";
+ reg = <0x5b160000 0x40000>;
+ clocks = <&usb3_lpcg IMX_LPCG_CLK_6>;
+ clock-names = "salvo_phy_clk";
+ power-domains = <&pd IMX_SC_R_USB_2_PHY>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
/* LPCG clocks */
sdhc0_lpcg: clock-controller@5b200000 {
compatible = "fsl,imx8qxp-lpcg";
@@ -234,4 +282,26 @@ usb2_lpcg: clock-controller@5b270000 {
clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
power-domains = <&pd IMX_SC_R_USB_0_PHY>;
};
+
+ usb3_lpcg: clock-controller@5b280000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b280000 0x10000>;
+ #clock-cells = <1>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
+ <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
+ clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
+ <&conn_ipg_clk>,
+ <&conn_ipg_clk>,
+ <&conn_ipg_clk>,
+ <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
+ clock-output-names = "usb3_app_clk",
+ "usb3_lpm_clk",
+ "usb3_ipg_clk",
+ "usb3_core_pclk",
+ "usb3_phy_clk",
+ "usb3_aclk";
+ power-domains = <&pd IMX_SC_R_USB_2_PHY>;
+ };
};
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v4 3/3] arm64: dts: freescale: imx8qxp-mek: enable cadence usb3
2023-03-23 16:31 [PATCH v4 0/3] dts: imx8qxp add cdns usb3 port Frank Li
2023-03-23 16:31 ` [PATCH v4 1/3] dt-bindings: usb: cdns-imx8qm: add imx8qm cdns3 glue layer Frank Li
2023-03-23 16:31 ` [PATCH v4 2/3] arm64: dts: imx8qxp: add cadence usb3 support Frank Li
@ 2023-03-23 16:31 ` Frank Li
2 siblings, 0 replies; 6+ messages in thread
From: Frank Li @ 2023-03-23 16:31 UTC (permalink / raw)
To: frank.li
Cc: devicetree, festevam, imx, kernel, krzysztof.kozlowski+dt,
krzysztof.kozlowski, linux-arm-kernel, linux-imx, linux-kernel,
robh+dt, s.hauer, shawnguo
Enable USB3 controller, phy and typec related nodes.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Change from v3 to v4
-none
Change from v2 to v3
-none
Change from v1 to v2
-fix shawn's comments.
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 85 +++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index afa883389456..9ba4c72f0006 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "imx8qxp.dtsi"
+#include <dt-bindings/usb/pd.h>
/ {
model = "Freescale i.MX8QXP MEK";
@@ -28,6 +29,21 @@ reg_usdhc2_vmmc: usdhc2-vmmc {
gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ gpio-sbu-mux {
+ compatible = "gpio-sbu-mux";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_typec_mux>;
+ select-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&pca9557_a 7 GPIO_ACTIVE_LOW>;
+ orientation-switch;
+
+ port {
+ usb3_data_ss: endpoint {
+ remote-endpoint = <&typec_con_ss>;
+ };
+ };
+ };
};
&dsp {
@@ -127,6 +143,42 @@ light-sensor@44 {
};
};
};
+
+ ptn5110: tcpc@50 {
+ compatible = "nxp,ptn5110";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_typec>;
+ reg = <0x50>;
+ interrupt-parent = <&lsio_gpio1>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+ port {
+ typec_dr_sw: endpoint {
+ remote-endpoint = <&usb3_drd_sw>;
+ };
+ };
+
+ usb_con1: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "source";
+ data-role = "dual";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ typec_con_ss: endpoint {
+ remote-endpoint = <&usb3_data_ss>;
+ };
+ };
+ };
+ };
+ };
+
};
&lpuart0 {
@@ -204,6 +256,27 @@ &usdhc2 {
status = "okay";
};
+&usb3_phy {
+ status = "okay";
+};
+
+&usbotg3 {
+ status = "okay";
+};
+
+&usbotg3_cdns3 {
+ dr_mode = "otg";
+ usb-role-switch;
+ status = "okay";
+
+ port {
+ usb3_drd_sw: endpoint {
+ remote-endpoint = <&typec_dr_sw>;
+ };
+ };
+};
+
+
&vpu {
compatible = "nxp,imx8qxp-vpu";
status = "okay";
@@ -267,6 +340,18 @@ IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
>;
};
+ pinctrl_typec: typecgrp {
+ fsl,pins = <
+ IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021
+ >;
+ };
+
+ pinctrl_typec_mux: typecmuxgrp {
+ fsl,pins = <
+ IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread