* [PATCH 1/4] arm64: dts: msm8953: Replace xo_board with rpmcc sourced xo
@ 2023-03-25 11:28 Adam Skladowski
2023-03-25 11:28 ` [PATCH 2/4] arm64: dts: msm8953: Provide dsi_phy clocks to gcc Adam Skladowski
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Adam Skladowski @ 2023-03-25 11:28 UTC (permalink / raw)
Cc: phone-devel, ~postmarketos/upstreaming, Adam Skladowski,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel
Assign RPM_SMD_XO_CLK_SRC from rpmcc in place
of fixed-clock where possible.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
---
arch/arm64/boot/dts/qcom/msm8953.dtsi | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index da00c2f04cda..438a70eb6152 100644
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -2,6 +2,7 @@
/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */
#include <dt-bindings/clock/qcom,gcc-msm8953.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
@@ -637,7 +638,7 @@ gcc: clock-controller@1800000 {
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
- clocks = <&xo_board>,
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>,
<0>,
<0>,
@@ -801,7 +802,7 @@ dsi0_phy: phy@1a94400 {
#clock-cells = <1>;
#phy-cells = <0>;
- clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>;
+ clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "ref";
status = "disabled";
@@ -868,7 +869,7 @@ dsi1_phy: phy@1a96400 {
#clock-cells = <1>;
#phy-cells = <0>;
- clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>;
+ clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "ref";
status = "disabled";
@@ -992,7 +993,7 @@ sdhc_1: mmc@7824900 {
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
- <&xo_board>;
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
power-domains = <&rpmpd MSM8953_VDDCX>;
@@ -1052,7 +1053,7 @@ sdhc_2: mmc@7864900 {
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
- <&xo_board>;
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
power-domains = <&rpmpd MSM8953_VDDCX>;
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/4] arm64: dts: msm8953: Provide dsi_phy clocks to gcc 2023-03-25 11:28 [PATCH 1/4] arm64: dts: msm8953: Replace xo_board with rpmcc sourced xo Adam Skladowski @ 2023-03-25 11:28 ` Adam Skladowski 2023-03-25 12:07 ` Konrad Dybcio 2023-03-27 10:12 ` Dmitry Baryshkov 2023-03-25 11:28 ` [PATCH 3/4] arm64: dts: msm8953: Drop unsupported dwc3 flag Adam Skladowski ` (3 subsequent siblings) 4 siblings, 2 replies; 10+ messages in thread From: Adam Skladowski @ 2023-03-25 11:28 UTC (permalink / raw) Cc: phone-devel, ~postmarketos/upstreaming, Adam Skladowski, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel Provide clocks from dsi_phy to gcc, this will make sure we don't fallback to global name lookup. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 438a70eb6152..5dd10c35ee0d 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -640,10 +640,10 @@ gcc: clock-controller@1800000 { #power-domain-cells = <1>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>, - <0>, - <0>, - <0>, - <0>; + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>; clock-names = "xo", "sleep", "dsi0pll", -- 2.25.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/4] arm64: dts: msm8953: Provide dsi_phy clocks to gcc 2023-03-25 11:28 ` [PATCH 2/4] arm64: dts: msm8953: Provide dsi_phy clocks to gcc Adam Skladowski @ 2023-03-25 12:07 ` Konrad Dybcio 2023-03-27 10:12 ` Dmitry Baryshkov 1 sibling, 0 replies; 10+ messages in thread From: Konrad Dybcio @ 2023-03-25 12:07 UTC (permalink / raw) To: Adam Skladowski Cc: phone-devel, ~postmarketos/upstreaming, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel On 25.03.2023 12:28, Adam Skladowski wrote: > Provide clocks from dsi_phy to gcc, this will make > sure we don't fallback to global name lookup. > > Signed-off-by: Adam Skladowski <a39.skl@gmail.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/msm8953.dtsi | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi > index 438a70eb6152..5dd10c35ee0d 100644 > --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi > @@ -640,10 +640,10 @@ gcc: clock-controller@1800000 { > #power-domain-cells = <1>; > clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, > <&sleep_clk>, > - <0>, > - <0>, > - <0>, > - <0>; > + <&dsi0_phy 1>, > + <&dsi0_phy 0>, > + <&dsi1_phy 1>, > + <&dsi1_phy 0>; > clock-names = "xo", > "sleep", > "dsi0pll", ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/4] arm64: dts: msm8953: Provide dsi_phy clocks to gcc 2023-03-25 11:28 ` [PATCH 2/4] arm64: dts: msm8953: Provide dsi_phy clocks to gcc Adam Skladowski 2023-03-25 12:07 ` Konrad Dybcio @ 2023-03-27 10:12 ` Dmitry Baryshkov 1 sibling, 0 replies; 10+ messages in thread From: Dmitry Baryshkov @ 2023-03-27 10:12 UTC (permalink / raw) To: Adam Skladowski Cc: phone-devel, ~postmarketos/upstreaming, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel On 25/03/2023 13:28, Adam Skladowski wrote: > Provide clocks from dsi_phy to gcc, this will make > sure we don't fallback to global name lookup. > > Signed-off-by: Adam Skladowski <a39.skl@gmail.com> > --- > arch/arm64/boot/dts/qcom/msm8953.dtsi | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/4] arm64: dts: msm8953: Drop unsupported dwc3 flag 2023-03-25 11:28 [PATCH 1/4] arm64: dts: msm8953: Replace xo_board with rpmcc sourced xo Adam Skladowski 2023-03-25 11:28 ` [PATCH 2/4] arm64: dts: msm8953: Provide dsi_phy clocks to gcc Adam Skladowski @ 2023-03-25 11:28 ` Adam Skladowski 2023-03-25 12:08 ` Konrad Dybcio 2023-03-25 11:28 ` [PATCH 4/4] arm64: dts: msm8953: Pad regs to 8 digits Adam Skladowski ` (2 subsequent siblings) 4 siblings, 1 reply; 10+ messages in thread From: Adam Skladowski @ 2023-03-25 11:28 UTC (permalink / raw) Cc: phone-devel, ~postmarketos/upstreaming, Adam Skladowski, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel Property phy_mode according to binding checker does not exist, drop it. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 5dd10c35ee0d..0a1bf1058cbf 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -977,7 +977,6 @@ usb3_dwc3: usb@7000000 { snps,hird-threshold = /bits/ 8 <0x00>; maximum-speed = "high-speed"; - phy_mode = "utmi"; }; }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 3/4] arm64: dts: msm8953: Drop unsupported dwc3 flag 2023-03-25 11:28 ` [PATCH 3/4] arm64: dts: msm8953: Drop unsupported dwc3 flag Adam Skladowski @ 2023-03-25 12:08 ` Konrad Dybcio 0 siblings, 0 replies; 10+ messages in thread From: Konrad Dybcio @ 2023-03-25 12:08 UTC (permalink / raw) To: Adam Skladowski Cc: phone-devel, ~postmarketos/upstreaming, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel On 25.03.2023 12:28, Adam Skladowski wrote: > Property phy_mode according to binding checker does not exist, > drop it. > > Signed-off-by: Adam Skladowski <a39.skl@gmail.com> > --- grepping for it in drivers/ also returns nothing Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/msm8953.dtsi | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi > index 5dd10c35ee0d..0a1bf1058cbf 100644 > --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi > @@ -977,7 +977,6 @@ usb3_dwc3: usb@7000000 { > snps,hird-threshold = /bits/ 8 <0x00>; > > maximum-speed = "high-speed"; > - phy_mode = "utmi"; > }; > }; > ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 4/4] arm64: dts: msm8953: Pad regs to 8 digits 2023-03-25 11:28 [PATCH 1/4] arm64: dts: msm8953: Replace xo_board with rpmcc sourced xo Adam Skladowski 2023-03-25 11:28 ` [PATCH 2/4] arm64: dts: msm8953: Provide dsi_phy clocks to gcc Adam Skladowski 2023-03-25 11:28 ` [PATCH 3/4] arm64: dts: msm8953: Drop unsupported dwc3 flag Adam Skladowski @ 2023-03-25 11:28 ` Adam Skladowski 2023-03-25 12:10 ` Konrad Dybcio 2023-03-25 12:06 ` [PATCH 1/4] arm64: dts: msm8953: Replace xo_board with rpmcc sourced xo Konrad Dybcio 2023-04-05 4:08 ` (subset) " Bjorn Andersson 4 siblings, 1 reply; 10+ messages in thread From: Adam Skladowski @ 2023-03-25 11:28 UTC (permalink / raw) Cc: phone-devel, ~postmarketos/upstreaming, Adam Skladowski, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel Follow other dtses and pad regs to 8 digits. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 98 +++++++++++++-------------- 1 file changed, 49 insertions(+), 49 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 0a1bf1058cbf..684668170353 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -350,12 +350,12 @@ soc: soc@0 { rpm_msg_ram: sram@60000 { compatible = "qcom,rpm-msg-ram"; - reg = <0x60000 0x8000>; + reg = <0x00060000 0x8000>; }; hsusb_phy: phy@79000 { compatible = "qcom,msm8953-qusb2-phy"; - reg = <0x79000 0x180>; + reg = <0x00079000 0x180>; #phy-cells = <0>; clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, @@ -378,8 +378,8 @@ rng@e3000 { tsens0: thermal-sensor@4a9000 { compatible = "qcom,msm8953-tsens", "qcom,tsens-v2"; - reg = <0x4a9000 0x1000>, /* TM */ - <0x4a8000 0x1000>; /* SROT */ + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ #qcom,sensors = <16>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; @@ -389,12 +389,12 @@ tsens0: thermal-sensor@4a9000 { restart@4ab000 { compatible = "qcom,pshold"; - reg = <0x4ab000 0x4>; + reg = <0x004ab000 0x4>; }; tlmm: pinctrl@1000000 { compatible = "qcom,msm8953-pinctrl"; - reg = <0x1000000 0x300000>; + reg = <0x01000000 0x300000>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; gpio-ranges = <&tlmm 0 0 142>; @@ -634,7 +634,7 @@ i2c_8_sleep: i2c-8-sleep-state { gcc: clock-controller@1800000 { compatible = "qcom,gcc-msm8953"; - reg = <0x1800000 0x80000>; + reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -654,25 +654,25 @@ gcc: clock-controller@1800000 { tcsr_mutex: hwlock@1905000 { compatible = "qcom,tcsr-mutex"; - reg = <0x1905000 0x20000>; + reg = <0x01905000 0x20000>; #hwlock-cells = <1>; }; tcsr: syscon@1937000 { compatible = "qcom,tcsr-msm8953", "syscon"; - reg = <0x1937000 0x30000>; + reg = <0x01937000 0x30000>; }; tcsr_phy_clk_scheme_sel: syscon@193f044 { compatible = "qcom,tcsr-msm8953", "syscon"; - reg = <0x193f044 0x4>; + reg = <0x0193f044 0x4>; }; mdss: display-subsystem@1a00000 { compatible = "qcom,mdss"; - reg = <0x1a00000 0x1000>, - <0x1ab0000 0x1040>; + reg = <0x01a00000 0x1000>, + <0x01ab0000 0x1040>; reg-names = "mdss_phys", "vbif_phys"; @@ -699,7 +699,7 @@ mdss: display-subsystem@1a00000 { mdp: display-controller@1a01000 { compatible = "qcom,msm8953-mdp5", "qcom,mdp5"; - reg = <0x1a01000 0x89000>; + reg = <0x01a01000 0x89000>; reg-names = "mdp_phys"; interrupt-parent = <&mdss>; @@ -740,7 +740,7 @@ mdp5_intf2_out: endpoint { dsi0: dsi@1a94000 { compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; - reg = <0x1a94000 0x400>; + reg = <0x01a94000 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; @@ -792,9 +792,9 @@ dsi0_out: endpoint { dsi0_phy: phy@1a94400 { compatible = "qcom,dsi-phy-14nm-8953"; - reg = <0x1a94400 0x100>, - <0x1a94500 0x300>, - <0x1a94800 0x188>; + reg = <0x01a94400 0x100>, + <0x01a94500 0x300>, + <0x01a94800 0x188>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; @@ -810,7 +810,7 @@ dsi0_phy: phy@1a94400 { dsi1: dsi@1a96000 { compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; - reg = <0x1a96000 0x400>; + reg = <0x01a96000 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; @@ -859,9 +859,9 @@ dsi1_out: endpoint { dsi1_phy: phy@1a96400 { compatible = "qcom,dsi-phy-14nm-8953"; - reg = <0x1a96400 0x100>, - <0x1a96500 0x300>, - <0x1a96800 0x188>; + reg = <0x01a96400 0x100>, + <0x01a96500 0x300>, + <0x01a96800 0x188>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; @@ -878,7 +878,7 @@ dsi1_phy: phy@1a96400 { apps_iommu: iommu@1e00000 { compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; - ranges = <0 0x1e20000 0x20000>; + ranges = <0 0x01e20000 0x20000>; clocks = <&gcc GCC_SMMU_CFG_CLK>, <&gcc GCC_APSS_TCU_ASYNC_CLK>; @@ -914,11 +914,11 @@ iommu-ctx@16000 { spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0x200f000 0x1000>, - <0x2400000 0x800000>, - <0x2c00000 0x800000>, - <0x3800000 0x200000>, - <0x200a000 0x2100>; + reg = <0x0200f000 0x1000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x2100>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; @@ -933,7 +933,7 @@ spmi_bus: spmi@200f000 { usb3: usb@70f8800 { compatible = "qcom,msm8953-dwc3", "qcom,dwc3"; - reg = <0x70f8800 0x400>; + reg = <0x070f8800 0x400>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -983,7 +983,7 @@ usb3_dwc3: usb@7000000 { sdhc_1: mmc@7824900 { compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; - reg = <0x7824900 0x500>, <0x7824000 0x800>; + reg = <0x07824900 0x500>, <0x07824000 0x800>; reg-names = "hc", "core"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, @@ -1043,7 +1043,7 @@ opp-384000000 { sdhc_2: mmc@7864900 { compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; - reg = <0x7864900 0x500>, <0x7864000 0x800>; + reg = <0x07864900 0x500>, <0x07864000 0x800>; reg-names = "hc", "core"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, @@ -1098,7 +1098,7 @@ opp-200000000 { uart_0: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78af000 0x200>; + reg = <0x078af000 0x200>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; @@ -1109,7 +1109,7 @@ uart_0: serial@78af000 { i2c_1: i2c@78b5000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b5000 0x600>; + reg = <0x078b5000 0x600>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, @@ -1127,7 +1127,7 @@ i2c_1: i2c@78b5000 { i2c_2: i2c@78b6000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b6000 0x600>; + reg = <0x078b6000 0x600>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, @@ -1145,7 +1145,7 @@ i2c_2: i2c@78b6000 { i2c_3: i2c@78b7000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b7000 0x600>; + reg = <0x078b7000 0x600>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, @@ -1162,7 +1162,7 @@ i2c_3: i2c@78b7000 { i2c_4: i2c@78b8000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b8000 0x600>; + reg = <0x078b8000 0x600>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, @@ -1179,7 +1179,7 @@ i2c_4: i2c@78b8000 { i2c_5: i2c@7af5000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x7af5000 0x600>; + reg = <0x07af5000 0x600>; interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, @@ -1196,7 +1196,7 @@ i2c_5: i2c@7af5000 { i2c_6: i2c@7af6000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x7af6000 0x600>; + reg = <0x07af6000 0x600>; interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, @@ -1213,7 +1213,7 @@ i2c_6: i2c@7af6000 { i2c_7: i2c@7af7000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x7af7000 0x600>; + reg = <0x07af7000 0x600>; interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, @@ -1230,7 +1230,7 @@ i2c_7: i2c@7af7000 { i2c_8: i2c@7af8000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x7af8000 0x600>; + reg = <0x07af8000 0x600>; interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, @@ -1254,13 +1254,13 @@ intc: interrupt-controller@b000000 { apcs: mailbox@b011000 { compatible = "qcom,msm8953-apcs-kpss-global", "syscon"; - reg = <0xb011000 0x1000>; + reg = <0x0b011000 0x1000>; #mbox-cells = <1>; }; timer@b120000 { compatible = "arm,armv7-timer-mem"; - reg = <0xb120000 0x1000>; + reg = <0x0b120000 0x1000>; #address-cells = <0x01>; #size-cells = <0x01>; ranges; @@ -1269,49 +1269,49 @@ frame@b121000 { frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xb121000 0x1000>, - <0xb122000 0x1000>; + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; }; frame@b123000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xb123000 0x1000>; + reg = <0x0b123000 0x1000>; status = "disabled"; }; frame@b124000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xb124000 0x1000>; + reg = <0x0b124000 0x1000>; status = "disabled"; }; frame@b125000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xb125000 0x1000>; + reg = <0x0b125000 0x1000>; status = "disabled"; }; frame@b126000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xb126000 0x1000>; + reg = <0x0b126000 0x1000>; status = "disabled"; }; frame@b127000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xb127000 0x1000>; + reg = <0x0b127000 0x1000>; status = "disabled"; }; frame@b128000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xb128000 0x1000>; + reg = <0x0b128000 0x1000>; status = "disabled"; }; }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 4/4] arm64: dts: msm8953: Pad regs to 8 digits 2023-03-25 11:28 ` [PATCH 4/4] arm64: dts: msm8953: Pad regs to 8 digits Adam Skladowski @ 2023-03-25 12:10 ` Konrad Dybcio 0 siblings, 0 replies; 10+ messages in thread From: Konrad Dybcio @ 2023-03-25 12:10 UTC (permalink / raw) To: Adam Skladowski Cc: phone-devel, ~postmarketos/upstreaming, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel On 25.03.2023 12:28, Adam Skladowski wrote: > Follow other dtses and pad regs to 8 digits. > > Signed-off-by: Adam Skladowski <a39.skl@gmail.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/msm8953.dtsi | 98 +++++++++++++-------------- > 1 file changed, 49 insertions(+), 49 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi > index 0a1bf1058cbf..684668170353 100644 > --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi > @@ -350,12 +350,12 @@ soc: soc@0 { > > rpm_msg_ram: sram@60000 { > compatible = "qcom,rpm-msg-ram"; > - reg = <0x60000 0x8000>; > + reg = <0x00060000 0x8000>; > }; > > hsusb_phy: phy@79000 { > compatible = "qcom,msm8953-qusb2-phy"; > - reg = <0x79000 0x180>; > + reg = <0x00079000 0x180>; > #phy-cells = <0>; > > clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, > @@ -378,8 +378,8 @@ rng@e3000 { > > tsens0: thermal-sensor@4a9000 { > compatible = "qcom,msm8953-tsens", "qcom,tsens-v2"; > - reg = <0x4a9000 0x1000>, /* TM */ > - <0x4a8000 0x1000>; /* SROT */ > + reg = <0x004a9000 0x1000>, /* TM */ > + <0x004a8000 0x1000>; /* SROT */ > #qcom,sensors = <16>; > interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; > @@ -389,12 +389,12 @@ tsens0: thermal-sensor@4a9000 { > > restart@4ab000 { > compatible = "qcom,pshold"; > - reg = <0x4ab000 0x4>; > + reg = <0x004ab000 0x4>; > }; > > tlmm: pinctrl@1000000 { > compatible = "qcom,msm8953-pinctrl"; > - reg = <0x1000000 0x300000>; > + reg = <0x01000000 0x300000>; > interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; > gpio-controller; > gpio-ranges = <&tlmm 0 0 142>; > @@ -634,7 +634,7 @@ i2c_8_sleep: i2c-8-sleep-state { > > gcc: clock-controller@1800000 { > compatible = "qcom,gcc-msm8953"; > - reg = <0x1800000 0x80000>; > + reg = <0x01800000 0x80000>; > #clock-cells = <1>; > #reset-cells = <1>; > #power-domain-cells = <1>; > @@ -654,25 +654,25 @@ gcc: clock-controller@1800000 { > > tcsr_mutex: hwlock@1905000 { > compatible = "qcom,tcsr-mutex"; > - reg = <0x1905000 0x20000>; > + reg = <0x01905000 0x20000>; > #hwlock-cells = <1>; > }; > > tcsr: syscon@1937000 { > compatible = "qcom,tcsr-msm8953", "syscon"; > - reg = <0x1937000 0x30000>; > + reg = <0x01937000 0x30000>; > }; > > tcsr_phy_clk_scheme_sel: syscon@193f044 { > compatible = "qcom,tcsr-msm8953", "syscon"; > - reg = <0x193f044 0x4>; > + reg = <0x0193f044 0x4>; > }; > > mdss: display-subsystem@1a00000 { > compatible = "qcom,mdss"; > > - reg = <0x1a00000 0x1000>, > - <0x1ab0000 0x1040>; > + reg = <0x01a00000 0x1000>, > + <0x01ab0000 0x1040>; > reg-names = "mdss_phys", > "vbif_phys"; > > @@ -699,7 +699,7 @@ mdss: display-subsystem@1a00000 { > > mdp: display-controller@1a01000 { > compatible = "qcom,msm8953-mdp5", "qcom,mdp5"; > - reg = <0x1a01000 0x89000>; > + reg = <0x01a01000 0x89000>; > reg-names = "mdp_phys"; > > interrupt-parent = <&mdss>; > @@ -740,7 +740,7 @@ mdp5_intf2_out: endpoint { > > dsi0: dsi@1a94000 { > compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; > - reg = <0x1a94000 0x400>; > + reg = <0x01a94000 0x400>; > reg-names = "dsi_ctrl"; > > interrupt-parent = <&mdss>; > @@ -792,9 +792,9 @@ dsi0_out: endpoint { > > dsi0_phy: phy@1a94400 { > compatible = "qcom,dsi-phy-14nm-8953"; > - reg = <0x1a94400 0x100>, > - <0x1a94500 0x300>, > - <0x1a94800 0x188>; > + reg = <0x01a94400 0x100>, > + <0x01a94500 0x300>, > + <0x01a94800 0x188>; > reg-names = "dsi_phy", > "dsi_phy_lane", > "dsi_pll"; > @@ -810,7 +810,7 @@ dsi0_phy: phy@1a94400 { > > dsi1: dsi@1a96000 { > compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; > - reg = <0x1a96000 0x400>; > + reg = <0x01a96000 0x400>; > reg-names = "dsi_ctrl"; > > interrupt-parent = <&mdss>; > @@ -859,9 +859,9 @@ dsi1_out: endpoint { > > dsi1_phy: phy@1a96400 { > compatible = "qcom,dsi-phy-14nm-8953"; > - reg = <0x1a96400 0x100>, > - <0x1a96500 0x300>, > - <0x1a96800 0x188>; > + reg = <0x01a96400 0x100>, > + <0x01a96500 0x300>, > + <0x01a96800 0x188>; > reg-names = "dsi_phy", > "dsi_phy_lane", > "dsi_pll"; > @@ -878,7 +878,7 @@ dsi1_phy: phy@1a96400 { > > apps_iommu: iommu@1e00000 { > compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; > - ranges = <0 0x1e20000 0x20000>; > + ranges = <0 0x01e20000 0x20000>; > > clocks = <&gcc GCC_SMMU_CFG_CLK>, > <&gcc GCC_APSS_TCU_ASYNC_CLK>; > @@ -914,11 +914,11 @@ iommu-ctx@16000 { > > spmi_bus: spmi@200f000 { > compatible = "qcom,spmi-pmic-arb"; > - reg = <0x200f000 0x1000>, > - <0x2400000 0x800000>, > - <0x2c00000 0x800000>, > - <0x3800000 0x200000>, > - <0x200a000 0x2100>; > + reg = <0x0200f000 0x1000>, > + <0x02400000 0x800000>, > + <0x02c00000 0x800000>, > + <0x03800000 0x200000>, > + <0x0200a000 0x2100>; > reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; > interrupt-names = "periph_irq"; > interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; > @@ -933,7 +933,7 @@ spmi_bus: spmi@200f000 { > > usb3: usb@70f8800 { > compatible = "qcom,msm8953-dwc3", "qcom,dwc3"; > - reg = <0x70f8800 0x400>; > + reg = <0x070f8800 0x400>; > #address-cells = <1>; > #size-cells = <1>; > ranges; > @@ -983,7 +983,7 @@ usb3_dwc3: usb@7000000 { > sdhc_1: mmc@7824900 { > compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; > > - reg = <0x7824900 0x500>, <0x7824000 0x800>; > + reg = <0x07824900 0x500>, <0x07824000 0x800>; > reg-names = "hc", "core"; > > interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, > @@ -1043,7 +1043,7 @@ opp-384000000 { > sdhc_2: mmc@7864900 { > compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; > > - reg = <0x7864900 0x500>, <0x7864000 0x800>; > + reg = <0x07864900 0x500>, <0x07864000 0x800>; > reg-names = "hc", "core"; > > interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > @@ -1098,7 +1098,7 @@ opp-200000000 { > > uart_0: serial@78af000 { > compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; > - reg = <0x78af000 0x200>; > + reg = <0x078af000 0x200>; > interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, > <&gcc GCC_BLSP1_AHB_CLK>; > @@ -1109,7 +1109,7 @@ uart_0: serial@78af000 { > > i2c_1: i2c@78b5000 { > compatible = "qcom,i2c-qup-v2.2.1"; > - reg = <0x78b5000 0x600>; > + reg = <0x078b5000 0x600>; > interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; > clock-names = "core", "iface"; > clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, > @@ -1127,7 +1127,7 @@ i2c_1: i2c@78b5000 { > > i2c_2: i2c@78b6000 { > compatible = "qcom,i2c-qup-v2.2.1"; > - reg = <0x78b6000 0x600>; > + reg = <0x078b6000 0x600>; > interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; > clock-names = "core", "iface"; > clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, > @@ -1145,7 +1145,7 @@ i2c_2: i2c@78b6000 { > > i2c_3: i2c@78b7000 { > compatible = "qcom,i2c-qup-v2.2.1"; > - reg = <0x78b7000 0x600>; > + reg = <0x078b7000 0x600>; > interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; > clock-names = "core", "iface"; > clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, > @@ -1162,7 +1162,7 @@ i2c_3: i2c@78b7000 { > > i2c_4: i2c@78b8000 { > compatible = "qcom,i2c-qup-v2.2.1"; > - reg = <0x78b8000 0x600>; > + reg = <0x078b8000 0x600>; > interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; > clock-names = "core", "iface"; > clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, > @@ -1179,7 +1179,7 @@ i2c_4: i2c@78b8000 { > > i2c_5: i2c@7af5000 { > compatible = "qcom,i2c-qup-v2.2.1"; > - reg = <0x7af5000 0x600>; > + reg = <0x07af5000 0x600>; > interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; > clock-names = "core", "iface"; > clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, > @@ -1196,7 +1196,7 @@ i2c_5: i2c@7af5000 { > > i2c_6: i2c@7af6000 { > compatible = "qcom,i2c-qup-v2.2.1"; > - reg = <0x7af6000 0x600>; > + reg = <0x07af6000 0x600>; > interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; > clock-names = "core", "iface"; > clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, > @@ -1213,7 +1213,7 @@ i2c_6: i2c@7af6000 { > > i2c_7: i2c@7af7000 { > compatible = "qcom,i2c-qup-v2.2.1"; > - reg = <0x7af7000 0x600>; > + reg = <0x07af7000 0x600>; > interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; > clock-names = "core", "iface"; > clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, > @@ -1230,7 +1230,7 @@ i2c_7: i2c@7af7000 { > > i2c_8: i2c@7af8000 { > compatible = "qcom,i2c-qup-v2.2.1"; > - reg = <0x7af8000 0x600>; > + reg = <0x07af8000 0x600>; > interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; > clock-names = "core", "iface"; > clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, > @@ -1254,13 +1254,13 @@ intc: interrupt-controller@b000000 { > > apcs: mailbox@b011000 { > compatible = "qcom,msm8953-apcs-kpss-global", "syscon"; > - reg = <0xb011000 0x1000>; > + reg = <0x0b011000 0x1000>; > #mbox-cells = <1>; > }; > > timer@b120000 { > compatible = "arm,armv7-timer-mem"; > - reg = <0xb120000 0x1000>; > + reg = <0x0b120000 0x1000>; > #address-cells = <0x01>; > #size-cells = <0x01>; > ranges; > @@ -1269,49 +1269,49 @@ frame@b121000 { > frame-number = <0>; > interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > - reg = <0xb121000 0x1000>, > - <0xb122000 0x1000>; > + reg = <0x0b121000 0x1000>, > + <0x0b122000 0x1000>; > }; > > frame@b123000 { > frame-number = <1>; > interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; > - reg = <0xb123000 0x1000>; > + reg = <0x0b123000 0x1000>; > status = "disabled"; > }; > > frame@b124000 { > frame-number = <2>; > interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; > - reg = <0xb124000 0x1000>; > + reg = <0x0b124000 0x1000>; > status = "disabled"; > }; > > frame@b125000 { > frame-number = <3>; > interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; > - reg = <0xb125000 0x1000>; > + reg = <0x0b125000 0x1000>; > status = "disabled"; > }; > > frame@b126000 { > frame-number = <4>; > interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > - reg = <0xb126000 0x1000>; > + reg = <0x0b126000 0x1000>; > status = "disabled"; > }; > > frame@b127000 { > frame-number = <5>; > interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; > - reg = <0xb127000 0x1000>; > + reg = <0x0b127000 0x1000>; > status = "disabled"; > }; > > frame@b128000 { > frame-number = <6>; > interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > - reg = <0xb128000 0x1000>; > + reg = <0x0b128000 0x1000>; > status = "disabled"; > }; > }; ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/4] arm64: dts: msm8953: Replace xo_board with rpmcc sourced xo 2023-03-25 11:28 [PATCH 1/4] arm64: dts: msm8953: Replace xo_board with rpmcc sourced xo Adam Skladowski ` (2 preceding siblings ...) 2023-03-25 11:28 ` [PATCH 4/4] arm64: dts: msm8953: Pad regs to 8 digits Adam Skladowski @ 2023-03-25 12:06 ` Konrad Dybcio 2023-04-05 4:08 ` (subset) " Bjorn Andersson 4 siblings, 0 replies; 10+ messages in thread From: Konrad Dybcio @ 2023-03-25 12:06 UTC (permalink / raw) To: Adam Skladowski Cc: phone-devel, ~postmarketos/upstreaming, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel On 25.03.2023 12:28, Adam Skladowski wrote: > Assign RPM_SMD_XO_CLK_SRC from rpmcc in place > of fixed-clock where possible. > > Signed-off-by: Adam Skladowski <a39.skl@gmail.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/msm8953.dtsi | 11 ++++++----- > 1 file changed, 6 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi > index da00c2f04cda..438a70eb6152 100644 > --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi > @@ -2,6 +2,7 @@ > /* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ > > #include <dt-bindings/clock/qcom,gcc-msm8953.h> > +#include <dt-bindings/clock/qcom,rpmcc.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/power/qcom-rpmpd.h> > @@ -637,7 +638,7 @@ gcc: clock-controller@1800000 { > #clock-cells = <1>; > #reset-cells = <1>; > #power-domain-cells = <1>; > - clocks = <&xo_board>, > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, > <&sleep_clk>, > <0>, > <0>, > @@ -801,7 +802,7 @@ dsi0_phy: phy@1a94400 { > #clock-cells = <1>; > #phy-cells = <0>; > > - clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>; > + clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; > clock-names = "iface", "ref"; > > status = "disabled"; > @@ -868,7 +869,7 @@ dsi1_phy: phy@1a96400 { > #clock-cells = <1>; > #phy-cells = <0>; > > - clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>; > + clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; > clock-names = "iface", "ref"; > > status = "disabled"; > @@ -992,7 +993,7 @@ sdhc_1: mmc@7824900 { > > clocks = <&gcc GCC_SDCC1_AHB_CLK>, > <&gcc GCC_SDCC1_APPS_CLK>, > - <&xo_board>; > + <&rpmcc RPM_SMD_XO_CLK_SRC>; > clock-names = "iface", "core", "xo"; > > power-domains = <&rpmpd MSM8953_VDDCX>; > @@ -1052,7 +1053,7 @@ sdhc_2: mmc@7864900 { > > clocks = <&gcc GCC_SDCC2_AHB_CLK>, > <&gcc GCC_SDCC2_APPS_CLK>, > - <&xo_board>; > + <&rpmcc RPM_SMD_XO_CLK_SRC>; > clock-names = "iface", "core", "xo"; > > power-domains = <&rpmpd MSM8953_VDDCX>; ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: (subset) [PATCH 1/4] arm64: dts: msm8953: Replace xo_board with rpmcc sourced xo 2023-03-25 11:28 [PATCH 1/4] arm64: dts: msm8953: Replace xo_board with rpmcc sourced xo Adam Skladowski ` (3 preceding siblings ...) 2023-03-25 12:06 ` [PATCH 1/4] arm64: dts: msm8953: Replace xo_board with rpmcc sourced xo Konrad Dybcio @ 2023-04-05 4:08 ` Bjorn Andersson 4 siblings, 0 replies; 10+ messages in thread From: Bjorn Andersson @ 2023-04-05 4:08 UTC (permalink / raw) To: Adam Skladowski Cc: linux-arm-msm, devicetree, phone-devel, Krzysztof Kozlowski, Andy Gross, Rob Herring, ~postmarketos/upstreaming, linux-kernel, Konrad Dybcio On Sat, 25 Mar 2023 12:28:49 +0100, Adam Skladowski wrote: > Assign RPM_SMD_XO_CLK_SRC from rpmcc in place > of fixed-clock where possible. > > Applied, thanks! [1/4] arm64: dts: msm8953: Replace xo_board with rpmcc sourced xo commit: 3042fb4b61c8a6ce692a4914b1970daa56e6f04e [2/4] arm64: dts: msm8953: Provide dsi_phy clocks to gcc commit: 635abd877516f6d5e35343d3c3eb233ab195ebc5 [3/4] arm64: dts: msm8953: Drop unsupported dwc3 flag commit: c0494df2cdac723f4c7df834c05d548ea3a804e9 [4/4] arm64: dts: msm8953: Pad regs to 8 digits commit: 26aae2310fd7375a5ca0dd772cd3bc57cf5e02bb Best regards, -- Bjorn Andersson <andersson@kernel.org> ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2023-04-05 4:06 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-03-25 11:28 [PATCH 1/4] arm64: dts: msm8953: Replace xo_board with rpmcc sourced xo Adam Skladowski 2023-03-25 11:28 ` [PATCH 2/4] arm64: dts: msm8953: Provide dsi_phy clocks to gcc Adam Skladowski 2023-03-25 12:07 ` Konrad Dybcio 2023-03-27 10:12 ` Dmitry Baryshkov 2023-03-25 11:28 ` [PATCH 3/4] arm64: dts: msm8953: Drop unsupported dwc3 flag Adam Skladowski 2023-03-25 12:08 ` Konrad Dybcio 2023-03-25 11:28 ` [PATCH 4/4] arm64: dts: msm8953: Pad regs to 8 digits Adam Skladowski 2023-03-25 12:10 ` Konrad Dybcio 2023-03-25 12:06 ` [PATCH 1/4] arm64: dts: msm8953: Replace xo_board with rpmcc sourced xo Konrad Dybcio 2023-04-05 4:08 ` (subset) " Bjorn Andersson
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