* [PATCH v3 0/5] Add interconnect support for SM6350
@ 2022-05-25 14:43 Luca Weiss
2022-05-25 14:43 ` [PATCH v3 2/5] dt-bindings: interconnect: qcom: Split out rpmh-common bindings Luca Weiss
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Luca Weiss @ 2022-05-25 14:43 UTC (permalink / raw)
To: linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel, Luca Weiss,
Bjorn Andersson, devicetree, Georgi Djakov, linux-kernel,
linux-pm, Odelu Kukatla
This series adds interconnect support for the various NoCs found on
sm6350.
A more special modification is allowing child NoC devices, like done for
rpm-based qcm2290 which was already merged, but now for rpmh-based
interconnect.
See also downstream dts:
https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/tags/android-11.0.0_r0.81/qcom/lagoon-bus.dtsi
Luca Weiss (5):
interconnect: qcom: icc-rpmh: Support child NoC device probe
dt-bindings: interconnect: qcom: Split out rpmh-common bindings
dt-bindings: interconnect: Add Qualcomm SM6350 NoC support
interconnect: qcom: Add SM6350 driver support
arm64: dts: qcom: sm6350: Add interconnect support
.../interconnect/qcom,rpmh-common.yaml | 43 ++
.../bindings/interconnect/qcom,rpmh.yaml | 22 +-
.../interconnect/qcom,sm6350-rpmh.yaml | 82 +++
arch/arm64/boot/dts/qcom/sm6350.dtsi | 109 ++++
drivers/interconnect/qcom/Kconfig | 9 +
drivers/interconnect/qcom/Makefile | 2 +
drivers/interconnect/qcom/icc-rpmh.c | 4 +
drivers/interconnect/qcom/sm6350.c | 493 ++++++++++++++++++
drivers/interconnect/qcom/sm6350.h | 139 +++++
.../dt-bindings/interconnect/qcom,sm6350.h | 148 ++++++
10 files changed, 1034 insertions(+), 17 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml
create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml
create mode 100644 drivers/interconnect/qcom/sm6350.c
create mode 100644 drivers/interconnect/qcom/sm6350.h
create mode 100644 include/dt-bindings/interconnect/qcom,sm6350.h
--
2.36.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 2/5] dt-bindings: interconnect: qcom: Split out rpmh-common bindings
2022-05-25 14:43 [PATCH v3 0/5] Add interconnect support for SM6350 Luca Weiss
@ 2022-05-25 14:43 ` Luca Weiss
2022-05-26 12:34 ` Krzysztof Kozlowski
2022-05-25 14:43 ` [PATCH v3 3/5] dt-bindings: interconnect: Add Qualcomm SM6350 NoC support Luca Weiss
` (3 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Luca Weiss @ 2022-05-25 14:43 UTC (permalink / raw)
To: linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel, Luca Weiss, Andy Gross,
Bjorn Andersson, Georgi Djakov, Rob Herring, Krzysztof Kozlowski,
Odelu Kukatla, linux-pm, devicetree, linux-kernel
In preparation for the platforms, split out common definitions used in
rpmh-based interconnects.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Changes since v2:
* Reorganize patches so order is more logical
* Replace bouncing maintainer email with Bjorn
* maxItems: 2 for qcom,bcm-voters and qcom,bcm-voter-names
* Remove | from some descriptions
.../interconnect/qcom,rpmh-common.yaml | 43 +++++++++++++++++++
.../bindings/interconnect/qcom,rpmh.yaml | 22 +++-------
2 files changed, 48 insertions(+), 17 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml
new file mode 100644
index 000000000000..e962e8dc9a61
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,rpmh-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm RPMh Network-On-Chip Interconnect
+
+maintainers:
+ - Georgi Djakov <georgi.djakov@linaro.org>
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description:
+ RPMh interconnect providers support system bandwidth requirements through
+ RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+ able to communicate with the BCM through the Resource State Coordinator (RSC)
+ associated with each execution environment. Provider nodes must point to at
+ least one RPMh device child node pertaining to their RSC and each provider
+ can map to multiple RPMh resources.
+
+properties:
+ '#interconnect-cells':
+ enum: [ 1, 2 ]
+
+ qcom,bcm-voters:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
+ maxItems: 2
+ description:
+ List of phandles to qcom,bcm-voter nodes that are required by
+ this interconnect to send RPMh commands.
+
+ qcom,bcm-voter-names:
+ description:
+ Names for each of the qcom,bcm-voters specified.
+ maxItems: 2
+
+required:
+ - '#interconnect-cells'
+ - qcom,bcm-voters
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
index fae3363fed02..e822dc099339 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
@@ -18,6 +18,9 @@ description: |
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
+allOf:
+ - $ref: qcom,rpmh-common.yaml#
+
properties:
reg:
maxItems: 1
@@ -131,28 +134,13 @@ properties:
- qcom,sm8450-pcie-anoc
- qcom,sm8450-system-noc
- '#interconnect-cells':
- enum: [ 1, 2 ]
-
- qcom,bcm-voters:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- items:
- maxItems: 1
- description: |
- List of phandles to qcom,bcm-voter nodes that are required by
- this interconnect to send RPMh commands.
-
- qcom,bcm-voter-names:
- description: |
- Names for each of the qcom,bcm-voters specified.
+ '#interconnect-cells': true
required:
- compatible
- reg
- - '#interconnect-cells'
- - qcom,bcm-voters
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
--
2.36.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v3 3/5] dt-bindings: interconnect: Add Qualcomm SM6350 NoC support
2022-05-25 14:43 [PATCH v3 0/5] Add interconnect support for SM6350 Luca Weiss
2022-05-25 14:43 ` [PATCH v3 2/5] dt-bindings: interconnect: qcom: Split out rpmh-common bindings Luca Weiss
@ 2022-05-25 14:43 ` Luca Weiss
2022-05-26 12:36 ` Krzysztof Kozlowski
2022-05-25 14:44 ` [PATCH v3 5/5] arm64: dts: qcom: sm6350: Add interconnect support Luca Weiss
` (2 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Luca Weiss @ 2022-05-25 14:43 UTC (permalink / raw)
To: linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel, Luca Weiss, Andy Gross,
Bjorn Andersson, Georgi Djakov, Rob Herring, Krzysztof Kozlowski,
linux-pm, devicetree, linux-kernel
Add bindings for Qualcomm SM6350 Network-On-Chip interconnect devices.
As SM6350 has two pairs of NoCs sharing the same reg, allow this in the
binding documentation, as was done for qcm2290.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Changes since v2:
* Put requires and unevaluatedProperties further down
.../interconnect/qcom,sm6350-rpmh.yaml | 82 ++++++++++
.../dt-bindings/interconnect/qcom,sm6350.h | 148 ++++++++++++++++++
2 files changed, 230 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml
create mode 100644 include/dt-bindings/interconnect/qcom,sm6350.h
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml
new file mode 100644
index 000000000000..3e3ea85b4792
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,sm6350-rpmh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6350 RPMh Network-On-Chip Interconnect
+
+maintainers:
+ - Luca Weiss <luca.weiss@fairphone.com>
+
+description: |
+ Qualcomm RPMh-based interconnect provider on SM6350.
+
+allOf:
+ - $ref: qcom,rpmh-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - qcom,sm6350-aggre1-noc
+ - qcom,sm6350-aggre2-noc
+ - qcom,sm6350-config-noc
+ - qcom,sm6350-dc-noc
+ - qcom,sm6350-gem-noc
+ - qcom,sm6350-mmss-noc
+ - qcom,sm6350-npu-noc
+ - qcom,sm6350-system-noc
+
+ reg:
+ maxItems: 1
+
+ '#interconnect-cells': true
+
+patternProperties:
+ '^interconnect-[a-z0-9\-]+$':
+ type: object
+ description:
+ The interconnect providers do not have a separate QoS register space,
+ but share parent's space.
+ $ref: qcom,rpmh-common.yaml#
+
+ properties:
+ compatible:
+ enum:
+ - qcom,sm6350-clk-virt
+ - qcom,sm6350-compute-noc
+
+ '#interconnect-cells': true
+
+ required:
+ - compatible
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ config_noc: interconnect@1500000 {
+ compatible = "qcom,sm6350-config-noc";
+ reg = <0x01500000 0x28000>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@1620000 {
+ compatible = "qcom,sm6350-system-noc";
+ reg = <0x01620000 0x17080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ clk_virt: interconnect-clk-virt {
+ compatible = "qcom,sm6350-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+ };
diff --git a/include/dt-bindings/interconnect/qcom,sm6350.h b/include/dt-bindings/interconnect/qcom,sm6350.h
new file mode 100644
index 000000000000..e662cede9aaa
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,sm6350.h
@@ -0,0 +1,148 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Qualcomm SM6350 interconnect IDs
+ *
+ * Copyright (C) 2022 Luca Weiss <luca.weiss@fairphone.com>
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM6350_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SM6350_H
+
+#define MASTER_A1NOC_CFG 0
+#define MASTER_QUP_0 1
+#define MASTER_EMMC 2
+#define MASTER_UFS_MEM 3
+#define A1NOC_SNOC_SLV 4
+#define SLAVE_SERVICE_A1NOC 5
+
+#define MASTER_A2NOC_CFG 0
+#define MASTER_QDSS_BAM 1
+#define MASTER_QUP_1 2
+#define MASTER_CRYPTO_CORE_0 3
+#define MASTER_IPA 4
+#define MASTER_QDSS_ETR 5
+#define MASTER_SDCC_2 6
+#define MASTER_USB3 7
+#define A2NOC_SNOC_SLV 8
+#define SLAVE_SERVICE_A2NOC 9
+
+#define MASTER_CAMNOC_HF0_UNCOMP 0
+#define MASTER_CAMNOC_ICP_UNCOMP 1
+#define MASTER_CAMNOC_SF_UNCOMP 2
+#define MASTER_QUP_CORE_0 3
+#define MASTER_QUP_CORE_1 4
+#define MASTER_LLCC 5
+#define SLAVE_CAMNOC_UNCOMP 6
+#define SLAVE_QUP_CORE_0 7
+#define SLAVE_QUP_CORE_1 8
+#define SLAVE_EBI_CH0 9
+
+#define MASTER_NPU 0
+#define MASTER_NPU_PROC 1
+#define SLAVE_CDSP_GEM_NOC 2
+
+#define SNOC_CNOC_MAS 0
+#define MASTER_QDSS_DAP 1
+#define SLAVE_A1NOC_CFG 2
+#define SLAVE_A2NOC_CFG 3
+#define SLAVE_AHB2PHY 4
+#define SLAVE_AHB2PHY_2 5
+#define SLAVE_AOSS 6
+#define SLAVE_BOOT_ROM 7
+#define SLAVE_CAMERA_CFG 8
+#define SLAVE_CAMERA_NRT_THROTTLE_CFG 9
+#define SLAVE_CAMERA_RT_THROTTLE_CFG 10
+#define SLAVE_CLK_CTL 11
+#define SLAVE_RBCPR_CX_CFG 12
+#define SLAVE_RBCPR_MX_CFG 13
+#define SLAVE_CRYPTO_0_CFG 14
+#define SLAVE_DCC_CFG 15
+#define SLAVE_CNOC_DDRSS 16
+#define SLAVE_DISPLAY_CFG 17
+#define SLAVE_DISPLAY_THROTTLE_CFG 18
+#define SLAVE_EMMC_CFG 19
+#define SLAVE_GLM 20
+#define SLAVE_GRAPHICS_3D_CFG 21
+#define SLAVE_IMEM_CFG 22
+#define SLAVE_IPA_CFG 23
+#define SLAVE_CNOC_MNOC_CFG 24
+#define SLAVE_CNOC_MSS 25
+#define SLAVE_NPU_CFG 26
+#define SLAVE_PDM 27
+#define SLAVE_PIMEM_CFG 28
+#define SLAVE_PRNG 29
+#define SLAVE_QDSS_CFG 30
+#define SLAVE_QM_CFG 31
+#define SLAVE_QM_MPU_CFG 32
+#define SLAVE_QUP_0 33
+#define SLAVE_QUP_1 34
+#define SLAVE_SDCC_2 35
+#define SLAVE_SECURITY 36
+#define SLAVE_SNOC_CFG 37
+#define SLAVE_TCSR 38
+#define SLAVE_UFS_MEM_CFG 39
+#define SLAVE_USB3 40
+#define SLAVE_VENUS_CFG 41
+#define SLAVE_VENUS_THROTTLE_CFG 42
+#define SLAVE_VSENSE_CTRL_CFG 43
+#define SLAVE_SERVICE_CNOC 44
+
+#define MASTER_CNOC_DC_NOC 0
+#define SLAVE_GEM_NOC_CFG 1
+#define SLAVE_LLCC_CFG 2
+
+#define MASTER_AMPSS_M0 0
+#define MASTER_SYS_TCU 1
+#define MASTER_GEM_NOC_CFG 2
+#define MASTER_COMPUTE_NOC 3
+#define MASTER_MNOC_HF_MEM_NOC 4
+#define MASTER_MNOC_SF_MEM_NOC 5
+#define MASTER_SNOC_GC_MEM_NOC 6
+#define MASTER_SNOC_SF_MEM_NOC 7
+#define MASTER_GRAPHICS_3D 8
+#define SLAVE_MCDMA_MS_MPU_CFG 9
+#define SLAVE_MSS_PROC_MS_MPU_CFG 10
+#define SLAVE_GEM_NOC_SNOC 11
+#define SLAVE_LLCC 12
+#define SLAVE_SERVICE_GEM_NOC 13
+
+#define MASTER_CNOC_MNOC_CFG 0
+#define MASTER_VIDEO_P0 1
+#define MASTER_VIDEO_PROC 2
+#define MASTER_CAMNOC_HF 3
+#define MASTER_CAMNOC_ICP 4
+#define MASTER_CAMNOC_SF 5
+#define MASTER_MDP_PORT0 6
+#define SLAVE_MNOC_HF_MEM_NOC 7
+#define SLAVE_MNOC_SF_MEM_NOC 8
+#define SLAVE_SERVICE_MNOC 9
+
+#define MASTER_NPU_SYS 0
+#define MASTER_NPU_NOC_CFG 1
+#define SLAVE_NPU_CAL_DP0 2
+#define SLAVE_NPU_CP 3
+#define SLAVE_NPU_INT_DMA_BWMON_CFG 4
+#define SLAVE_NPU_DPM 5
+#define SLAVE_ISENSE_CFG 6
+#define SLAVE_NPU_LLM_CFG 7
+#define SLAVE_NPU_TCM 8
+#define SLAVE_NPU_COMPUTE_NOC 9
+#define SLAVE_SERVICE_NPU_NOC 10
+
+#define MASTER_SNOC_CFG 0
+#define A1NOC_SNOC_MAS 1
+#define A2NOC_SNOC_MAS 2
+#define MASTER_GEM_NOC_SNOC 3
+#define MASTER_PIMEM 4
+#define MASTER_GIC 5
+#define SLAVE_APPSS 6
+#define SNOC_CNOC_SLV 7
+#define SLAVE_SNOC_GEM_NOC_GC 8
+#define SLAVE_SNOC_GEM_NOC_SF 9
+#define SLAVE_OCIMEM 10
+#define SLAVE_PIMEM 11
+#define SLAVE_SERVICE_SNOC 12
+#define SLAVE_QDSS_STM 13
+#define SLAVE_TCU 14
+
+#endif
--
2.36.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v3 5/5] arm64: dts: qcom: sm6350: Add interconnect support
2022-05-25 14:43 [PATCH v3 0/5] Add interconnect support for SM6350 Luca Weiss
2022-05-25 14:43 ` [PATCH v3 2/5] dt-bindings: interconnect: qcom: Split out rpmh-common bindings Luca Weiss
2022-05-25 14:43 ` [PATCH v3 3/5] dt-bindings: interconnect: Add Qualcomm SM6350 NoC support Luca Weiss
@ 2022-05-25 14:44 ` Luca Weiss
2022-07-18 7:58 ` Georgi Djakov
` (2 more replies)
2022-07-15 13:34 ` [PATCH v3 0/5] Add interconnect support for SM6350 Luca Weiss
2022-08-29 23:46 ` (subset) " Bjorn Andersson
4 siblings, 3 replies; 14+ messages in thread
From: Luca Weiss @ 2022-05-25 14:44 UTC (permalink / raw)
To: linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel, Luca Weiss, Andy Gross,
Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, devicetree,
linux-kernel
Add all the different NoC providers that are found in SM6350 and
populate different nodes that use the interconnect properties.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Changes since v2:
* none
arch/arm64/boot/dts/qcom/sm6350.dtsi | 109 +++++++++++++++++++++++++++
1 file changed, 109 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index fb1a0f662575..119073f19285 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1,11 +1,13 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com>
*/
#include <dt-bindings/clock/qcom,gcc-sm6350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,sm6350.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
@@ -539,6 +541,10 @@ i2c0: i2c@880000 {
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
@@ -552,6 +558,10 @@ i2c2: i2c@888000 {
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
};
@@ -578,6 +588,10 @@ i2c6: i2c@980000 {
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
@@ -591,6 +605,10 @@ i2c7: i2c@984000 {
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
@@ -604,6 +622,10 @@ i2c8: i2c@988000 {
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
@@ -615,6 +637,9 @@ uart9: serial@98c000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart9_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -628,11 +653,62 @@ i2c10: i2c@990000 {
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
};
+ config_noc: interconnect@1500000 {
+ compatible = "qcom,sm6350-config-noc";
+ reg = <0 0x01500000 0 0x28000>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@1620000 {
+ compatible = "qcom,sm6350-system-noc";
+ reg = <0 0x01620000 0 0x17080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ clk_virt: interconnect-clk-virt {
+ compatible = "qcom,sm6350-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+ };
+
+ aggre1_noc: interconnect@16e0000 {
+ compatible = "qcom,sm6350-aggre1-noc";
+ reg = <0 0x016e0000 0 0x15080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre2_noc: interconnect@1700000 {
+ compatible = "qcom,sm6350-aggre2-noc";
+ reg = <0 0x01700000 0 0x1f880>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ compute_noc: interconnect-compute-noc {
+ compatible = "qcom,sm6350-compute-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+ };
+
+ mmss_noc: interconnect@1740000 {
+ compatible = "qcom,sm6350-mmss-noc";
+ reg = <0 0x01740000 0 0x1c100>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
ufs_mem_hc: ufs@1d84000 {
compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
@@ -933,6 +1009,10 @@ sdhc_2: sdhci@8804000 {
<&gcc GCC_SDCC2_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "core", "xo";
+ interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
+ interconnect-names = "sdhc-ddr", "cpu-sdhc";
+
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
power-domains = <&rpmhpd 0>;
@@ -947,11 +1027,15 @@ sdhc2_opp_table: sdhc2-opp-table {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <790000 131000>;
+ opp-avg-kBps = <50000 50000>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <3190000 294000>;
+ opp-avg-kBps = <261438 300000>;
};
};
};
@@ -1017,12 +1101,33 @@ dp_phy: dp-phy@88ea200 {
};
};
+ dc_noc: interconnect@9160000 {
+ compatible = "qcom,sm6350-dc-noc";
+ reg = <0 0x09160000 0 0x3200>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
system-cache-controller@9200000 {
compatible = "qcom,sm6350-llcc";
reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
};
+ gem_noc: interconnect@9680000 {
+ compatible = "qcom,sm6350-gem-noc";
+ reg = <0 0x09680000 0 0x3e200>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ npu_noc: interconnect@9990000 {
+ compatible = "qcom,sm6350-npu-noc";
+ reg = <0 0x09990000 0 0x1600>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
usb_1: usb@a6f8800 {
compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
@@ -1051,6 +1156,10 @@ usb_1: usb@a6f8800 {
resets = <&gcc GCC_USB30_PRIM_BCR>;
+ interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
+ interconnect-names = "usb-ddr", "apps-usb";
+
usb_1_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
--
2.36.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: interconnect: qcom: Split out rpmh-common bindings
2022-05-25 14:43 ` [PATCH v3 2/5] dt-bindings: interconnect: qcom: Split out rpmh-common bindings Luca Weiss
@ 2022-05-26 12:34 ` Krzysztof Kozlowski
0 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-26 12:34 UTC (permalink / raw)
To: Luca Weiss, linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel, Andy Gross,
Bjorn Andersson, Georgi Djakov, Rob Herring, Krzysztof Kozlowski,
Odelu Kukatla, linux-pm, devicetree, linux-kernel
On 25/05/2022 16:43, Luca Weiss wrote:
> In preparation for the platforms, split out common definitions used in
> rpmh-based interconnects.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Changes since v2:
> * Reorganize patches so order is more logical
> * Replace bouncing maintainer email with Bjorn
> * maxItems: 2 for qcom,bcm-voters and qcom,bcm-voter-names
> * Remove | from some descriptions
>
> .../interconnect/qcom,rpmh-common.yaml | 43 +++++++++++++++++++
> .../bindings/interconnect/qcom,rpmh.yaml | 22 +++-------
> 2 files changed, 48 insertions(+), 17 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml
>
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml
> new file mode 100644
> index 000000000000..e962e8dc9a61
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml
> @@ -0,0 +1,43 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interconnect/qcom,rpmh-common.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm RPMh Network-On-Chip Interconnect
> +
> +maintainers:
> + - Georgi Djakov <georgi.djakov@linaro.org>
> + - Bjorn Andersson <bjorn.andersson@linaro.org>
> +
> +description:
> + RPMh interconnect providers support system bandwidth requirements through
> + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
> + able to communicate with the BCM through the Resource State Coordinator (RSC)
> + associated with each execution environment. Provider nodes must point to at
> + least one RPMh device child node pertaining to their RSC and each provider
> + can map to multiple RPMh resources.
> +
> +properties:
> + '#interconnect-cells':
> + enum: [ 1, 2 ]
> +
> + qcom,bcm-voters:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + maxItems: 1
> + maxItems: 2
> + description:
> + List of phandles to qcom,bcm-voter nodes that are required by
> + this interconnect to send RPMh commands.
> +
> + qcom,bcm-voter-names:
> + description:
> + Names for each of the qcom,bcm-voters specified.
> + maxItems: 2
Property above has maxItems before description, so let's make it
consistent (also above).
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 3/5] dt-bindings: interconnect: Add Qualcomm SM6350 NoC support
2022-05-25 14:43 ` [PATCH v3 3/5] dt-bindings: interconnect: Add Qualcomm SM6350 NoC support Luca Weiss
@ 2022-05-26 12:36 ` Krzysztof Kozlowski
0 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-26 12:36 UTC (permalink / raw)
To: Luca Weiss, linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel, Andy Gross,
Bjorn Andersson, Georgi Djakov, Rob Herring, Krzysztof Kozlowski,
linux-pm, devicetree, linux-kernel
On 25/05/2022 16:43, Luca Weiss wrote:
> Add bindings for Qualcomm SM6350 Network-On-Chip interconnect devices.
>
> As SM6350 has two pairs of NoCs sharing the same reg, allow this in the
> binding documentation, as was done for qcm2290.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Changes since v2:
> * Put requires and unevaluatedProperties further down
>
> .../interconnect/qcom,sm6350-rpmh.yaml | 82 ++++++++++
> .../dt-bindings/interconnect/qcom,sm6350.h | 148 ++++++++++++++++++
> 2 files changed, 230 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml
> create mode 100644 include/dt-bindings/interconnect/qcom,sm6350.h
>
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml
> new file mode 100644
> index 000000000000..3e3ea85b4792
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml
> @@ -0,0 +1,82 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interconnect/qcom,sm6350-rpmh.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM6350 RPMh Network-On-Chip Interconnect
> +
> +maintainers:
> + - Luca Weiss <luca.weiss@fairphone.com>
> +
> +description: |
No need for |.
> + Qualcomm RPMh-based interconnect provider on SM6350.
> +
> +allOf:
> + - $ref: qcom,rpmh-common.yaml#
> +
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 0/5] Add interconnect support for SM6350
2022-05-25 14:43 [PATCH v3 0/5] Add interconnect support for SM6350 Luca Weiss
` (2 preceding siblings ...)
2022-05-25 14:44 ` [PATCH v3 5/5] arm64: dts: qcom: sm6350: Add interconnect support Luca Weiss
@ 2022-07-15 13:34 ` Luca Weiss
2022-07-18 7:15 ` Georgi Djakov
2022-08-29 23:46 ` (subset) " Bjorn Andersson
4 siblings, 1 reply; 14+ messages in thread
From: Luca Weiss @ 2022-07-15 13:34 UTC (permalink / raw)
To: Luca Weiss, linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel, Bjorn Andersson,
devicetree, Georgi Djakov, linux-kernel, linux-pm, Odelu Kukatla
Hi all,
On Wed May 25, 2022 at 4:43 PM CEST, Luca Weiss wrote:
> This series adds interconnect support for the various NoCs found on
> sm6350.
>
> A more special modification is allowing child NoC devices, like done for
> rpm-based qcm2290 which was already merged, but now for rpmh-based
> interconnect.
any feedback on the two interconnect patches and the dts patch?
Georgi? Bjorn?
Thanks Krzysztof for the dt-binding review!
Regards
Luca
>
> See also downstream dts:
> https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/tags/android-11.0.0_r0.81/qcom/lagoon-bus.dtsi
>
> Luca Weiss (5):
> interconnect: qcom: icc-rpmh: Support child NoC device probe
> dt-bindings: interconnect: qcom: Split out rpmh-common bindings
> dt-bindings: interconnect: Add Qualcomm SM6350 NoC support
> interconnect: qcom: Add SM6350 driver support
> arm64: dts: qcom: sm6350: Add interconnect support
>
> .../interconnect/qcom,rpmh-common.yaml | 43 ++
> .../bindings/interconnect/qcom,rpmh.yaml | 22 +-
> .../interconnect/qcom,sm6350-rpmh.yaml | 82 +++
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 109 ++++
> drivers/interconnect/qcom/Kconfig | 9 +
> drivers/interconnect/qcom/Makefile | 2 +
> drivers/interconnect/qcom/icc-rpmh.c | 4 +
> drivers/interconnect/qcom/sm6350.c | 493 ++++++++++++++++++
> drivers/interconnect/qcom/sm6350.h | 139 +++++
> .../dt-bindings/interconnect/qcom,sm6350.h | 148 ++++++
> 10 files changed, 1034 insertions(+), 17 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml
> create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml
> create mode 100644 drivers/interconnect/qcom/sm6350.c
> create mode 100644 drivers/interconnect/qcom/sm6350.h
> create mode 100644 include/dt-bindings/interconnect/qcom,sm6350.h
>
> --
> 2.36.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 0/5] Add interconnect support for SM6350
2022-07-15 13:34 ` [PATCH v3 0/5] Add interconnect support for SM6350 Luca Weiss
@ 2022-07-18 7:15 ` Georgi Djakov
0 siblings, 0 replies; 14+ messages in thread
From: Georgi Djakov @ 2022-07-18 7:15 UTC (permalink / raw)
To: Luca Weiss, linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel, Bjorn Andersson,
devicetree, linux-kernel, linux-pm, Odelu Kukatla
On 15.07.22 16:34, Luca Weiss wrote:
> Hi all,
>
> On Wed May 25, 2022 at 4:43 PM CEST, Luca Weiss wrote:
>> This series adds interconnect support for the various NoCs found on
>> sm6350.
>>
>> A more special modification is allowing child NoC devices, like done for
>> rpm-based qcm2290 which was already merged, but now for rpmh-based
>> interconnect.
>
> any feedback on the two interconnect patches and the dts patch?
> Georgi? Bjorn?
I merged the interconnect patches.
Thanks,
Georgi
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 5/5] arm64: dts: qcom: sm6350: Add interconnect support
2022-05-25 14:44 ` [PATCH v3 5/5] arm64: dts: qcom: sm6350: Add interconnect support Luca Weiss
@ 2022-07-18 7:58 ` Georgi Djakov
2022-07-18 9:46 ` Luca Weiss
2022-08-12 12:09 ` Luca Weiss
2022-08-29 23:46 ` (subset) " Bjorn Andersson
2 siblings, 1 reply; 14+ messages in thread
From: Georgi Djakov @ 2022-07-18 7:58 UTC (permalink / raw)
To: Luca Weiss, linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel, Andy Gross,
Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, devicetree,
linux-kernel
On 25.05.22 17:44, Luca Weiss wrote:
> Add all the different NoC providers that are found in SM6350 and
> populate different nodes that use the interconnect properties.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Changes since v2:
> * none
>
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 109 +++++++++++++++++++++++++++
> 1 file changed, 109 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index fb1a0f662575..119073f19285 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -1,11 +1,13 @@
> // SPDX-License-Identifier: BSD-3-Clause
> /*
> * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
> + * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com>
> */
>
> #include <dt-bindings/clock/qcom,gcc-sm6350.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interconnect/qcom,sm6350.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/mailbox/qcom-ipcc.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> @@ -539,6 +541,10 @@ i2c0: i2c@880000 {
> interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> status = "disabled";
> };
>
> @@ -552,6 +558,10 @@ i2c2: i2c@888000 {
> interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> status = "disabled";
> };
> };
> @@ -578,6 +588,10 @@ i2c6: i2c@980000 {
> interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> status = "disabled";
> };
>
> @@ -591,6 +605,10 @@ i2c7: i2c@984000 {
> interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> status = "disabled";
> };
>
> @@ -604,6 +622,10 @@ i2c8: i2c@988000 {
> interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> status = "disabled";
> };
>
> @@ -615,6 +637,9 @@ uart9: serial@98c000 {
> pinctrl-names = "default";
> pinctrl-0 = <&qup_uart9_default>;
> interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
> + interconnect-names = "qup-core", "qup-config";
> status = "disabled";
> };
>
> @@ -628,11 +653,62 @@ i2c10: i2c@990000 {
> interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> status = "disabled";
> };
>
> };
>
> + config_noc: interconnect@1500000 {
> + compatible = "qcom,sm6350-config-noc";
> + reg = <0 0x01500000 0 0x28000>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + system_noc: interconnect@1620000 {
> + compatible = "qcom,sm6350-system-noc";
> + reg = <0 0x01620000 0 0x17080>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> +
> + clk_virt: interconnect-clk-virt {
> + compatible = "qcom,sm6350-clk-virt";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> + };
> +
> + aggre1_noc: interconnect@16e0000 {
> + compatible = "qcom,sm6350-aggre1-noc";
> + reg = <0 0x016e0000 0 0x15080>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + aggre2_noc: interconnect@1700000 {
> + compatible = "qcom,sm6350-aggre2-noc";
> + reg = <0 0x01700000 0 0x1f880>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> +
> + compute_noc: interconnect-compute-noc {
> + compatible = "qcom,sm6350-compute-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> + };
> +
> + mmss_noc: interconnect@1740000 {
> + compatible = "qcom,sm6350-mmss-noc";
> + reg = <0 0x01740000 0 0x1c100>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> ufs_mem_hc: ufs@1d84000 {
> compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
> "jedec,ufs-2.0";
> @@ -933,6 +1009,10 @@ sdhc_2: sdhci@8804000 {
> <&gcc GCC_SDCC2_APPS_CLK>,
> <&rpmhcc RPMH_CXO_CLK>;
> clock-names = "iface", "core", "xo";
> + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
> + interconnect-names = "sdhc-ddr", "cpu-sdhc";
> +
> qcom,dll-config = <0x0007642c>;
> qcom,ddr-config = <0x80040868>;
> power-domains = <&rpmhpd 0>;
> @@ -947,11 +1027,15 @@ sdhc2_opp_table: sdhc2-opp-table {
> opp-100000000 {
> opp-hz = /bits/ 64 <100000000>;
> required-opps = <&rpmhpd_opp_svs_l1>;
> + opp-peak-kBps = <790000 131000>;
> + opp-avg-kBps = <50000 50000>;
> };
>
> opp-202000000 {
> opp-hz = /bits/ 64 <202000000>;
> required-opps = <&rpmhpd_opp_nom>;
> + opp-peak-kBps = <3190000 294000>;
> + opp-avg-kBps = <261438 300000>;
Just wondering where do these values come from? Are they from the downstream DT?
The rest looks good to me.
Thanks,
Georgi
> };
> };
> };
> @@ -1017,12 +1101,33 @@ dp_phy: dp-phy@88ea200 {
> };
> };
>
> + dc_noc: interconnect@9160000 {
> + compatible = "qcom,sm6350-dc-noc";
> + reg = <0 0x09160000 0 0x3200>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> system-cache-controller@9200000 {
> compatible = "qcom,sm6350-llcc";
> reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
> reg-names = "llcc_base", "llcc_broadcast_base";
> };
>
> + gem_noc: interconnect@9680000 {
> + compatible = "qcom,sm6350-gem-noc";
> + reg = <0 0x09680000 0 0x3e200>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + npu_noc: interconnect@9990000 {
> + compatible = "qcom,sm6350-npu-noc";
> + reg = <0 0x09990000 0 0x1600>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> usb_1: usb@a6f8800 {
> compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
> reg = <0 0x0a6f8800 0 0x400>;
> @@ -1051,6 +1156,10 @@ usb_1: usb@a6f8800 {
>
> resets = <&gcc GCC_USB30_PRIM_BCR>;
>
> + interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
> + interconnect-names = "usb-ddr", "apps-usb";
> +
> usb_1_dwc3: usb@a600000 {
> compatible = "snps,dwc3";
> reg = <0 0x0a600000 0 0xcd00>;
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 5/5] arm64: dts: qcom: sm6350: Add interconnect support
2022-07-18 7:58 ` Georgi Djakov
@ 2022-07-18 9:46 ` Luca Weiss
0 siblings, 0 replies; 14+ messages in thread
From: Luca Weiss @ 2022-07-18 9:46 UTC (permalink / raw)
To: Georgi Djakov, linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel, Andy Gross,
Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, devicetree,
linux-kernel
Hi Georgi,
On Mon Jul 18, 2022 at 9:58 AM CEST, Georgi Djakov wrote:
> On 25.05.22 17:44, Luca Weiss wrote:
> > Add all the different NoC providers that are found in SM6350 and
> > populate different nodes that use the interconnect properties.
> >
> > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> > ---
> > Changes since v2:
> > * none
> >
> > arch/arm64/boot/dts/qcom/sm6350.dtsi | 109 +++++++++++++++++++++++++++
> > 1 file changed, 109 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> > index fb1a0f662575..119073f19285 100644
> > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> > @@ -1,11 +1,13 @@
> > // SPDX-License-Identifier: BSD-3-Clause
> > /*
> > * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
> > + * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com>
> > */
> >
> > #include <dt-bindings/clock/qcom,gcc-sm6350.h>
> > #include <dt-bindings/clock/qcom,rpmh.h>
> > #include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interconnect/qcom,sm6350.h>
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > #include <dt-bindings/mailbox/qcom-ipcc.h>
> > #include <dt-bindings/power/qcom-rpmpd.h>
> > @@ -539,6 +541,10 @@ i2c0: i2c@880000 {
> > interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> > #address-cells = <1>;
> > #size-cells = <0>;
> > + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> > + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
> > + <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
> > + interconnect-names = "qup-core", "qup-config", "qup-memory";
> > status = "disabled";
> > };
> >
> > @@ -552,6 +558,10 @@ i2c2: i2c@888000 {
> > interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> > #address-cells = <1>;
> > #size-cells = <0>;
> > + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> > + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
> > + <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
> > + interconnect-names = "qup-core", "qup-config", "qup-memory";
> > status = "disabled";
> > };
> > };
> > @@ -578,6 +588,10 @@ i2c6: i2c@980000 {
> > interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> > #address-cells = <1>;
> > #size-cells = <0>;
> > + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> > + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> > + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> > + interconnect-names = "qup-core", "qup-config", "qup-memory";
> > status = "disabled";
> > };
> >
> > @@ -591,6 +605,10 @@ i2c7: i2c@984000 {
> > interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> > #address-cells = <1>;
> > #size-cells = <0>;
> > + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> > + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> > + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> > + interconnect-names = "qup-core", "qup-config", "qup-memory";
> > status = "disabled";
> > };
> >
> > @@ -604,6 +622,10 @@ i2c8: i2c@988000 {
> > interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> > #address-cells = <1>;
> > #size-cells = <0>;
> > + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> > + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> > + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> > + interconnect-names = "qup-core", "qup-config", "qup-memory";
> > status = "disabled";
> > };
> >
> > @@ -615,6 +637,9 @@ uart9: serial@98c000 {
> > pinctrl-names = "default";
> > pinctrl-0 = <&qup_uart9_default>;
> > interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> > + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> > + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
> > + interconnect-names = "qup-core", "qup-config";
> > status = "disabled";
> > };
> >
> > @@ -628,11 +653,62 @@ i2c10: i2c@990000 {
> > interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> > #address-cells = <1>;
> > #size-cells = <0>;
> > + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> > + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> > + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> > + interconnect-names = "qup-core", "qup-config", "qup-memory";
> > status = "disabled";
> > };
> >
> > };
> >
> > + config_noc: interconnect@1500000 {
> > + compatible = "qcom,sm6350-config-noc";
> > + reg = <0 0x01500000 0 0x28000>;
> > + #interconnect-cells = <2>;
> > + qcom,bcm-voters = <&apps_bcm_voter>;
> > + };
> > +
> > + system_noc: interconnect@1620000 {
> > + compatible = "qcom,sm6350-system-noc";
> > + reg = <0 0x01620000 0 0x17080>;
> > + #interconnect-cells = <2>;
> > + qcom,bcm-voters = <&apps_bcm_voter>;
> > +
> > + clk_virt: interconnect-clk-virt {
> > + compatible = "qcom,sm6350-clk-virt";
> > + #interconnect-cells = <2>;
> > + qcom,bcm-voters = <&apps_bcm_voter>;
> > + };
> > + };
> > +
> > + aggre1_noc: interconnect@16e0000 {
> > + compatible = "qcom,sm6350-aggre1-noc";
> > + reg = <0 0x016e0000 0 0x15080>;
> > + #interconnect-cells = <2>;
> > + qcom,bcm-voters = <&apps_bcm_voter>;
> > + };
> > +
> > + aggre2_noc: interconnect@1700000 {
> > + compatible = "qcom,sm6350-aggre2-noc";
> > + reg = <0 0x01700000 0 0x1f880>;
> > + #interconnect-cells = <2>;
> > + qcom,bcm-voters = <&apps_bcm_voter>;
> > +
> > + compute_noc: interconnect-compute-noc {
> > + compatible = "qcom,sm6350-compute-noc";
> > + #interconnect-cells = <2>;
> > + qcom,bcm-voters = <&apps_bcm_voter>;
> > + };
> > + };
> > +
> > + mmss_noc: interconnect@1740000 {
> > + compatible = "qcom,sm6350-mmss-noc";
> > + reg = <0 0x01740000 0 0x1c100>;
> > + #interconnect-cells = <2>;
> > + qcom,bcm-voters = <&apps_bcm_voter>;
> > + };
> > +
> > ufs_mem_hc: ufs@1d84000 {
> > compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
> > "jedec,ufs-2.0";
> > @@ -933,6 +1009,10 @@ sdhc_2: sdhci@8804000 {
> > <&gcc GCC_SDCC2_APPS_CLK>,
> > <&rpmhcc RPMH_CXO_CLK>;
> > clock-names = "iface", "core", "xo";
> > + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
> > + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
> > + interconnect-names = "sdhc-ddr", "cpu-sdhc";
> > +
> > qcom,dll-config = <0x0007642c>;
> > qcom,ddr-config = <0x80040868>;
> > power-domains = <&rpmhpd 0>;
> > @@ -947,11 +1027,15 @@ sdhc2_opp_table: sdhc2-opp-table {
> > opp-100000000 {
> > opp-hz = /bits/ 64 <100000000>;
> > required-opps = <&rpmhpd_opp_svs_l1>;
> > + opp-peak-kBps = <790000 131000>;
> > + opp-avg-kBps = <50000 50000>;
> > };
> >
> > opp-202000000 {
> > opp-hz = /bits/ 64 <202000000>;
> > required-opps = <&rpmhpd_opp_nom>;
> > + opp-peak-kBps = <3190000 294000>;
> > + opp-avg-kBps = <261438 300000>;
>
> Just wondering where do these values come from? Are they from the downstream DT?
> The rest looks good to me.
Exactly, the values are part of downstream dtsi[0]. The docs for this
property are:
- qcom,msm-bus,vectors-KBps:
Arrays of unsigned integers representing:
* master-id
* slave-id
* arbitrated bandwidth in KBps
* instantaneous bandwidth in KBps
The first two paths downstream are consolidated into one here, the third
downstream is the second one here.
[0] https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/tags/android-12.1.0_r0.15/qcom/lagoon.dtsi#3165
Hope that clears it up!
Regards
Luca
>
> Thanks,
> Georgi
>
> > };
> > };
> > };
> > @@ -1017,12 +1101,33 @@ dp_phy: dp-phy@88ea200 {
> > };
> > };
> >
> > + dc_noc: interconnect@9160000 {
> > + compatible = "qcom,sm6350-dc-noc";
> > + reg = <0 0x09160000 0 0x3200>;
> > + #interconnect-cells = <2>;
> > + qcom,bcm-voters = <&apps_bcm_voter>;
> > + };
> > +
> > system-cache-controller@9200000 {
> > compatible = "qcom,sm6350-llcc";
> > reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
> > reg-names = "llcc_base", "llcc_broadcast_base";
> > };
> >
> > + gem_noc: interconnect@9680000 {
> > + compatible = "qcom,sm6350-gem-noc";
> > + reg = <0 0x09680000 0 0x3e200>;
> > + #interconnect-cells = <2>;
> > + qcom,bcm-voters = <&apps_bcm_voter>;
> > + };
> > +
> > + npu_noc: interconnect@9990000 {
> > + compatible = "qcom,sm6350-npu-noc";
> > + reg = <0 0x09990000 0 0x1600>;
> > + #interconnect-cells = <2>;
> > + qcom,bcm-voters = <&apps_bcm_voter>;
> > + };
> > +
> > usb_1: usb@a6f8800 {
> > compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
> > reg = <0 0x0a6f8800 0 0x400>;
> > @@ -1051,6 +1156,10 @@ usb_1: usb@a6f8800 {
> >
> > resets = <&gcc GCC_USB30_PRIM_BCR>;
> >
> > + interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>,
> > + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
> > + interconnect-names = "usb-ddr", "apps-usb";
> > +
> > usb_1_dwc3: usb@a600000 {
> > compatible = "snps,dwc3";
> > reg = <0 0x0a600000 0 0xcd00>;
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 5/5] arm64: dts: qcom: sm6350: Add interconnect support
2022-05-25 14:44 ` [PATCH v3 5/5] arm64: dts: qcom: sm6350: Add interconnect support Luca Weiss
2022-07-18 7:58 ` Georgi Djakov
@ 2022-08-12 12:09 ` Luca Weiss
2022-08-12 13:34 ` Krzysztof Kozlowski
2022-08-29 23:46 ` (subset) " Bjorn Andersson
2 siblings, 1 reply; 14+ messages in thread
From: Luca Weiss @ 2022-08-12 12:09 UTC (permalink / raw)
To: Luca Weiss, linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel, Andy Gross,
Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, devicetree,
linux-kernel
Hi Bjorn,
On Wed May 25, 2022 at 4:44 PM CEST, Luca Weiss wrote:
> Add all the different NoC providers that are found in SM6350 and
> populate different nodes that use the interconnect properties.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
The other patches (1-4) from this series have been merged into torvalds'
repo already, so just this one is missing from 5.20/6.0.
Could you please pick it up for the next merge window if everything's
alright with it?
Regards
Luca
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 5/5] arm64: dts: qcom: sm6350: Add interconnect support
2022-08-12 12:09 ` Luca Weiss
@ 2022-08-12 13:34 ` Krzysztof Kozlowski
0 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-08-12 13:34 UTC (permalink / raw)
To: Luca Weiss, linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel, Andy Gross,
Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, devicetree,
linux-kernel
On 12/08/2022 15:09, Luca Weiss wrote:
> Hi Bjorn,
>
> On Wed May 25, 2022 at 4:44 PM CEST, Luca Weiss wrote:
>> Add all the different NoC providers that are found in SM6350 and
>> populate different nodes that use the interconnect properties.
>>
>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>
> The other patches (1-4) from this series have been merged into torvalds'
> repo already, so just this one is missing from 5.20/6.0.
>
> Could you please pick it up for the next merge window if everything's
> alright with it?
It's still a merge window...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: (subset) [PATCH v3 0/5] Add interconnect support for SM6350
2022-05-25 14:43 [PATCH v3 0/5] Add interconnect support for SM6350 Luca Weiss
` (3 preceding siblings ...)
2022-07-15 13:34 ` [PATCH v3 0/5] Add interconnect support for SM6350 Luca Weiss
@ 2022-08-29 23:46 ` Bjorn Andersson
4 siblings, 0 replies; 14+ messages in thread
From: Bjorn Andersson @ 2022-08-29 23:46 UTC (permalink / raw)
To: linux-arm-msm, luca.weiss
Cc: linux-pm, okukatla, georgi.djakov, ~postmarketos/upstreaming,
linux-kernel, phone-devel, devicetree
On Wed, 25 May 2022 16:43:56 +0200, Luca Weiss wrote:
> This series adds interconnect support for the various NoCs found on
> sm6350.
>
> A more special modification is allowing child NoC devices, like done for
> rpm-based qcm2290 which was already merged, but now for rpmh-based
> interconnect.
>
> [...]
Applied, thanks!
[5/5] arm64: dts: qcom: sm6350: Add interconnect support
commit: 38c5c4fe17014130dee4f85e663c5d919655801e
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: (subset) [PATCH v3 5/5] arm64: dts: qcom: sm6350: Add interconnect support
2022-05-25 14:44 ` [PATCH v3 5/5] arm64: dts: qcom: sm6350: Add interconnect support Luca Weiss
2022-07-18 7:58 ` Georgi Djakov
2022-08-12 12:09 ` Luca Weiss
@ 2022-08-29 23:46 ` Bjorn Andersson
2 siblings, 0 replies; 14+ messages in thread
From: Bjorn Andersson @ 2022-08-29 23:46 UTC (permalink / raw)
To: linux-arm-msm, luca.weiss
Cc: robh+dt, ~postmarketos/upstreaming, linux-kernel, phone-devel,
krzysztof.kozlowski+dt, agross, devicetree
On Wed, 25 May 2022 16:44:01 +0200, Luca Weiss wrote:
> Add all the different NoC providers that are found in SM6350 and
> populate different nodes that use the interconnect properties.
>
>
Applied, thanks!
[5/5] arm64: dts: qcom: sm6350: Add interconnect support
commit: 38c5c4fe17014130dee4f85e663c5d919655801e
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2022-08-29 23:48 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-25 14:43 [PATCH v3 0/5] Add interconnect support for SM6350 Luca Weiss
2022-05-25 14:43 ` [PATCH v3 2/5] dt-bindings: interconnect: qcom: Split out rpmh-common bindings Luca Weiss
2022-05-26 12:34 ` Krzysztof Kozlowski
2022-05-25 14:43 ` [PATCH v3 3/5] dt-bindings: interconnect: Add Qualcomm SM6350 NoC support Luca Weiss
2022-05-26 12:36 ` Krzysztof Kozlowski
2022-05-25 14:44 ` [PATCH v3 5/5] arm64: dts: qcom: sm6350: Add interconnect support Luca Weiss
2022-07-18 7:58 ` Georgi Djakov
2022-07-18 9:46 ` Luca Weiss
2022-08-12 12:09 ` Luca Weiss
2022-08-12 13:34 ` Krzysztof Kozlowski
2022-08-29 23:46 ` (subset) " Bjorn Andersson
2022-07-15 13:34 ` [PATCH v3 0/5] Add interconnect support for SM6350 Luca Weiss
2022-07-18 7:15 ` Georgi Djakov
2022-08-29 23:46 ` (subset) " Bjorn Andersson
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