* [PATCH v7 0/6] Mediatek MT2712 clock and scpsys support
@ 2017-11-28 7:28 Weiyi Lu
[not found] ` <1511854102-23195-1-git-send-email-weiyi.lu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Weiyi Lu @ 2017-11-28 7:28 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Mike Turquette, Rob Herring
Cc: James Liao, Fan Chen, devicetree, linux-arm-kernel, linux-kernel,
linux-mediatek, linux-clk, srv_heupstream, Weiyi Lu
This series is based on v4.15-rc1 and composed of
scpsys control (PATCH 1-4) and device tree (PATCH 5-6)
changes since v6:
- Rebase to v4.15-rc1.
changes since v5:
- Refine bus protection with proper variable name
and better implementation for the if statement.
changes since v4:
- Refine scpsys and infracfg for bus protection by passing
a boolean flag to determine the register update method
changes since v3:
- Rebase to v4.14-rc1.
changes since v2:
- ensure the clocks used by clocksource driver are registered
before clocksource init() by using CLK_OF_DECLARE()
- correct the frequency of clk32k/clkrtc_ext/clkrtc_int
changes since v1:
- Rebase to v4.13-next-soc.
- Refine scpsys and infracfg for bus protection.
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v7 0/6] Mediatek MT2712 clock and scpsys support
[not found] ` <1511854102-23195-1-git-send-email-weiyi.lu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
@ 2017-11-28 7:28 ` Weiyi Lu
2017-12-15 5:50 ` Weiyi Lu
2017-11-28 7:28 ` [PATCH v7 1/6] dt-bindings: soc: add MT2712 power dt-bindings Weiyi Lu
1 sibling, 1 reply; 11+ messages in thread
From: Weiyi Lu @ 2017-11-28 7:28 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Mike Turquette, Rob Herring
Cc: James Liao, Weiyi Lu, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Fan Chen,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
This series is based on v4.15-rc1 and composed of
scpsys control (PATCH 1-4) and device tree (PATCH 5-6)
changes since v6:
- Rebase to v4.15-rc1.
changes since v5:
- Refine bus protection with proper variable name
and better implementation for the if statement.
changes since v4:
- Refine scpsys and infracfg for bus protection by passing
a boolean flag to determine the register update method
changes since v3:
- Rebase to v4.14-rc1.
changes since v2:
- ensure the clocks used by clocksource driver are registered
before clocksource init() by using CLK_OF_DECLARE()
- correct the frequency of clk32k/clkrtc_ext/clkrtc_int
changes since v1:
- Rebase to v4.13-next-soc.
- Refine scpsys and infracfg for bus protection.
*** BLURB HERE ***
Weiyi Lu (6):
dt-bindings: soc: add MT2712 power dt-bindings
soc: mediatek: extend bus protection API
soc: mediatek: add dependent clock jpgdec/audio for scpsys
soc: mediatek: add MT2712 scpsys support
arm: dts: mt2712: Add clock controller device nodes
arm: dts: Add power controller device node of MT2712
.../devicetree/bindings/soc/mediatek/scpsys.txt | 3 +
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 131 +++++++++++++++++++
drivers/soc/mediatek/mtk-infracfg.c | 26 +++-
drivers/soc/mediatek/mtk-scpsys.c | 140 ++++++++++++++++++---
include/dt-bindings/power/mt2712-power.h | 26 ++++
include/linux/soc/mediatek/infracfg.h | 7 +-
6 files changed, 311 insertions(+), 22 deletions(-)
create mode 100644 include/dt-bindings/power/mt2712-power.h
--
1.9.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v7 1/6] dt-bindings: soc: add MT2712 power dt-bindings
[not found] ` <1511854102-23195-1-git-send-email-weiyi.lu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2017-11-28 7:28 ` Weiyi Lu
@ 2017-11-28 7:28 ` Weiyi Lu
1 sibling, 0 replies; 11+ messages in thread
From: Weiyi Lu @ 2017-11-28 7:28 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Mike Turquette, Rob Herring
Cc: James Liao, Weiyi Lu, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Fan Chen,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Add power dt-bindings for MT2712.
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Weiyi Lu <weiyi.lu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
.../devicetree/bindings/soc/mediatek/scpsys.txt | 3 +++
include/dt-bindings/power/mt2712-power.h | 26 ++++++++++++++++++++++
2 files changed, 29 insertions(+)
create mode 100644 include/dt-bindings/power/mt2712-power.h
diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index 40056f7..76bf45b 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -12,11 +12,13 @@ power/power_domain.txt. It provides the power domains defined in
- include/dt-bindings/power/mt8173-power.h
- include/dt-bindings/power/mt6797-power.h
- include/dt-bindings/power/mt2701-power.h
+- include/dt-bindings/power/mt2712-power.h
- include/dt-bindings/power/mt7622-power.h
Required properties:
- compatible: Should be one of:
- "mediatek,mt2701-scpsys"
+ - "mediatek,mt2712-scpsys"
- "mediatek,mt6797-scpsys"
- "mediatek,mt7622-scpsys"
- "mediatek,mt8173-scpsys"
@@ -27,6 +29,7 @@ Required properties:
These are clocks which hardware needs to be
enabled before enabling certain power domains.
Required clocks for MT2701: "mm", "mfg", "ethif"
+ Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
Required clocks for MT6797: "mm", "mfg", "vdec"
Required clocks for MT7622: "hif_sel"
Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
diff --git a/include/dt-bindings/power/mt2712-power.h b/include/dt-bindings/power/mt2712-power.h
new file mode 100644
index 0000000..92b46d7
--- /dev/null
+++ b/include/dt-bindings/power/mt2712-power.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2017 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See http://www.gnu.org/licenses/gpl-2.0.html for more details.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT2712_POWER_H
+#define _DT_BINDINGS_POWER_MT2712_POWER_H
+
+#define MT2712_POWER_DOMAIN_MM 0
+#define MT2712_POWER_DOMAIN_VDEC 1
+#define MT2712_POWER_DOMAIN_VENC 2
+#define MT2712_POWER_DOMAIN_ISP 3
+#define MT2712_POWER_DOMAIN_AUDIO 4
+#define MT2712_POWER_DOMAIN_USB 5
+#define MT2712_POWER_DOMAIN_USB2 6
+#define MT2712_POWER_DOMAIN_MFG 7
+
+#endif /* _DT_BINDINGS_POWER_MT2712_POWER_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v7 2/6] soc: mediatek: extend bus protection API
2017-11-28 7:28 [PATCH v7 0/6] Mediatek MT2712 clock and scpsys support Weiyi Lu
[not found] ` <1511854102-23195-1-git-send-email-weiyi.lu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
@ 2017-11-28 7:28 ` Weiyi Lu
2017-11-28 7:28 ` [PATCH v7 3/6] soc: mediatek: add dependent clock jpgdec/audio for scpsys Weiyi Lu
` (3 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Weiyi Lu @ 2017-11-28 7:28 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Mike Turquette, Rob Herring
Cc: James Liao, Fan Chen, devicetree, linux-arm-kernel, linux-kernel,
linux-mediatek, linux-clk, srv_heupstream, Weiyi Lu
MT2712 add "set/clear" bus control register to each control register set
instead of providing only one "enable" control register, we could avoid
the read-modify-write racing by declaring "bus_prot_reg_update" as "false"
in scp_soc_data or declaring as "true" to use the legacy update method.
By improving the mtk-infracfg bus protection implementation to
support set/clear bus protection control method by IC configuration.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-infracfg.c | 26 ++++++++++++++++++++++----
drivers/soc/mediatek/mtk-scpsys.c | 28 ++++++++++++++++++++--------
include/linux/soc/mediatek/infracfg.h | 7 ++++---
3 files changed, 46 insertions(+), 15 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c
index dba3055..8c310de 100644
--- a/drivers/soc/mediatek/mtk-infracfg.c
+++ b/drivers/soc/mediatek/mtk-infracfg.c
@@ -19,23 +19,33 @@
#define INFRA_TOPAXI_PROTECTEN 0x0220
#define INFRA_TOPAXI_PROTECTSTA1 0x0228
+#define INFRA_TOPAXI_PROTECTEN_SET 0x0260
+#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264
/**
* mtk_infracfg_set_bus_protection - enable bus protection
* @regmap: The infracfg regmap
* @mask: The mask containing the protection bits to be enabled.
+ * @reg_update: The boolean flag determines to set the protection bits
+ * by regmap_update_bits with enable register(PROTECTEN) or
+ * by regmap_write with set register(PROTECTEN_SET).
*
* This function enables the bus protection bits for disabled power
* domains so that the system does not hang when some unit accesses the
* bus while in power down.
*/
-int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask)
+int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
+ bool reg_update)
{
unsigned long expired;
u32 val;
int ret;
- regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, mask);
+ if (reg_update)
+ regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask,
+ mask);
+ else
+ regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask);
expired = jiffies + HZ;
@@ -59,16 +69,24 @@ int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask)
* mtk_infracfg_clear_bus_protection - disable bus protection
* @regmap: The infracfg regmap
* @mask: The mask containing the protection bits to be disabled.
+ * @reg_update: The boolean flag determines to clear the protection bits
+ * by regmap_update_bits with enable register(PROTECTEN) or
+ * by regmap_write with clear register(PROTECTEN_CLR).
*
* This function disables the bus protection bits previously enabled with
* mtk_infracfg_set_bus_protection.
*/
-int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask)
+
+int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
+ bool reg_update)
{
unsigned long expired;
int ret;
- regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0);
+ if (reg_update)
+ regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0);
+ else
+ regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask);
expired = jiffies + HZ;
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index e570b6a..4c484b1 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -134,6 +134,7 @@ struct scp {
void __iomem *base;
struct regmap *infracfg;
struct scp_ctrl_reg ctrl_reg;
+ bool bus_prot_reg_update;
};
struct scp_subdomain {
@@ -147,6 +148,7 @@ struct scp_soc_data {
const struct scp_subdomain *subdomains;
int num_subdomains;
const struct scp_ctrl_reg regs;
+ bool bus_prot_reg_update;
};
static int scpsys_domain_is_on(struct scp_domain *scpd)
@@ -254,7 +256,8 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
if (scpd->data->bus_prot_mask) {
ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
- scpd->data->bus_prot_mask);
+ scpd->data->bus_prot_mask,
+ scp->bus_prot_reg_update);
if (ret)
goto err_pwr_ack;
}
@@ -289,7 +292,8 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
if (scpd->data->bus_prot_mask) {
ret = mtk_infracfg_set_bus_protection(scp->infracfg,
- scpd->data->bus_prot_mask);
+ scpd->data->bus_prot_mask,
+ scp->bus_prot_reg_update);
if (ret)
goto out;
}
@@ -371,7 +375,8 @@ static void init_clks(struct platform_device *pdev, struct clk **clk)
static struct scp *init_scp(struct platform_device *pdev,
const struct scp_domain_data *scp_domain_data, int num,
- const struct scp_ctrl_reg *scp_ctrl_reg)
+ const struct scp_ctrl_reg *scp_ctrl_reg,
+ bool bus_prot_reg_update)
{
struct genpd_onecell_data *pd_data;
struct resource *res;
@@ -386,6 +391,8 @@ static struct scp *init_scp(struct platform_device *pdev,
scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs;
scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs;
+ scp->bus_prot_reg_update = bus_prot_reg_update;
+
scp->dev = &pdev->dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -806,7 +813,8 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
- }
+ },
+ .bus_prot_reg_update = true,
};
static const struct scp_soc_data mt6797_data = {
@@ -817,7 +825,8 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS_MT6797,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797
- }
+ },
+ .bus_prot_reg_update = true,
};
static const struct scp_soc_data mt7622_data = {
@@ -826,7 +835,8 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
- }
+ },
+ .bus_prot_reg_update = true,
};
static const struct scp_soc_data mt8173_data = {
@@ -837,7 +847,8 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
- }
+ },
+ .bus_prot_reg_update = true,
};
/*
@@ -874,7 +885,8 @@ static int scpsys_probe(struct platform_device *pdev)
match = of_match_device(of_scpsys_match_tbl, &pdev->dev);
soc = (const struct scp_soc_data *)match->data;
- scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs);
+ scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs,
+ soc->bus_prot_reg_update);
if (IS_ERR(scp))
return PTR_ERR(scp);
diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
index e8d9f0d..b0a507d 100644
--- a/include/linux/soc/mediatek/infracfg.h
+++ b/include/linux/soc/mediatek/infracfg.h
@@ -28,7 +28,8 @@
#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
BIT(7) | BIT(8))
-int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask);
-int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask);
-
+int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
+ bool reg_update);
+int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
+ bool reg_update);
#endif /* __SOC_MEDIATEK_INFRACFG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v7 3/6] soc: mediatek: add dependent clock jpgdec/audio for scpsys
2017-11-28 7:28 [PATCH v7 0/6] Mediatek MT2712 clock and scpsys support Weiyi Lu
[not found] ` <1511854102-23195-1-git-send-email-weiyi.lu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2017-11-28 7:28 ` [PATCH v7 2/6] soc: mediatek: extend bus protection API Weiyi Lu
@ 2017-11-28 7:28 ` Weiyi Lu
2017-11-28 7:28 ` [PATCH v7 4/6] soc: mediatek: add MT2712 scpsys support Weiyi Lu
` (2 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Weiyi Lu @ 2017-11-28 7:28 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Mike Turquette, Rob Herring
Cc: James Liao, Fan Chen, devicetree, linux-arm-kernel, linux-kernel,
linux-mediatek, linux-clk, srv_heupstream, Weiyi Lu
There are dependent clock jpgdec/audio in scpsys on MT2712,
and will exist three dependent clocks on MT2712 VDEC.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 4c484b1..c0f3219 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -84,6 +84,8 @@ enum clk_id {
CLK_ETHIF,
CLK_VDEC,
CLK_HIFSEL,
+ CLK_JPGDEC,
+ CLK_AUDIO,
CLK_MAX,
};
@@ -96,10 +98,12 @@ enum clk_id {
"ethif",
"vdec",
"hif_sel",
+ "jpgdec",
+ "audio",
NULL,
};
-#define MAX_CLKS 2
+#define MAX_CLKS 3
struct scp_domain_data {
const char *name;
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v7 4/6] soc: mediatek: add MT2712 scpsys support
2017-11-28 7:28 [PATCH v7 0/6] Mediatek MT2712 clock and scpsys support Weiyi Lu
` (2 preceding siblings ...)
2017-11-28 7:28 ` [PATCH v7 3/6] soc: mediatek: add dependent clock jpgdec/audio for scpsys Weiyi Lu
@ 2017-11-28 7:28 ` Weiyi Lu
2017-11-28 7:28 ` [PATCH v7 5/6] arm: dts: mt2712: Add clock controller device nodes Weiyi Lu
2017-11-28 7:28 ` [PATCH v7 6/6] arm: dts: Add power controller device node of MT2712 Weiyi Lu
5 siblings, 0 replies; 11+ messages in thread
From: Weiyi Lu @ 2017-11-28 7:28 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Mike Turquette, Rob Herring
Cc: James Liao, Fan Chen, devicetree, linux-arm-kernel, linux-kernel,
linux-mediatek, linux-clk, srv_heupstream, Weiyi Lu
add scpsys driver for MT2712
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 106 +++++++++++++++++++++++++++++++++++---
1 file changed, 100 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index c0f3219..435ce5e 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -21,6 +21,7 @@
#include <linux/soc/mediatek/infracfg.h>
#include <dt-bindings/power/mt2701-power.h>
+#include <dt-bindings/power/mt2712-power.h>
#include <dt-bindings/power/mt6797-power.h>
#include <dt-bindings/power/mt7622-power.h>
#include <dt-bindings/power/mt8173-power.h>
@@ -32,7 +33,7 @@
#define SPM_DIS_PWR_CON 0x023c
#define SPM_CONN_PWR_CON 0x0280
#define SPM_VEN2_PWR_CON 0x0298
-#define SPM_AUDIO_PWR_CON 0x029c /* MT8173 */
+#define SPM_AUDIO_PWR_CON 0x029c /* MT8173, MT2712 */
#define SPM_BDP_PWR_CON 0x029c /* MT2701 */
#define SPM_ETH_PWR_CON 0x02a0
#define SPM_HIF_PWR_CON 0x02a4
@@ -40,12 +41,12 @@
#define SPM_MFG_2D_PWR_CON 0x02c0
#define SPM_MFG_ASYNC_PWR_CON 0x02c4
#define SPM_USB_PWR_CON 0x02cc
+#define SPM_USB2_PWR_CON 0x02d4 /* MT2712 */
#define SPM_ETHSYS_PWR_CON 0x02e0 /* MT7622 */
#define SPM_HIF0_PWR_CON 0x02e4 /* MT7622 */
#define SPM_HIF1_PWR_CON 0x02e8 /* MT7622 */
#define SPM_WB_PWR_CON 0x02ec /* MT7622 */
-
#define SPM_PWR_STATUS 0x060c
#define SPM_PWR_STATUS_2ND 0x0610
@@ -64,12 +65,13 @@
#define PWR_STATUS_ETH BIT(15)
#define PWR_STATUS_HIF BIT(16)
#define PWR_STATUS_IFR_MSC BIT(17)
+#define PWR_STATUS_USB2 BIT(19) /* MT2712 */
#define PWR_STATUS_VENC_LT BIT(20)
#define PWR_STATUS_VENC BIT(21)
-#define PWR_STATUS_MFG_2D BIT(22)
-#define PWR_STATUS_MFG_ASYNC BIT(23)
-#define PWR_STATUS_AUDIO BIT(24)
-#define PWR_STATUS_USB BIT(25)
+#define PWR_STATUS_MFG_2D BIT(22) /* MT8173 */
+#define PWR_STATUS_MFG_ASYNC BIT(23) /* MT8173 */
+#define PWR_STATUS_AUDIO BIT(24) /* MT8173, MT2712 */
+#define PWR_STATUS_USB BIT(25) /* MT8173, MT2712 */
#define PWR_STATUS_ETHSYS BIT(24) /* MT7622 */
#define PWR_STATUS_HIF0 BIT(25) /* MT7622 */
#define PWR_STATUS_HIF1 BIT(26) /* MT7622 */
@@ -592,6 +594,85 @@ static void mtk_register_power_domains(struct platform_device *pdev,
};
/*
+ * MT2712 power domain support
+ */
+static const struct scp_domain_data scp_domain_data_mt2712[] = {
+ [MT2712_POWER_DOMAIN_MM] = {
+ .name = "mm",
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = SPM_DIS_PWR_CON,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_MM},
+ .active_wakeup = true,
+ },
+ [MT2712_POWER_DOMAIN_VDEC] = {
+ .name = "vdec",
+ .sta_mask = PWR_STATUS_VDEC,
+ .ctl_offs = SPM_VDE_PWR_CON,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_MM, CLK_VDEC},
+ .active_wakeup = true,
+ },
+ [MT2712_POWER_DOMAIN_VENC] = {
+ .name = "venc",
+ .sta_mask = PWR_STATUS_VENC,
+ .ctl_offs = SPM_VEN_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_MM, CLK_VENC, CLK_JPGDEC},
+ .active_wakeup = true,
+ },
+ [MT2712_POWER_DOMAIN_ISP] = {
+ .name = "isp",
+ .sta_mask = PWR_STATUS_ISP,
+ .ctl_offs = SPM_ISP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .clk_id = {CLK_MM},
+ .active_wakeup = true,
+ },
+ [MT2712_POWER_DOMAIN_AUDIO] = {
+ .name = "audio",
+ .sta_mask = PWR_STATUS_AUDIO,
+ .ctl_offs = SPM_AUDIO_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .clk_id = {CLK_AUDIO},
+ .active_wakeup = true,
+ },
+ [MT2712_POWER_DOMAIN_USB] = {
+ .name = "usb",
+ .sta_mask = PWR_STATUS_USB,
+ .ctl_offs = SPM_USB_PWR_CON,
+ .sram_pdn_bits = GENMASK(10, 8),
+ .sram_pdn_ack_bits = GENMASK(14, 12),
+ .clk_id = {CLK_NONE},
+ .active_wakeup = true,
+ },
+ [MT2712_POWER_DOMAIN_USB2] = {
+ .name = "usb2",
+ .sta_mask = PWR_STATUS_USB2,
+ .ctl_offs = SPM_USB2_PWR_CON,
+ .sram_pdn_bits = GENMASK(10, 8),
+ .sram_pdn_ack_bits = GENMASK(14, 12),
+ .clk_id = {CLK_NONE},
+ .active_wakeup = true,
+ },
+ [MT2712_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = SPM_MFG_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(19, 16),
+ .clk_id = {CLK_MFG},
+ .bus_prot_mask = BIT(14) | BIT(21) | BIT(23),
+ .active_wakeup = true,
+ },
+};
+
+/*
* MT6797 power domain support
*/
@@ -821,6 +902,16 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.bus_prot_reg_update = true,
};
+static const struct scp_soc_data mt2712_data = {
+ .domains = scp_domain_data_mt2712,
+ .num_domains = ARRAY_SIZE(scp_domain_data_mt2712),
+ .regs = {
+ .pwr_sta_offs = SPM_PWR_STATUS,
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ },
+ .bus_prot_reg_update = false,
+};
+
static const struct scp_soc_data mt6797_data = {
.domains = scp_domain_data_mt6797,
.num_domains = ARRAY_SIZE(scp_domain_data_mt6797),
@@ -864,6 +955,9 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.compatible = "mediatek,mt2701-scpsys",
.data = &mt2701_data,
}, {
+ .compatible = "mediatek,mt2712-scpsys",
+ .data = &mt2712_data,
+ }, {
.compatible = "mediatek,mt6797-scpsys",
.data = &mt6797_data,
}, {
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v7 5/6] arm: dts: mt2712: Add clock controller device nodes
2017-11-28 7:28 [PATCH v7 0/6] Mediatek MT2712 clock and scpsys support Weiyi Lu
` (3 preceding siblings ...)
2017-11-28 7:28 ` [PATCH v7 4/6] soc: mediatek: add MT2712 scpsys support Weiyi Lu
@ 2017-11-28 7:28 ` Weiyi Lu
2017-12-20 18:03 ` Matthias Brugger
2017-11-28 7:28 ` [PATCH v7 6/6] arm: dts: Add power controller device node of MT2712 Weiyi Lu
5 siblings, 1 reply; 11+ messages in thread
From: Weiyi Lu @ 2017-11-28 7:28 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Mike Turquette, Rob Herring
Cc: James Liao, Fan Chen, devicetree, linux-arm-kernel, linux-kernel,
linux-mediatek, linux-clk, srv_heupstream, Weiyi Lu
Add clock controller nodes for MT2712, include topckgen, infracfg,
pericfg, mcucfg and apmixedsys. This patch also add six oscillators that
provide clocks for MT2712.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 115 ++++++++++++++++++++++++++++++
1 file changed, 115 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 5d4e406..5703793 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -5,6 +5,7 @@
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
*/
+#include <dt-bindings/clock/mt2712-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -98,6 +99,48 @@
#clock-cells = <0>;
};
+ clk26m: oscillator@0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ clk32k: oscillator@1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "clk32k";
+ };
+
+ clkfpc: oscillator@2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "clkfpc";
+ };
+
+ clkaud_ext_i_0: oscillator@3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <6500000>;
+ clock-output-names = "clkaud_ext_i_0";
+ };
+
+ clkaud_ext_i_1: oscillator@4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <196608000>;
+ clock-output-names = "clkaud_ext_i_1";
+ };
+
+ clkaud_ext_i_2: oscillator@5 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <180633600>;
+ clock-output-names = "clkaud_ext_i_2";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
@@ -111,6 +154,24 @@
(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
};
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt2712-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt2712-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt2712-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
uart5: serial@1000f000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
@@ -121,6 +182,18 @@
status = "disabled";
};
+ apmixedsys: syscon@10209000 {
+ compatible = "mediatek,mt2712-apmixedsys", "syscon";
+ reg = <0 0x10209000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mcucfg: syscon@10220000 {
+ compatible = "mediatek,mt2712-mcucfg", "syscon";
+ reg = <0 0x10220000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
sysirq: interrupt-controller@10220a80 {
compatible = "mediatek,mt2712-sysirq",
"mediatek,mt6577-sysirq";
@@ -192,5 +265,47 @@
clock-names = "baud", "bus";
status = "disabled";
};
+
+ mfgcfg: syscon@13000000 {
+ compatible = "mediatek,mt2712-mfgcfg", "syscon";
+ reg = <0 0x13000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt2712-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: syscon@15000000 {
+ compatible = "mediatek,mt2712-imgsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ bdpsys: syscon@15010000 {
+ compatible = "mediatek,mt2712-bdpsys", "syscon";
+ reg = <0 0x15010000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: syscon@16000000 {
+ compatible = "mediatek,mt2712-vdecsys", "syscon";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: syscon@18000000 {
+ compatible = "mediatek,mt2712-vencsys", "syscon";
+ reg = <0 0x18000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ jpgdecsys: syscon@19000000 {
+ compatible = "mediatek,mt2712-jpgdecsys", "syscon";
+ reg = <0 0x19000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
};
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v7 6/6] arm: dts: Add power controller device node of MT2712
2017-11-28 7:28 [PATCH v7 0/6] Mediatek MT2712 clock and scpsys support Weiyi Lu
` (4 preceding siblings ...)
2017-11-28 7:28 ` [PATCH v7 5/6] arm: dts: mt2712: Add clock controller device nodes Weiyi Lu
@ 2017-11-28 7:28 ` Weiyi Lu
5 siblings, 0 replies; 11+ messages in thread
From: Weiyi Lu @ 2017-11-28 7:28 UTC (permalink / raw)
To: Matthias Brugger, Stephen Boyd, Mike Turquette, Rob Herring
Cc: James Liao, Fan Chen, devicetree, linux-arm-kernel, linux-kernel,
linux-mediatek, linux-clk, srv_heupstream, Weiyi Lu
add power controller node for MT2712
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 5703793..61dd763 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mt2712-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/mt2712-power.h>
/ {
compatible = "mediatek,mt2712";
@@ -172,6 +173,21 @@
#clock-cells = <1>;
};
+ scpsys: scpsys@10006000 {
+ compatible = "mediatek,mt2712-scpsys", "syscon";
+ #power-domain-cells = <1>;
+ reg = <0 0x10006000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_MFG_SEL>,
+ <&topckgen CLK_TOP_VENC_SEL>,
+ <&topckgen CLK_TOP_JPGDEC_SEL>,
+ <&topckgen CLK_TOP_A1SYS_HP_SEL>,
+ <&topckgen CLK_TOP_VDEC_SEL>;
+ clock-names = "mm", "mfg", "venc",
+ "jpgdec", "audio", "vdec";
+ infracfg = <&infracfg>;
+ };
+
uart5: serial@1000f000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v7 0/6] Mediatek MT2712 clock and scpsys support
2017-11-28 7:28 ` Weiyi Lu
@ 2017-12-15 5:50 ` Weiyi Lu
2017-12-20 18:02 ` Matthias Brugger
0 siblings, 1 reply; 11+ messages in thread
From: Weiyi Lu @ 2017-12-15 5:50 UTC (permalink / raw)
To: Matthias Brugger
Cc: Stephen Boyd, Mike Turquette, Rob Herring, James Liao, Fan Chen,
devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
linux-clk, srv_heupstream
On Tue, 2017-11-28 at 15:28 +0800, Weiyi Lu wrote:
Hi Matthias,
Just gentle ping. Many thanks.
> This series is based on v4.15-rc1 and composed of
> scpsys control (PATCH 1-4) and device tree (PATCH 5-6)
>
> changes since v6:
> - Rebase to v4.15-rc1.
>
> changes since v5:
> - Refine bus protection with proper variable name
> and better implementation for the if statement.
>
> changes since v4:
> - Refine scpsys and infracfg for bus protection by passing
> a boolean flag to determine the register update method
>
> changes since v3:
> - Rebase to v4.14-rc1.
>
> changes since v2:
> - ensure the clocks used by clocksource driver are registered
> before clocksource init() by using CLK_OF_DECLARE()
> - correct the frequency of clk32k/clkrtc_ext/clkrtc_int
>
> changes since v1:
> - Rebase to v4.13-next-soc.
> - Refine scpsys and infracfg for bus protection.
>
> *** BLURB HERE ***
>
> Weiyi Lu (6):
> dt-bindings: soc: add MT2712 power dt-bindings
> soc: mediatek: extend bus protection API
> soc: mediatek: add dependent clock jpgdec/audio for scpsys
> soc: mediatek: add MT2712 scpsys support
> arm: dts: mt2712: Add clock controller device nodes
> arm: dts: Add power controller device node of MT2712
>
> .../devicetree/bindings/soc/mediatek/scpsys.txt | 3 +
> arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 131 +++++++++++++++++++
> drivers/soc/mediatek/mtk-infracfg.c | 26 +++-
> drivers/soc/mediatek/mtk-scpsys.c | 140 ++++++++++++++++++---
> include/dt-bindings/power/mt2712-power.h | 26 ++++
> include/linux/soc/mediatek/infracfg.h | 7 +-
> 6 files changed, 311 insertions(+), 22 deletions(-)
> create mode 100644 include/dt-bindings/power/mt2712-power.h
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v7 0/6] Mediatek MT2712 clock and scpsys support
2017-12-15 5:50 ` Weiyi Lu
@ 2017-12-20 18:02 ` Matthias Brugger
0 siblings, 0 replies; 11+ messages in thread
From: Matthias Brugger @ 2017-12-20 18:02 UTC (permalink / raw)
To: Weiyi Lu
Cc: Stephen Boyd, Mike Turquette, Rob Herring, James Liao, Fan Chen,
devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
linux-clk, srv_heupstream
On 12/15/2017 06:50 AM, Weiyi Lu wrote:
> On Tue, 2017-11-28 at 15:28 +0800, Weiyi Lu wrote:
>
> Hi Matthias,
> Just gentle ping. Many thanks.
>
Now pushed to v4.15-next thanks
>> This series is based on v4.15-rc1 and composed of
>> scpsys control (PATCH 1-4) and device tree (PATCH 5-6)
>>
>> changes since v6:
>> - Rebase to v4.15-rc1.
>>
>> changes since v5:
>> - Refine bus protection with proper variable name
>> and better implementation for the if statement.
>>
>> changes since v4:
>> - Refine scpsys and infracfg for bus protection by passing
>> a boolean flag to determine the register update method
>>
>> changes since v3:
>> - Rebase to v4.14-rc1.
>>
>> changes since v2:
>> - ensure the clocks used by clocksource driver are registered
>> before clocksource init() by using CLK_OF_DECLARE()
>> - correct the frequency of clk32k/clkrtc_ext/clkrtc_int
>>
>> changes since v1:
>> - Rebase to v4.13-next-soc.
>> - Refine scpsys and infracfg for bus protection.
>>
>> *** BLURB HERE ***
>>
>> Weiyi Lu (6):
>> dt-bindings: soc: add MT2712 power dt-bindings
>> soc: mediatek: extend bus protection API
>> soc: mediatek: add dependent clock jpgdec/audio for scpsys
>> soc: mediatek: add MT2712 scpsys support
>> arm: dts: mt2712: Add clock controller device nodes
>> arm: dts: Add power controller device node of MT2712
>>
>> .../devicetree/bindings/soc/mediatek/scpsys.txt | 3 +
>> arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 131 +++++++++++++++++++
>> drivers/soc/mediatek/mtk-infracfg.c | 26 +++-
>> drivers/soc/mediatek/mtk-scpsys.c | 140 ++++++++++++++++++---
>> include/dt-bindings/power/mt2712-power.h | 26 ++++
>> include/linux/soc/mediatek/infracfg.h | 7 +-
>> 6 files changed, 311 insertions(+), 22 deletions(-)
>> create mode 100644 include/dt-bindings/power/mt2712-power.h
>>
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v7 5/6] arm: dts: mt2712: Add clock controller device nodes
2017-11-28 7:28 ` [PATCH v7 5/6] arm: dts: mt2712: Add clock controller device nodes Weiyi Lu
@ 2017-12-20 18:03 ` Matthias Brugger
0 siblings, 0 replies; 11+ messages in thread
From: Matthias Brugger @ 2017-12-20 18:03 UTC (permalink / raw)
To: Weiyi Lu, Stephen Boyd, Mike Turquette, Rob Herring
Cc: James Liao, Fan Chen, devicetree, linux-arm-kernel, linux-kernel,
linux-mediatek, linux-clk, srv_heupstream
On 11/28/2017 08:28 AM, Weiyi Lu wrote:
> Add clock controller nodes for MT2712, include topckgen, infracfg,
> pericfg, mcucfg and apmixedsys. This patch also add six oscillators that
> provide clocks for MT2712.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 115 ++++++++++++++++++++++++++++++
> 1 file changed, 115 insertions(+)
I fixed the subject line for you, but the next time please take care to start
the line with "arm64" instead of "arm"
Thanks,
Matthias
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> index 5d4e406..5703793 100644
> --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> @@ -5,6 +5,7 @@
> * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> */
>
> +#include <dt-bindings/clock/mt2712-clk.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
>
> @@ -98,6 +99,48 @@
> #clock-cells = <0>;
> };
>
> + clk26m: oscillator@0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + clock-output-names = "clk26m";
> + };
> +
> + clk32k: oscillator@1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + clock-output-names = "clk32k";
> + };
> +
> + clkfpc: oscillator@2 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
> + clock-output-names = "clkfpc";
> + };
> +
> + clkaud_ext_i_0: oscillator@3 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <6500000>;
> + clock-output-names = "clkaud_ext_i_0";
> + };
> +
> + clkaud_ext_i_1: oscillator@4 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <196608000>;
> + clock-output-names = "clkaud_ext_i_1";
> + };
> +
> + clkaud_ext_i_2: oscillator@5 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <180633600>;
> + clock-output-names = "clkaud_ext_i_2";
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupt-parent = <&gic>;
> @@ -111,6 +154,24 @@
> (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
> };
>
> + topckgen: syscon@10000000 {
> + compatible = "mediatek,mt2712-topckgen", "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + infracfg: syscon@10001000 {
> + compatible = "mediatek,mt2712-infracfg", "syscon";
> + reg = <0 0x10001000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + pericfg: syscon@10003000 {
> + compatible = "mediatek,mt2712-pericfg", "syscon";
> + reg = <0 0x10003000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> uart5: serial@1000f000 {
> compatible = "mediatek,mt2712-uart",
> "mediatek,mt6577-uart";
> @@ -121,6 +182,18 @@
> status = "disabled";
> };
>
> + apmixedsys: syscon@10209000 {
> + compatible = "mediatek,mt2712-apmixedsys", "syscon";
> + reg = <0 0x10209000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mcucfg: syscon@10220000 {
> + compatible = "mediatek,mt2712-mcucfg", "syscon";
> + reg = <0 0x10220000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> sysirq: interrupt-controller@10220a80 {
> compatible = "mediatek,mt2712-sysirq",
> "mediatek,mt6577-sysirq";
> @@ -192,5 +265,47 @@
> clock-names = "baud", "bus";
> status = "disabled";
> };
> +
> + mfgcfg: syscon@13000000 {
> + compatible = "mediatek,mt2712-mfgcfg", "syscon";
> + reg = <0 0x13000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mmsys: syscon@14000000 {
> + compatible = "mediatek,mt2712-mmsys", "syscon";
> + reg = <0 0x14000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + imgsys: syscon@15000000 {
> + compatible = "mediatek,mt2712-imgsys", "syscon";
> + reg = <0 0x15000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + bdpsys: syscon@15010000 {
> + compatible = "mediatek,mt2712-bdpsys", "syscon";
> + reg = <0 0x15010000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + vdecsys: syscon@16000000 {
> + compatible = "mediatek,mt2712-vdecsys", "syscon";
> + reg = <0 0x16000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + vencsys: syscon@18000000 {
> + compatible = "mediatek,mt2712-vencsys", "syscon";
> + reg = <0 0x18000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + jpgdecsys: syscon@19000000 {
> + compatible = "mediatek,mt2712-jpgdecsys", "syscon";
> + reg = <0 0x19000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> };
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2017-12-20 18:03 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-28 7:28 [PATCH v7 0/6] Mediatek MT2712 clock and scpsys support Weiyi Lu
[not found] ` <1511854102-23195-1-git-send-email-weiyi.lu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2017-11-28 7:28 ` Weiyi Lu
2017-12-15 5:50 ` Weiyi Lu
2017-12-20 18:02 ` Matthias Brugger
2017-11-28 7:28 ` [PATCH v7 1/6] dt-bindings: soc: add MT2712 power dt-bindings Weiyi Lu
2017-11-28 7:28 ` [PATCH v7 2/6] soc: mediatek: extend bus protection API Weiyi Lu
2017-11-28 7:28 ` [PATCH v7 3/6] soc: mediatek: add dependent clock jpgdec/audio for scpsys Weiyi Lu
2017-11-28 7:28 ` [PATCH v7 4/6] soc: mediatek: add MT2712 scpsys support Weiyi Lu
2017-11-28 7:28 ` [PATCH v7 5/6] arm: dts: mt2712: Add clock controller device nodes Weiyi Lu
2017-12-20 18:03 ` Matthias Brugger
2017-11-28 7:28 ` [PATCH v7 6/6] arm: dts: Add power controller device node of MT2712 Weiyi Lu
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