[PATCH V2 0/7] ARM: OMAP2+: Add device-tree support for timers

[PATCH V2 0/7] ARM: OMAP2+: Add device-tree support for timers

[Jon Hunter]

This series adds device-tree support for the timers on OMAP2+ devices
including AM33xx.

Testing:
1. I have booted linux with this series on OMAP2420 H4, OMAP3430 Beagle and
   OMAP4430 Panda with/without device-tree present.
2. Vaibhav has booted linux on AM335x Beagle bone (thanks!)
3. I have tested the all the timers (not used by the kernel as sys-timers) on
   OMAP2420 H4, OMAP3430 Beagle and OMAP4430 Panda with/without device-tree with
   this series. The testing includes ...
   a. Configuring, starting a timer and checking the counter value is
      incrementing.
   b. Testing timer overflow interrupt when timer expires.
   c. Using different clock sources to operate the timer with.
4. Verified on OMAP4430 and AM33xx (Vaibhav) that the kernel boots when using a
   GP timer as clock-source (default for OMAP is 32k-sync timer). Thanks to
   Vaibhav for catching and tracking down a bug when using a GP-timer as the
   clock-source!

V2 changes:
- Remove use of device-tree alias property
- Migrate OMAP timers to request timers by property instead of device ID
- Include OMAP2 support

Jon Hunter (7):
  ARM: dts: OMAP: Add timer nodes
  ARM: OMAP3: Dynamically disable secure timer nodes for secure devices
  ARM: OMAP4: Add timer clock aliases for device-tree
  ARM: OMAP: Add a timer attribute for timers that can interrupt the
    DSP
  ARM: OMAP: Add function to request a timer by capability
  ARM: OMAP3: Add generic machine descriptor for boards with OMAP3 GP
    devices
  ARM: OMAP: Add DT support for timer driver

 .../devicetree/bindings/arm/omap/timer.txt         |   30 +++++
 arch/arm/boot/dts/am33xx.dtsi                      |   61 +++++++++
 arch/arm/boot/dts/omap2.dtsi                       |   86 +++++++++++++
 arch/arm/boot/dts/omap2420.dtsi                    |    8 ++
 arch/arm/boot/dts/omap2430.dtsi                    |    8 ++
 arch/arm/boot/dts/omap3.dtsi                       |   96 ++++++++++++++
 arch/arm/boot/dts/omap4.dtsi                       |   86 +++++++++++++
 arch/arm/mach-omap1/timer.c                        |    2 +-
 arch/arm/mach-omap2/board-generic.c                |   18 +++
 arch/arm/mach-omap2/clock44xx_data.c               |   12 ++
 arch/arm/mach-omap2/common.h                       |    1 +
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |    9 ++
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |   15 ++-
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |   15 ++-
 arch/arm/mach-omap2/timer.c                        |  131 +++++++++++++++++---
 arch/arm/plat-omap/dmtimer.c                       |   94 +++++++++++++-
 arch/arm/plat-omap/include/plat/dmtimer.h          |    2 +
 17 files changed, 646 insertions(+), 28 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/omap/timer.txt

-- 
1.7.9.5

[PATCH V2 1/7] ARM: dts: OMAP: Add timer nodes

[Jon Hunter]

Add the 12 GP timers nodes present in OMAP2.
Add the 12 GP timers nodes present in OMAP3.
Add the 11 GP timers nodes present in OMAP4.
Add the 7 GP timers nodes present in AM33xx.

Add documentation for timer properties specific to OMAP.

Please note that for OMAP2/3 devices, there is only one interrupt controller
for the ARM CPU (which has the label "intc") and so globally define this as the
interrupt parent to save duplicating the interrupt parent for all device nodes.

Thanks to Vaibhav Hiremath for creating the AM33xx timer nodes. I have modified
Vaibhav's original nodes adding information on which timers support a PWM
output.

Cc: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
 .../devicetree/bindings/arm/omap/timer.txt         |   30 ++++++
 arch/arm/boot/dts/am33xx.dtsi                      |   61 +++++++++++++
 arch/arm/boot/dts/omap2.dtsi                       |   86 ++++++++++++++++++
 arch/arm/boot/dts/omap2420.dtsi                    |    8 ++
 arch/arm/boot/dts/omap2430.dtsi                    |    8 ++
 arch/arm/boot/dts/omap3.dtsi                       |   96 ++++++++++++++++++++
 arch/arm/boot/dts/omap4.dtsi                       |   86 ++++++++++++++++++
 7 files changed, 375 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/omap/timer.txt

diff --git a/Documentation/devicetree/bindings/arm/omap/timer.txt b/Documentation/devicetree/bindings/arm/omap/timer.txt
new file mode 100644
index 0000000..30b83deff
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/timer.txt
@@ -0,0 +1,30 @@
+OMAP Timer controller bindings
+
+Required properties:
+- compatible:	Must be "ti,omap2-timer" for OMAP2+ controllers
+- reg:		Contains timer register address range (base address and length)
+- interrupts: 	Contains the interrupt information for the timer. The format is
+		being dependent on which interrupt controller the OMAP device
+		uses.
+
+OMAP specific properties:
+- ti,hwmods:		Name of the hwmod associated to the timer, "timer<X>",
+			where <X> is the instance number of the timer from the
+			HW spec.
+- ti,timer-alwon:	Indicates the timer is in an alway-on power domain.
+- ti,timer-dsp:		Indicates the timer can interrupt the on-chip DSP in
+			addition to the ARM CPU.
+- ti,timer-pwm: 	Indicates the timer can generate a PWM output.
+- ti,timer-secure: 	Indicates the timer is reserved on a secure OMAP device
+			and therefore cannot be used by the kernel.
+
+Example:
+
+timer12: timer@48304000 {
+	compatible = "ti,omap2-timer";
+	reg = <0x48304000 0xfff>;
+	interrupts = <95>;
+	ti,hwmods = "timer12"
+	ti,timer-alwon;
+	ti,timer-secure;
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bb31bff..fd5074c 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -210,5 +210,66 @@
 			interrupt-parent = <&intc>;
 			interrupts = <91>;
 		};
+
+		timer1: timer@44e31000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x44e31000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <67>;
+			ti,hwmods = "timer1";
+			ti,timer-alwon;
+		};
+
+		timer2: timer@48040000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48040000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <68>;
+			ti,hwmods = "timer2";
+		};
+
+		timer3: timer@48042000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48042000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <69>;
+			ti,hwmods = "timer3";
+		};
+
+		timer4: timer@48044000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48044000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <92>;
+			ti,hwmods = "timer4";
+			ti,timer-pwm;
+		};
+
+		timer5: timer@48046000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48046000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <93>;
+			ti,hwmods = "timer5";
+			ti,timer-pwm;
+		};
+
+		timer6: timer@48048000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48048000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <94>;
+			ti,hwmods = "timer6";
+			ti,timer-pwm;
+		};
+
+		timer7: timer@4804a000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x4804a000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <95>;
+			ti,hwmods = "timer7";
+			ti,timer-pwm;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 581cb08..731de55 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -12,6 +12,7 @@
 
 / {
 	compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
+	interrupt-parent = <&intc>;
 
 	aliases {
 		serial0 = &uart1;
@@ -65,5 +66,90 @@
 			ti,hwmods = "uart3";
 			clock-frequency = <48000000>;
 		};
+
+		timer2: timer@4802a000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x4802a000 0xfff>;
+			interrupts = <38>;
+			ti,hwmods = "timer2";
+		};
+
+		timer3: timer@48078000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48078000 0xfff>;
+			interrupts = <39>;
+			ti,hwmods = "timer3";
+		};
+
+		timer4: timer@4807a000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x4807a000 0xfff>;
+			interrupts = <40>;
+			ti,hwmods = "timer4";
+		};
+
+		timer5: timer@4807c000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x4807c000 0xfff>;
+			interrupts = <41>;
+			ti,hwmods = "timer5";
+			ti,timer-dsp;
+		};
+
+		timer6: timer@4807e000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x4807e000 0xfff>;
+			interrupts = <42>;
+			ti,hwmods = "timer6";
+			ti,timer-dsp;
+		};
+
+		timer7: timer@48080000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48080000 0xfff>;
+			interrupts = <43>;
+			ti,hwmods = "timer7";
+			ti,timer-dsp;
+		};
+
+		timer8: timer@48082000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48082000 0xfff>;
+			interrupts = <44>;
+			ti,hwmods = "timer8";
+			ti,timer-dsp;
+		};
+
+		timer9: timer@48084000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48084000 0xfff>;
+			interrupts = <45>;
+			ti,hwmods = "timer9";
+			ti,timer-pwm;
+		};
+
+		timer10: timer@48086000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48086000 0xfff>;
+			interrupts = <46>;
+			ti,hwmods = "timer10";
+			ti,timer-pwm;
+		};
+
+		timer11: timer@48088000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48088000 0xfff>;
+			interrupts = <47>;
+			ti,hwmods = "timer11";
+			ti,timer-pwm;
+		};
+
+		timer12: timer@4808a000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x4808a000 0xfff>;
+			interrupts = <48>;
+			ti,hwmods = "timer12";
+			ti,timer-pwm;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index bfd76b4..5f68a70 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -44,5 +44,13 @@
 			interrupt-parent = <&intc>;
 			ti,hwmods = "mcbsp2";
 		};
+
+		timer1: timer@48028000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48028000 0xfff>;
+			interrupts = <37>;
+			ti,hwmods = "timer1";
+			ti,timer-alwon;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 4565d97..7439987 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -88,5 +88,13 @@
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp5";
 		};
+
+		timer1: timer@49018000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x49018000 0xfff>;
+			interrupts = <37>;
+			ti,hwmods = "timer1";
+			ti,timer-alwon;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index f38ea87..3fb910f 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -12,6 +12,7 @@
 
 / {
 	compatible = "ti,omap3430", "ti,omap3";
+	interrupt-parent = <&intc>;
 
 	aliases {
 		serial0 = &uart1;
@@ -300,5 +301,100 @@
 			ti,buffer-size = <128>;
 			ti,hwmods = "mcbsp5";
 		};
+
+		timer1: timer@48318000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48318000 0xfff>;
+			interrupts = <37>;
+			ti,hwmods = "timer1";
+			ti,timer-alwon;
+		};
+
+		timer2: timer@49032000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x49032000 0xfff>;
+			interrupts = <38>;
+			ti,hwmods = "timer2";
+		};
+
+		timer3: timer@49034000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x49034000 0xfff>;
+			interrupts = <39>;
+			ti,hwmods = "timer3";
+		};
+
+		timer4: timer@49036000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x49036000 0xfff>;
+			interrupts = <40>;
+			ti,hwmods = "timer4";
+		};
+
+		timer5: timer@49038000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x49038000 0xfff>;
+			interrupts = <41>;
+			ti,hwmods = "timer5";
+			ti,timer-dsp;
+		};
+
+		timer6: timer@4903a000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x4903a000 0xfff>;
+			interrupts = <42>;
+			ti,hwmods = "timer6";
+			ti,timer-dsp;
+		};
+
+		timer7: timer@4903c000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x4903c000 0xfff>;
+			interrupts = <43>;
+			ti,hwmods = "timer7";
+			ti,timer-dsp;
+		};
+
+		timer8: timer@4903e000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x4903e000 0xfff>;
+			interrupts = <44>;
+			ti,hwmods = "timer8";
+			ti,timer-pwm;
+			ti,timer-dsp;
+		};
+
+		timer9: timer@49040000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x49040000 0xfff>;
+			interrupts = <45>;
+			ti,hwmods = "timer9";
+			ti,timer-pwm;
+		};
+
+		timer10: timer@48086000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48086000 0xfff>;
+			interrupts = <46>;
+			ti,hwmods = "timer10";
+			ti,timer-pwm;
+		};
+
+		timer11: timer@48088000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48088000 0xfff>;
+			interrupts = <47>;
+			ti,hwmods = "timer11";
+			ti,timer-pwm;
+		};
+
+		timer12: timer@48304000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48304000 0xfff>;
+			interrupts = <95>;
+			ti,hwmods = "timer12";
+			ti,timer-alwon;
+			ti,timer-secure;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 5d1c484..8436c39 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -430,5 +430,91 @@
 			hw-caps-ll-interface;
 			hw-caps-temp-alert;
 		};
+
+		timer1: timer@4a318000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x4a318000 0x7f>;
+			interrupts = <0 37 0x4>;
+			ti,hwmods = "timer1";
+			ti,timer-alwon;
+		};
+
+		timer2: timer@48032000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48032000 0x7f>;
+			interrupts = <0 38 0x4>;
+			ti,hwmods = "timer2";
+		};
+
+		timer3: timer@48034000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48034000 0x7f>;
+			interrupts = <0 39 0x4>;
+			ti,hwmods = "timer3";
+		};
+
+		timer4: timer@48036000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48036000 0x7f>;
+			interrupts = <0 40 0x4>;
+			ti,hwmods = "timer4";
+		};
+
+		timer5: timer@49038000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x49038000 0x7f>;
+			interrupts = <0 41 0x4>;
+			ti,hwmods = "timer5";
+			ti,timer-dsp;
+		};
+
+		timer6: timer@4903a000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x4903a000 0x7f>;
+			interrupts = <0 42 0x4>;
+			ti,hwmods = "timer6";
+			ti,timer-dsp;
+		};
+
+		timer7: timer@4903c000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x4903c000 0x7f>;
+			interrupts = <0 43 0x4>;
+			ti,hwmods = "timer7";
+			ti,timer-dsp;
+		};
+
+		timer8: timer@4903e000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x4903e000 0x7f>;
+			interrupts = <0 44 0x4>;
+			ti,hwmods = "timer8";
+			ti,timer-pwm;
+			ti,timer-dsp;
+		};
+
+		timer9: timer@4803e000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x4803e000 0x7f>;
+			interrupts = <0 45 0x4>;
+			ti,hwmods = "timer9";
+			ti,timer-pwm;
+		};
+
+		timer10: timer@48086000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48086000 0x7f>;
+			interrupts = <0 46 0x4>;
+			ti,hwmods = "timer10";
+			ti,timer-pwm;
+		};
+
+		timer11: timer@48088000 {
+			compatible = "ti,omap2-timer";
+			reg = <0x48088000 0x7f>;
+			interrupts = <0 47 0x4>;
+			ti,hwmods = "timer11";
+			ti,timer-pwm;
+		};
 	};
 };
-- 
1.7.9.5

[PATCH V2 2/7] ARM: OMAP3: Dynamically disable secure timer nodes for secure devices

[Jon Hunter]

OMAP3 devices may or may not have security features enabled. Security enabled
devices are known as high-secure (HS) and devices without security are known as
general purpose (GP).

For OMAP3 devices there are 12 general purpose timers available. On secure
devices the 12th timer is reserved for secure usage and so cannot be used by
the kernel, where as for a GP device it is available. We can detect the OMAP
device type, secure or GP, at runtime via an on-chip register. Today, when not
using DT, we do not register the 12th timer as a linux device if the device is
secure.

When using device tree, device tree is going to register all the timer devices
it finds in the device tree blob. To prevent device tree from registering 12th
timer on a secure OMAP3 device we can add a status property to the timer
binding with the value "disabled" at boot time. Note that timer 12 on a OMAP3
device has a property "ti,timer-secure" to indicate that it will not be
available on a secure device and so for secure OMAP3 devices, we search for
timers with this property and then disable them. Using the prom_add_property()
function to dynamically add a property was a recommended approach suggested by
Rob Herring [1].

I have tested this on an OMAP3 GP device and faking it to pretend to be a
secure device to ensure that any timers marked with "ti,timer-secure" are not
registered on boot. I have also made sure that all timers are registered as
expected on a GP device by default.

[1] http://comments.gmane.org/gmane.linux.ports.arm.omap/79203

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
 arch/arm/mach-omap2/board-generic.c |    1 +
 arch/arm/mach-omap2/common.h        |    1 +
 arch/arm/mach-omap2/timer.c         |   35 +++++++++++++++++++++++++++++++++++
 3 files changed, 37 insertions(+)

diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 6f93a20..20124d7 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -40,6 +40,7 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
 static void __init omap_generic_init(void)
 {
 	omap_sdrc_init(NULL, NULL);
+	omap_dmtimer_init();
 
 	of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
 }
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 1f65b18..d6a4875 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -326,6 +326,7 @@ extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
 				      struct omap_sdrc_params *sdrc_cs1);
 struct omap2_hsmmc_info;
 extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
+extern void omap_dmtimer_init(void);
 
 #endif /* __ASSEMBLER__ */
 #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 31f9c93..60d43c8 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -136,6 +136,41 @@ static struct clock_event_device clockevent_gpt = {
 	.set_mode	= omap2_gp_timer_set_mode,
 };
 
+static struct property timer_disabled = {
+	.name = "status",
+	.length = sizeof("disabled"),
+	.value = "disabled",
+};
+
+static struct of_device_id omap_timer_match[] __initdata = {
+	{ .compatible = "ti,omap2-timer", },
+	{ }
+};
+
+/**
+ * omap_dmtimer_init - initialisation function when device tree is used
+ *
+ * For secure OMAP3 devices, timers with device type "timer-secure" cannot
+ * be used by the kernel as they are reserved. Therefore, to prevent the
+ * kernel registering these devices remove them dynamically from the device
+ * tree on boot.
+ */
+void __init omap_dmtimer_init(void)
+{
+	struct device_node *np;
+
+	if (!cpu_is_omap34xx())
+		return;
+
+	/* If we are a secure device, remove any secure timer nodes */
+	if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
+		for_each_matching_node(np, omap_timer_match) {
+			if (of_get_property(np, "ti,timer-secure", NULL))
+				prom_add_property(np, &timer_disabled);
+		}
+	}
+}
+
 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 						int gptimer_id,
 						const char *fck_source)
-- 
1.7.9.5

[PATCH V2 3/7] ARM: OMAP4: Add timer clock aliases for device-tree

[Jon Hunter]

For OMAP4, the dmtimers are located in the Wake-up, ABE and Peripheral (PER)
power domains. Hence, when the dmtimer is configured to use the "timer_sys_ck"
as its functional clock the actual clock used is different depending on whether
the clock is in the Wake-up, ABE or PER domain. So when we look-up the dmtimer's
"timer_sys_ck" we need to specify the timer device name as well as clock alias
to find the right clock.

Currently, the device names for the timers have the format "omap_timer.X" where
X is the timer instance number. When using to device tree, the format of the
device name created by device-tree is different and has the format
"<reg-address>.<device-name>" (this is assuming that the device-tree "reg"
property is specified). This causes the look-up for the OMAP4 "timer_sys_ck" to
fail. To fix this add new timer clock alias for using device-tree.

Please note that adding a 2nd set of clock aliases for the same clocks to only
temporary until device-tree migration is complete. Then we can remove the legacy
aliases. Hence, I have marked the legacy aliases with a "TODO" to remove them.

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
 arch/arm/mach-omap2/clock44xx_data.c |   12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index d7f55e4..7dfeaf0 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3314,6 +3314,7 @@ static struct omap_clk omap44xx_clks[] = {
 	CLK("usbhs_omap",	"usbtll_fck",		&dummy_ck,	CK_443X),
 	CLK("omap_wdt",	"ick",				&dummy_ck,	CK_443X),
 	CLK(NULL,	"timer_32k_ck",	&sys_32k_ck,	CK_443X),
+	/* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
 	CLK("omap_timer.1",	"timer_sys_ck",	&sys_clkin_ck,	CK_443X),
 	CLK("omap_timer.2",	"timer_sys_ck",	&sys_clkin_ck,	CK_443X),
 	CLK("omap_timer.3",	"timer_sys_ck",	&sys_clkin_ck,	CK_443X),
@@ -3325,6 +3326,17 @@ static struct omap_clk omap44xx_clks[] = {
 	CLK("omap_timer.6",	"timer_sys_ck",	&syc_clk_div_ck,	CK_443X),
 	CLK("omap_timer.7",	"timer_sys_ck",	&syc_clk_div_ck,	CK_443X),
 	CLK("omap_timer.8",	"timer_sys_ck",	&syc_clk_div_ck,	CK_443X),
+	CLK("4a318000.timer",	"timer_sys_ck",	&sys_clkin_ck,	CK_443X),
+	CLK("48032000.timer",	"timer_sys_ck",	&sys_clkin_ck,	CK_443X),
+	CLK("48034000.timer",	"timer_sys_ck",	&sys_clkin_ck,	CK_443X),
+	CLK("48036000.timer",	"timer_sys_ck",	&sys_clkin_ck,	CK_443X),
+	CLK("4803e000.timer",	"timer_sys_ck",	&sys_clkin_ck,	CK_443X),
+	CLK("48086000.timer",	"timer_sys_ck",	&sys_clkin_ck,	CK_443X),
+	CLK("48088000.timer",	"timer_sys_ck",	&sys_clkin_ck,	CK_443X),
+	CLK("49038000.timer",	"timer_sys_ck",	&syc_clk_div_ck,	CK_443X),
+	CLK("4903a000.timer",	"timer_sys_ck",	&syc_clk_div_ck,	CK_443X),
+	CLK("4903c000.timer",	"timer_sys_ck",	&syc_clk_div_ck,	CK_443X),
+	CLK("4903e000.timer",	"timer_sys_ck",	&syc_clk_div_ck,	CK_443X),
 };
 
 int __init omap4xxx_clk_init(void)
-- 
1.7.9.5

Re: [PATCH V2 3/7] ARM: OMAP4: Add timer clock aliases for device-tree

[Paul Walmsley]

On Thu, 13 Sep 2012, Jon Hunter wrote:

> For OMAP4, the dmtimers are located in the Wake-up, ABE and Peripheral (PER)
> power domains. Hence, when the dmtimer is configured to use the "timer_sys_ck"
> as its functional clock the actual clock used is different depending on whether
> the clock is in the Wake-up, ABE or PER domain. So when we look-up the dmtimer's
> "timer_sys_ck" we need to specify the timer device name as well as clock alias
> to find the right clock.
> 
> Currently, the device names for the timers have the format "omap_timer.X" where
> X is the timer instance number. When using to device tree, the format of the
> device name created by device-tree is different and has the format
> "<reg-address>.<device-name>" (this is assuming that the device-tree "reg"
> property is specified). This causes the look-up for the OMAP4 "timer_sys_ck" to
> fail. To fix this add new timer clock alias for using device-tree.
> 
> Please note that adding a 2nd set of clock aliases for the same clocks to only
> temporary until device-tree migration is complete. Then we can remove the legacy
> aliases. Hence, I have marked the legacy aliases with a "TODO" to remove them.
> 
> Signed-off-by: Jon Hunter <jon-hunter-l0cyMroinI0@public.gmane.org>

Thanks, queued for 3.7.

- Paul

[PATCH V2 4/7] ARM: OMAP: Add a timer attribute for timers that can interrupt the DSP

[Jon Hunter]

Some instances of the DMTIMER peripheral on OMAP devices have the ability
to interrupt the on-chip DSP in addition to the ARM CPU. Add a DMTIMER
attribute to indicate which timers can interrupt the DSP. By using the
omap_dm_timer_request_by_cap() API, driver will now be able to allocate
a DMTIMER that can interrupt the DSP based upon this attribute and not require
the driver to know which instance has this capability.

DMTIMERs that have the ability to interrupt the DSP on OMAP devices are as
follows ...

- OMAP1 (OMAP5912/16xx/17xx) devices	- All 8 DMTIMERs
- OMAP2/3/4 devices			- DMTIMERs 5-8

Please note that for OMAP3+, timer8 has the ability to interrupt the DSP and
generate a PWM output.

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
 arch/arm/mach-omap1/timer.c                        |    2 +-
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |    9 +++++++++
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |   15 ++++++++++++++-
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |   15 ++++++++++++++-
 arch/arm/plat-omap/include/plat/dmtimer.h          |    1 +
 5 files changed, 39 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index aa81593..cdeb9d3 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -141,7 +141,7 @@ static int __init omap1_dm_timer_init(void)
 
 		pdata->set_timer_src = omap1_dm_timer_set_src;
 		pdata->timer_capability = OMAP_TIMER_ALWON |
-				OMAP_TIMER_NEEDS_RESET;
+				OMAP_TIMER_NEEDS_RESET | OMAP_TIMER_HAS_DSP_IRQ;
 
 		ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
 		if (ret) {
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index afad69c..efd0004 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -222,6 +222,11 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 	.timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+	.timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
+};
+
 /* timer1 */
 
 struct omap_hwmod omap2xxx_timer1_hwmod = {
@@ -310,6 +315,7 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
 			.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 		},
 	},
+	.dev_attr	= &capability_dsp_dev_attr,
 	.class		= &omap2xxx_timer_hwmod_class,
 };
 
@@ -328,6 +334,7 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
 			.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 		},
 	},
+	.dev_attr	= &capability_dsp_dev_attr,
 	.class		= &omap2xxx_timer_hwmod_class,
 };
 
@@ -346,6 +353,7 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
 			.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 		},
 	},
+	.dev_attr	= &capability_dsp_dev_attr,
 	.class		= &omap2xxx_timer_hwmod_class,
 };
 
@@ -364,6 +372,7 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
 			.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 		},
 	},
+	.dev_attr	= &capability_dsp_dev_attr,
 	.class		= &omap2xxx_timer_hwmod_class,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index c9e3820..88a4cea 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -161,6 +161,16 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 	.timer_capability	= OMAP_TIMER_HAS_PWM,
 };
 
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+	.timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
+};
+
+/* pwm timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
+	.timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
+};
+
 /* timer1 */
 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 	.name		= "timer1",
@@ -244,6 +254,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
 			.idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 		},
 	},
+	.dev_attr	= &capability_dsp_dev_attr,
 	.class		= &omap3xxx_timer_hwmod_class,
 };
 
@@ -261,6 +272,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
 			.idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 		},
 	},
+	.dev_attr	= &capability_dsp_dev_attr,
 	.class		= &omap3xxx_timer_hwmod_class,
 };
 
@@ -278,6 +290,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
 			.idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 		},
 	},
+	.dev_attr	= &capability_dsp_dev_attr,
 	.class		= &omap3xxx_timer_hwmod_class,
 };
 
@@ -295,7 +308,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
 			.idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 		},
 	},
-	.dev_attr	= &capability_pwm_dev_attr,
+	.dev_attr	= &capability_dsp_pwm_dev_attr,
 	.class		= &omap3xxx_timer_hwmod_class,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 242aee4..09683bb 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2902,6 +2902,16 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 	.timer_capability	= OMAP_TIMER_HAS_PWM,
 };
 
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+	.timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
+};
+
+/* pwm timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
+	.timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
+};
+
 /* timer1 */
 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
 	{ .irq = 37 + OMAP44XX_IRQ_GIC_START },
@@ -3006,6 +3016,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
 			.modulemode   = MODULEMODE_SWCTRL,
 		},
 	},
+	.dev_attr	= &capability_dsp_dev_attr,
 };
 
 /* timer6 */
@@ -3028,6 +3039,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
 			.modulemode   = MODULEMODE_SWCTRL,
 		},
 	},
+	.dev_attr	= &capability_dsp_dev_attr,
 };
 
 /* timer7 */
@@ -3049,6 +3061,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
 			.modulemode   = MODULEMODE_SWCTRL,
 		},
 	},
+	.dev_attr	= &capability_dsp_dev_attr,
 };
 
 /* timer8 */
@@ -3070,7 +3083,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
 			.modulemode   = MODULEMODE_SWCTRL,
 		},
 	},
-	.dev_attr	= &capability_pwm_dev_attr,
+	.dev_attr	= &capability_dsp_pwm_dev_attr,
 };
 
 /* timer9 */
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 19e7fa5..85868e9 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -60,6 +60,7 @@
 #define OMAP_TIMER_ALWON				0x40000000
 #define OMAP_TIMER_HAS_PWM				0x20000000
 #define OMAP_TIMER_NEEDS_RESET				0x10000000
+#define OMAP_TIMER_HAS_DSP_IRQ				0x08000000
 
 struct omap_timer_capability_dev_attr {
 	u32 timer_capability;
-- 
1.7.9.5

Re: [PATCH V2 4/7] ARM: OMAP: Add a timer attribute for timers that can interrupt the DSP

[Paul Walmsley]

On Thu, 13 Sep 2012, Jon Hunter wrote:

> Some instances of the DMTIMER peripheral on OMAP devices have the ability
> to interrupt the on-chip DSP in addition to the ARM CPU. Add a DMTIMER
> attribute to indicate which timers can interrupt the DSP. By using the
> omap_dm_timer_request_by_cap() API, driver will now be able to allocate
> a DMTIMER that can interrupt the DSP based upon this attribute and not require
> the driver to know which instance has this capability.
> 
> DMTIMERs that have the ability to interrupt the DSP on OMAP devices are as
> follows ...
> 
> - OMAP1 (OMAP5912/16xx/17xx) devices	- All 8 DMTIMERs
> - OMAP2/3/4 devices			- DMTIMERs 5-8
> 
> Please note that for OMAP3+, timer8 has the ability to interrupt the DSP and
> generate a PWM output.
> 
> Signed-off-by: Jon Hunter <jon-hunter@ti.com>

Thanks, queued for 3.7.

- Paul

[PATCH V2 5/7] ARM: OMAP: Add function to request a timer by capability

[Jon Hunter]

Currently OMAP timers can be requested by requesting any available or by a
numerical device ID. If a specific timer is required because it has a particular
capability, such as can interrupt the on-chip DSP in addition to the ARM CPU,
then the user needs to know the device ID of the timer with this feature.
Therefore, add a new API called omap_dm_timer_request_by_cap() that allows
drivers to request a timer by capability.

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
 arch/arm/plat-omap/dmtimer.c              |   53 +++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/dmtimer.h |    1 +
 2 files changed, 54 insertions(+)

diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 938b50a..061a0b9 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -237,6 +237,59 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
 
+/**
+ * omap_dm_timer_request_by_cap - Request a timer by capability
+ *
+ * @cap:	Bit mask of capabilities to match
+ *
+ * Find a timer based upon capabilities bit mask. Callers of this function
+ * should use the definitions found in the plat/dmtimer.h file under the
+ * comment "timer capabilities used in hwmod database". Returns pointer to
+ * timer handle on success and a NULL pointer on failure.
+ */
+struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
+{
+	struct omap_dm_timer *timer = NULL, *t;
+	unsigned long flags;
+
+	if (!cap)
+		return NULL;
+
+	spin_lock_irqsave(&dm_timer_lock, flags);
+	list_for_each_entry(t, &omap_timer_list, node) {
+		if ((!t->reserved) && ((t->capability & cap) == cap)) {
+			/*
+			 * If timer is not NULL, we have already found one timer
+			 * but it was not an exact match because it had more
+			 * capabilites that what was required. Therefore,
+			 * unreserve the last timer found and see if this one
+			 * is a better match.
+			 */
+			if (timer)
+				timer->reserved = 0;
+
+			timer = t;
+			timer->reserved = 1;
+
+			/* Exit loop early if we find an exact match */
+			if (t->capability == cap)
+				break;
+		}
+	}
+	spin_unlock_irqrestore(&dm_timer_lock, flags);
+
+	if (timer && omap_dm_timer_prepare(timer)) {
+		timer->reserved = 0;
+		timer = NULL;
+	}
+
+	if (!timer)
+		pr_debug("%s: timer request failed!\n", __func__);
+
+	return timer;
+}
+EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_cap);
+
 int omap_dm_timer_free(struct omap_dm_timer *timer)
 {
 	if (unlikely(!timer))
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 85868e9..348f855 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -99,6 +99,7 @@ struct dmtimer_platform_data {
 int omap_dm_timer_reserve_systimer(int id);
 struct omap_dm_timer *omap_dm_timer_request(void);
 struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
+struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);
 int omap_dm_timer_free(struct omap_dm_timer *timer);
 void omap_dm_timer_enable(struct omap_dm_timer *timer);
 void omap_dm_timer_disable(struct omap_dm_timer *timer);
-- 
1.7.9.5

[PATCH V2 6/7] ARM: OMAP3: Add generic machine descriptor for boards with OMAP3 GP devices

[Jon Hunter]

OMAP3 devices may or may not have security features enabled. Security enabled
devices are known as high-secure (HS) and devices without security are known as
general purpose (GP).

Some OMAP3 boards, such as the OMAP3 beagle board, only use GP devices and for
GP devices there is a 12th timer available on-chip that can operate at 32kHz.
The clock for 12th timer is generated by an internal oscillator and is unique
this timer. Boards such as the beagle board use this timer as a 32kHz based
clock-events timer because early versions of the board had a hardware problem
preventing them from using other on-chip timers clocked by a external 32kHz
clock.

When booting with device-tree all OMAP3 devices use timer 1 by default for
the clock-events timer. Therefore, add a generic machine descriptor for boards
with OMAP3 GP devices so that they can use the 12th timer as the clock-events
timer instead of the default.

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
 arch/arm/mach-omap2/board-generic.c |   17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 20124d7..68a5c3b 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -100,6 +100,23 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
 	.dt_compat	= omap3_boards_compat,
 	.restart	= omap_prcm_restart,
 MACHINE_END
+
+static const char *omap3_gp_boards_compat[] __initdata = {
+	"ti,omap3-beagle",
+	NULL,
+};
+
+DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
+	.reserve	= omap_reserve,
+	.map_io		= omap3_map_io,
+	.init_early	= omap3430_init_early,
+	.init_irq	= omap_intc_of_init,
+	.handle_irq	= omap3_intc_handle_irq,
+	.init_machine	= omap_generic_init,
+	.timer		= &omap3_secure_timer,
+	.dt_compat	= omap3_gp_boards_compat,
+	.restart	= omap_prcm_restart,
+MACHINE_END
 #endif
 
 #ifdef CONFIG_SOC_AM33XX
-- 
1.7.9.5

[PATCH V2 7/7] ARM: OMAP: Add DT support for timer driver

[Jon Hunter]

In order to add device-tree support to the timer driver the following changes
were made ...

1. Allocate system timers (used for clock-events and clock-source) based upon
   timer properties rather than using an hard-coded timer instance ID. To allow
   this a new helper function called omap_dmtimer_find_by_property() has been
   added for finding a timer with the particular properties in the device-tree
   blob. Please note that this is an internal helper function for system timers
   only to find a timer in the device-tree blob. This cannot be used by device
   drivers, another API has been added for that (see below). Timers that are
   allocated for system timers are dynamically disabled at boot time by adding
   a status property with the value "disabled" to the timer's device-tree node.

   Please note that when allocating system timers we now pass a timer ID and
   timer property. The timer ID is only be used for allocating a timer when
   booting without device-tree. Once device-tree migration is complete, all
   the timer ID references will be removed.

2. If DT blob is present, then let device-tree create the timer devices
   dynamically.

3. When device-tree is present the "id" field in the platform_device structure
   (pdev->id) is initialised to -1 and hence cannot be used to identify a timer
   instance. Due to this the following changes were made ...
   a). The API omap_dm_timer_request_specific() is not supported when using
       device-tree, because it uses the device ID to request a specific timer.
       This function will return an error if called when device-tree is present.
       Users of this API should use omap_dm_timer_request_by_cap() instead.
   b). When removing the DMTIMER driver, the timer "id" was used to identify the
       timer instance. The remove function has been modified to use the device
       name instead of the "id".

4. When device-tree is present the platform_data structure will be NULL and so
   check for this.

5. The OMAP timer device tree binding has the following optional parameters ...
   a). ti,timer-alwon  --> Timer is in an always-on power domain
   b). ti,timer-dsp    --> Timer can generate an interrupt to the on-chip DSP
   c). ti,timer-pwm    --> Timer can generate a PWM output
   d). ti,timer-secure --> Timer is reserved on a secure OMAP device
   Search for the above parameters and set the appropriate timer attribute
   flags.

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
 arch/arm/mach-omap2/timer.c  |   96 +++++++++++++++++++++++++++++++++---------
 arch/arm/plat-omap/dmtimer.c |   41 +++++++++++++++---
 2 files changed, 112 insertions(+), 25 deletions(-)

diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 60d43c8..d1c7771 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -58,16 +58,20 @@
 #define OMAP3_32K_SOURCE	"omap_32k_fck"
 #define OMAP4_32K_SOURCE	"sys_32k_ck"
 
+#define TIMER_PROP_ALWON	"ti,timer-alwon"
+
 #ifdef CONFIG_OMAP_32K_TIMER
 #define OMAP2_CLKEV_SOURCE	OMAP2_32K_SOURCE
 #define OMAP3_CLKEV_SOURCE	OMAP3_32K_SOURCE
 #define OMAP4_CLKEV_SOURCE	OMAP4_32K_SOURCE
 #define OMAP3_SECURE_TIMER	12
+#define TIMER_PROP_SECURE	"ti,timer-secure"
 #else
 #define OMAP2_CLKEV_SOURCE	OMAP2_MPU_SOURCE
 #define OMAP3_CLKEV_SOURCE	OMAP3_MPU_SOURCE
 #define OMAP4_CLKEV_SOURCE	OMAP4_MPU_SOURCE
 #define OMAP3_SECURE_TIMER	1
+#define TIMER_PROP_SECURE	TIMER_PROP_ALWON
 #endif
 
 /* Clockevent code */
@@ -171,20 +175,63 @@ void __init omap_dmtimer_init(void)
 	}
 }
 
+/**
+ * omap_dmtimer_find_by_property - find timer in device-tree by property
+ *
+ * Helper function for finding a timer to be used as kernel system timer
+ * using device-tree. Optionally, the property argument can be used to
+ * select a timer with a specific property. Once a timer is found then
+ * mark the timer node in device-tree as disabled to prevent the kernel
+ * from registering this timer and so no other device can use it.
+ */
+static const char * __init omap_dmtimer_find_by_property(const char *property)
+{
+	struct device_node *np;
+	const char *oh_name;
+
+	for_each_matching_node(np, omap_timer_match) {
+		if (!of_device_is_available(np))
+			continue;
+
+		if (property && !of_get_property(np, property, NULL))
+			continue;
+
+		of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
+		if (oh_name) {
+			prom_add_property(np, &timer_disabled);
+			return oh_name;
+		}
+	}
+
+	return NULL;
+}
+
 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 						int gptimer_id,
-						const char *fck_source)
+						const char *fck_source,
+						const char *property)
 {
 	char name[10]; /* 10 = sizeof("gptXX_Xck0") */
+	const char *oh_name;
 	struct omap_hwmod *oh;
 	struct resource irq_rsrc, mem_rsrc;
 	size_t size;
 	int res = 0;
 	int r;
 
-	sprintf(name, "timer%d", gptimer_id);
-	omap_hwmod_setup_one(name);
-	oh = omap_hwmod_lookup(name);
+	oh_name = name;
+
+	if (of_have_populated_dt())
+		oh_name = omap_dmtimer_find_by_property(property);
+	else
+		sprintf(name, "timer%d", gptimer_id);
+
+	if (!oh_name)
+		return -ENODEV;
+
+	omap_hwmod_setup_one(oh_name);
+	oh = omap_hwmod_lookup(oh_name);
+
 	if (!oh)
 		return -ENODEV;
 
@@ -211,9 +258,11 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 
 	omap_hwmod_enable(oh);
 
-	if (omap_dm_timer_reserve_systimer(gptimer_id))
-		return -ENODEV;
+	if (!of_have_populated_dt())
+		if (omap_dm_timer_reserve_systimer(gptimer_id))
+			return -ENODEV;
 
+	/* FIXME: Need to remove hard-coded test on timer ID */
 	if (gptimer_id != 12) {
 		struct clk *src;
 
@@ -223,8 +272,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 		} else {
 			res = __omap_dm_timer_set_source(timer->fclk, src);
 			if (IS_ERR_VALUE(res))
-				pr_warning("%s: timer%i cannot set source\n",
-						__func__, gptimer_id);
+				pr_warn("%s: %s cannot set source\n",
+					__func__, oh->name);
 			clk_put(src);
 		}
 	}
@@ -240,11 +289,12 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 }
 
 static void __init omap2_gp_clockevent_init(int gptimer_id,
-						const char *fck_source)
+						const char *fck_source,
+						const char *property)
 {
 	int res;
 
-	res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
+	res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property);
 	BUG_ON(res);
 
 	omap2_gp_timer_irq.dev_id = (void *)&clkev;
@@ -341,7 +391,7 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
 {
 	int res;
 
-	res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
+	res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL);
 	BUG_ON(res);
 
 	__omap_dm_timer_load_start(&clksrc,
@@ -375,11 +425,11 @@ static void __init omap2_clocksource_init(int gptimer_id,
 		omap2_gptimer_clocksource_init(gptimer_id, fck_source);
 }
 
-#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,			\
+#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,	\
 				clksrc_nr, clksrc_src)			\
 static void __init omap##name##_timer_init(void)			\
 {									\
-	omap2_gp_clockevent_init((clkev_nr), clkev_src);		\
+	omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);	\
 	omap2_clocksource_init((clksrc_nr), clksrc_src);		\
 }
 
@@ -389,20 +439,23 @@ struct sys_timer omap##name##_timer = {					\
 };
 
 #ifdef CONFIG_ARCH_OMAP2
-OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
+OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, TIMER_PROP_ALWON,
+		    2, OMAP2_MPU_SOURCE)
 OMAP_SYS_TIMER(2)
 #endif
 
 #ifdef CONFIG_ARCH_OMAP3
-OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
+OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, TIMER_PROP_ALWON,
+		    2, OMAP3_MPU_SOURCE)
 OMAP_SYS_TIMER(3)
 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
-			2, OMAP3_MPU_SOURCE)
+			TIMER_PROP_SECURE, 2, OMAP3_MPU_SOURCE)
 OMAP_SYS_TIMER(3_secure)
 #endif
 
 #ifdef CONFIG_SOC_AM33XX
-OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
+OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, TIMER_PROP_ALWON,
+		    2, OMAP4_MPU_SOURCE)
 OMAP_SYS_TIMER(3_am33xx)
 #endif
 
@@ -415,7 +468,7 @@ static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
 
 static void __init omap4_timer_init(void)
 {
-	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
+	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, TIMER_PROP_ALWON);
 	omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
 #ifdef CONFIG_LOCAL_TIMERS
 	/* Local timers are not supprted on OMAP4430 ES1.0 */
@@ -437,7 +490,8 @@ OMAP_SYS_TIMER(4)
 #endif
 
 #ifdef CONFIG_SOC_OMAP5
-OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE)
+OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, TIMER_PROP_ALWON,
+		    2, OMAP4_MPU_SOURCE)
 OMAP_SYS_TIMER(5)
 #endif
 
@@ -515,6 +569,10 @@ static int __init omap2_dm_timer_init(void)
 {
 	int ret;
 
+	/* If dtb is there, the devices will be created dynamically */
+	if (of_have_populated_dt())
+		return -ENODEV;
+
 	ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
 	if (unlikely(ret)) {
 		pr_err("%s: device registration failed.\n", __func__);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 061a0b9..9a4482f 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -40,6 +40,8 @@
 #include <linux/device.h>
 #include <linux/err.h>
 #include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 
 #include <plat/dmtimer.h>
 #include <plat/omap-pm.h>
@@ -212,6 +214,13 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 	unsigned long flags;
 	int ret = 0;
 
+	/* Requesting timer by ID is not supported when device tree is used */
+	if (of_have_populated_dt()) {
+		pr_warn("%s: Please use omap_dm_timer_request_by_cap()\n",
+			__func__);
+		return NULL;
+	}
+
 	spin_lock_irqsave(&dm_timer_lock, flags);
 	list_for_each_entry(t, &omap_timer_list, node) {
 		if (t->pdev->id == id && !t->reserved) {
@@ -467,7 +476,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 	 * use the clock framework to set the parent clock. To be removed
 	 * once OMAP1 migrated to using clock framework for dmtimers
 	 */
-	if (pdata->set_timer_src)
+	if (pdata && pdata->set_timer_src)
 		return pdata->set_timer_src(timer->pdev, source);
 
 	fclk = clk_get(&timer->pdev->dev, "fck");
@@ -748,7 +757,7 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
 
-	if (!pdata) {
+	if (!pdata && !dev->of_node) {
 		dev_err(dev, "%s: no platform data.\n", __func__);
 		return -ENODEV;
 	}
@@ -777,11 +786,23 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
 		return -ENOMEM;
 	}
 
-	timer->id = pdev->id;
+	if (dev->of_node) {
+		if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
+			timer->capability |= OMAP_TIMER_ALWON;
+		if (of_find_property(dev->of_node, "ti,timer-dsp", NULL))
+			timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
+		if (of_find_property(dev->of_node, "ti,timer-pwm", NULL))
+			timer->capability |= OMAP_TIMER_HAS_PWM;
+		if (of_find_property(dev->of_node, "ti,timer-secure", NULL))
+			timer->capability |= OMAP_TIMER_SECURE;
+	} else {
+		timer->id = pdev->id;
+		timer->capability = pdata->timer_capability;
+		timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
+	}
+
 	timer->irq = irq->start;
-	timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
 	timer->pdev = pdev;
-	timer->capability = pdata->timer_capability;
 
 	/* Skip pm_runtime_enable for OMAP1 */
 	if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
@@ -821,7 +842,8 @@ static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
 
 	spin_lock_irqsave(&dm_timer_lock, flags);
 	list_for_each_entry(timer, &omap_timer_list, node)
-		if (timer->pdev->id == pdev->id) {
+		if (!strcmp(dev_name(&timer->pdev->dev),
+			    dev_name(&pdev->dev))) {
 			list_del(&timer->node);
 			ret = 0;
 			break;
@@ -831,11 +853,18 @@ static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
 	return ret;
 }
 
+static const struct of_device_id omap_timer_match[] = {
+	{ .compatible = "ti,omap2-timer", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, omap_timer_match);
+
 static struct platform_driver omap_dm_timer_driver = {
 	.probe  = omap_dm_timer_probe,
 	.remove = __devexit_p(omap_dm_timer_remove),
 	.driver = {
 		.name   = "omap_timer",
+		.of_match_table = of_match_ptr(omap_timer_match),
 	},
 };
 
-- 
1.7.9.5

Re: [PATCH V2 7/7] ARM: OMAP: Add DT support for timer driver

[Rob Herring]

On 09/13/2012 06:31 PM, Jon Hunter wrote:
> In order to add device-tree support to the timer driver the following changes
> were made ...
> 
> 1. Allocate system timers (used for clock-events and clock-source) based upon
>    timer properties rather than using an hard-coded timer instance ID. To allow
>    this a new helper function called omap_dmtimer_find_by_property() has been
>    added for finding a timer with the particular properties in the device-tree
>    blob. Please note that this is an internal helper function for system timers
>    only to find a timer in the device-tree blob. This cannot be used by device
>    drivers, another API has been added for that (see below). Timers that are
>    allocated for system timers are dynamically disabled at boot time by adding
>    a status property with the value "disabled" to the timer's device-tree node.
> 
>    Please note that when allocating system timers we now pass a timer ID and
>    timer property. The timer ID is only be used for allocating a timer when
>    booting without device-tree. Once device-tree migration is complete, all
>    the timer ID references will be removed.
> 
> 2. If DT blob is present, then let device-tree create the timer devices
>    dynamically.
> 
> 3. When device-tree is present the "id" field in the platform_device structure
>    (pdev->id) is initialised to -1 and hence cannot be used to identify a timer
>    instance. Due to this the following changes were made ...
>    a). The API omap_dm_timer_request_specific() is not supported when using
>        device-tree, because it uses the device ID to request a specific timer.
>        This function will return an error if called when device-tree is present.
>        Users of this API should use omap_dm_timer_request_by_cap() instead.
>    b). When removing the DMTIMER driver, the timer "id" was used to identify the
>        timer instance. The remove function has been modified to use the device
>        name instead of the "id".
> 
> 4. When device-tree is present the platform_data structure will be NULL and so
>    check for this.
> 
> 5. The OMAP timer device tree binding has the following optional parameters ...
>    a). ti,timer-alwon  --> Timer is in an always-on power domain
>    b). ti,timer-dsp    --> Timer can generate an interrupt to the on-chip DSP
>    c). ti,timer-pwm    --> Timer can generate a PWM output
>    d). ti,timer-secure --> Timer is reserved on a secure OMAP device
>    Search for the above parameters and set the appropriate timer attribute
>    flags.
> 
> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
> ---

Looks pretty good from a DT perspective. I won't try to understand the
omap timer code. One comment though.

>  arch/arm/mach-omap2/timer.c  |   96 +++++++++++++++++++++++++++++++++---------
>  arch/arm/plat-omap/dmtimer.c |   41 +++++++++++++++---
>  2 files changed, 112 insertions(+), 25 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> index 60d43c8..d1c7771 100644
> --- a/arch/arm/mach-omap2/timer.c
> +++ b/arch/arm/mach-omap2/timer.c
> @@ -58,16 +58,20 @@
>  #define OMAP3_32K_SOURCE	"omap_32k_fck"
>  #define OMAP4_32K_SOURCE	"sys_32k_ck"
>  
> +#define TIMER_PROP_ALWON	"ti,timer-alwon"
> +

It would be easier to follow the code if you use the strings directly
(and you do in some places).

>  #ifdef CONFIG_OMAP_32K_TIMER
>  #define OMAP2_CLKEV_SOURCE	OMAP2_32K_SOURCE
>  #define OMAP3_CLKEV_SOURCE	OMAP3_32K_SOURCE
>  #define OMAP4_CLKEV_SOURCE	OMAP4_32K_SOURCE
>  #define OMAP3_SECURE_TIMER	12
> +#define TIMER_PROP_SECURE	"ti,timer-secure"
>  #else
>  #define OMAP2_CLKEV_SOURCE	OMAP2_MPU_SOURCE
>  #define OMAP3_CLKEV_SOURCE	OMAP3_MPU_SOURCE
>  #define OMAP4_CLKEV_SOURCE	OMAP4_MPU_SOURCE
>  #define OMAP3_SECURE_TIMER	1
> +#define TIMER_PROP_SECURE	TIMER_PROP_ALWON
>  #endif
>  

Re: [PATCH V2 7/7] ARM: OMAP: Add DT support for timer driver

[Jon Hunter]

Hi Rob,

On 09/13/2012 06:31 PM, Jon Hunter wrote:
> In order to add device-tree support to the timer driver the following changes
> were made ...
> 
> 1. Allocate system timers (used for clock-events and clock-source) based upon
>    timer properties rather than using an hard-coded timer instance ID. To allow
>    this a new helper function called omap_dmtimer_find_by_property() has been
>    added for finding a timer with the particular properties in the device-tree
>    blob. Please note that this is an internal helper function for system timers
>    only to find a timer in the device-tree blob. This cannot be used by device
>    drivers, another API has been added for that (see below). Timers that are
>    allocated for system timers are dynamically disabled at boot time by adding
>    a status property with the value "disabled" to the timer's device-tree node.
> 
>    Please note that when allocating system timers we now pass a timer ID and
>    timer property. The timer ID is only be used for allocating a timer when
>    booting without device-tree. Once device-tree migration is complete, all
>    the timer ID references will be removed.
> 
> 2. If DT blob is present, then let device-tree create the timer devices
>    dynamically.
> 
> 3. When device-tree is present the "id" field in the platform_device structure
>    (pdev->id) is initialised to -1 and hence cannot be used to identify a timer
>    instance. Due to this the following changes were made ...
>    a). The API omap_dm_timer_request_specific() is not supported when using
>        device-tree, because it uses the device ID to request a specific timer.
>        This function will return an error if called when device-tree is present.
>        Users of this API should use omap_dm_timer_request_by_cap() instead.
>    b). When removing the DMTIMER driver, the timer "id" was used to identify the
>        timer instance. The remove function has been modified to use the device
>        name instead of the "id".
> 
> 4. When device-tree is present the platform_data structure will be NULL and so
>    check for this.
> 
> 5. The OMAP timer device tree binding has the following optional parameters ...
>    a). ti,timer-alwon  --> Timer is in an always-on power domain
>    b). ti,timer-dsp    --> Timer can generate an interrupt to the on-chip DSP
>    c). ti,timer-pwm    --> Timer can generate a PWM output
>    d). ti,timer-secure --> Timer is reserved on a secure OMAP device
>    Search for the above parameters and set the appropriate timer attribute
>    flags.
> 
> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
> ---
>  arch/arm/mach-omap2/timer.c  |   96 +++++++++++++++++++++++++++++++++---------
>  arch/arm/plat-omap/dmtimer.c |   41 +++++++++++++++---
>  2 files changed, 112 insertions(+), 25 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> index 60d43c8..d1c7771 100644
> --- a/arch/arm/mach-omap2/timer.c
> +++ b/arch/arm/mach-omap2/timer.c
> @@ -58,16 +58,20 @@
>  #define OMAP3_32K_SOURCE	"omap_32k_fck"
>  #define OMAP4_32K_SOURCE	"sys_32k_ck"
>  
> +#define TIMER_PROP_ALWON	"ti,timer-alwon"
> +

I see you made the following comment [1] here ...

"It would be easier to follow the code if you use the strings directly
(and you do in some places)."

I could avoid the above definition.

>  #ifdef CONFIG_OMAP_32K_TIMER
>  #define OMAP2_CLKEV_SOURCE	OMAP2_32K_SOURCE
>  #define OMAP3_CLKEV_SOURCE	OMAP3_32K_SOURCE
>  #define OMAP4_CLKEV_SOURCE	OMAP4_32K_SOURCE
>  #define OMAP3_SECURE_TIMER	12
> +#define TIMER_PROP_SECURE	"ti,timer-secure"
>  #else
>  #define OMAP2_CLKEV_SOURCE	OMAP2_MPU_SOURCE
>  #define OMAP3_CLKEV_SOURCE	OMAP3_MPU_SOURCE
>  #define OMAP4_CLKEV_SOURCE	OMAP4_MPU_SOURCE
>  #define OMAP3_SECURE_TIMER	1
> +#define TIMER_PROP_SECURE	TIMER_PROP_ALWON
>  #endif

Are you ok, with having the TIMER_PROP_SECURE definition or would you
prefer I handle this differently? This is dependent on the kernel config.

Cheers
Jon

[1] http://thread.gmane.org/gmane.linux.ports.arm.omap/84458/focus=84982

Re: [PATCH V2 7/7] ARM: OMAP: Add DT support for timer driver

[Rob Herring]

On 09/26/2012 10:51 AM, Jon Hunter wrote:
> Hi Rob,



>>  #define OMAP3_32K_SOURCE	"omap_32k_fck"
>>  #define OMAP4_32K_SOURCE	"sys_32k_ck"
>>  
>> +#define TIMER_PROP_ALWON	"ti,timer-alwon"
>> +
> 
> I see you made the following comment [1] here ...
> 
> "It would be easier to follow the code if you use the strings directly
> (and you do in some places)."
> 
> I could avoid the above definition.
> 
>>  #ifdef CONFIG_OMAP_32K_TIMER
>>  #define OMAP2_CLKEV_SOURCE	OMAP2_32K_SOURCE
>>  #define OMAP3_CLKEV_SOURCE	OMAP3_32K_SOURCE
>>  #define OMAP4_CLKEV_SOURCE	OMAP4_32K_SOURCE
>>  #define OMAP3_SECURE_TIMER	12
>> +#define TIMER_PROP_SECURE	"ti,timer-secure"
>>  #else
>>  #define OMAP2_CLKEV_SOURCE	OMAP2_MPU_SOURCE
>>  #define OMAP3_CLKEV_SOURCE	OMAP3_MPU_SOURCE
>>  #define OMAP4_CLKEV_SOURCE	OMAP4_MPU_SOURCE
>>  #define OMAP3_SECURE_TIMER	1
>> +#define TIMER_PROP_SECURE	TIMER_PROP_ALWON
>>  #endif
> 
> Are you ok, with having the TIMER_PROP_SECURE definition or would you
> prefer I handle this differently? This is dependent on the kernel config.\

Yes, that's fine.

Rob

> 
> Cheers
> Jon
> 
> [1] http://thread.gmane.org/gmane.linux.ports.arm.omap/84458/focus=84982
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

Re: [PATCH V2 0/7] ARM: OMAP2+: Add device-tree support for timers

[Jon Hunter]

On 09/13/2012 06:31 PM, Jon Hunter wrote:
> This series adds device-tree support for the timers on OMAP2+ devices
> including AM33xx.

One more comment. This has been tested on v3.6-rc5 and rebased on top of
Tony's devel-dt branch.

Cheers
Jon

Re: [PATCH V2 0/7] ARM: OMAP2+: Add device-tree support for timers

[Benoit Cousson]

Hi Tony,

I was about to take the DTS patch, but was wondering if you will pull
the driver changes for 3.7.

Thanks,
Benoit

On 09/14/2012 01:31 AM, Jon Hunter wrote:
> This series adds device-tree support for the timers on OMAP2+ devices
> including AM33xx.
> 
> Testing:
> 1. I have booted linux with this series on OMAP2420 H4, OMAP3430 Beagle and
>    OMAP4430 Panda with/without device-tree present.
> 2. Vaibhav has booted linux on AM335x Beagle bone (thanks!)
> 3. I have tested the all the timers (not used by the kernel as sys-timers) on
>    OMAP2420 H4, OMAP3430 Beagle and OMAP4430 Panda with/without device-tree with
>    this series. The testing includes ...
>    a. Configuring, starting a timer and checking the counter value is
>       incrementing.
>    b. Testing timer overflow interrupt when timer expires.
>    c. Using different clock sources to operate the timer with.
> 4. Verified on OMAP4430 and AM33xx (Vaibhav) that the kernel boots when using a
>    GP timer as clock-source (default for OMAP is 32k-sync timer). Thanks to
>    Vaibhav for catching and tracking down a bug when using a GP-timer as the
>    clock-source!
> 
> V2 changes:
> - Remove use of device-tree alias property
> - Migrate OMAP timers to request timers by property instead of device ID
> - Include OMAP2 support
> 
> Jon Hunter (7):
>   ARM: dts: OMAP: Add timer nodes
>   ARM: OMAP3: Dynamically disable secure timer nodes for secure devices
>   ARM: OMAP4: Add timer clock aliases for device-tree
>   ARM: OMAP: Add a timer attribute for timers that can interrupt the
>     DSP
>   ARM: OMAP: Add function to request a timer by capability
>   ARM: OMAP3: Add generic machine descriptor for boards with OMAP3 GP
>     devices
>   ARM: OMAP: Add DT support for timer driver
> 
>  .../devicetree/bindings/arm/omap/timer.txt         |   30 +++++
>  arch/arm/boot/dts/am33xx.dtsi                      |   61 +++++++++
>  arch/arm/boot/dts/omap2.dtsi                       |   86 +++++++++++++
>  arch/arm/boot/dts/omap2420.dtsi                    |    8 ++
>  arch/arm/boot/dts/omap2430.dtsi                    |    8 ++
>  arch/arm/boot/dts/omap3.dtsi                       |   96 ++++++++++++++
>  arch/arm/boot/dts/omap4.dtsi                       |   86 +++++++++++++
>  arch/arm/mach-omap1/timer.c                        |    2 +-
>  arch/arm/mach-omap2/board-generic.c                |   18 +++
>  arch/arm/mach-omap2/clock44xx_data.c               |   12 ++
>  arch/arm/mach-omap2/common.h                       |    1 +
>  arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |    9 ++
>  arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |   15 ++-
>  arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |   15 ++-
>  arch/arm/mach-omap2/timer.c                        |  131 +++++++++++++++++---
>  arch/arm/plat-omap/dmtimer.c                       |   94 +++++++++++++-
>  arch/arm/plat-omap/include/plat/dmtimer.h          |    2 +
>  17 files changed, 646 insertions(+), 28 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/omap/timer.txt
> 

Re: [PATCH V2 0/7] ARM: OMAP2+: Add device-tree support for timers

[Tony Lindgren]

* Benoit Cousson <b-cousson@ti.com> [120919 19:24]:
> Hi Tony,
> 
> I was about to take the DTS patch, but was wondering if you will pull
> the driver changes for 3.7.

I suggest that you do a separate branch on top of Paul's hwmod series
when he posts those if that works for you?

Regards,

Tony

Re: [PATCH V2 0/7] ARM: OMAP2+: Add device-tree support for timers

[Jon Hunter]

On 09/20/2012 06:53 PM, Tony Lindgren wrote:
> * Benoit Cousson <b-cousson@ti.com> [120919 19:24]:
>> Hi Tony,
>>
>> I was about to take the DTS patch, but was wondering if you will pull
>> the driver changes for 3.7.
> 
> I suggest that you do a separate branch on top of Paul's hwmod series
> when he posts those if that works for you?

Benoit, I see that you have pulled in the DTS patch.

Do you guys want me to rebase the remaining patches with Rob's change on
Tony's master branch and re-submit?

Cheers
Jon

Re: [PATCH V2 0/7] ARM: OMAP2+: Add device-tree support for timers

[Vaibhav Hiremath]

On 9/26/2012 10:23 PM, Jon Hunter wrote:
> 
> On 09/20/2012 06:53 PM, Tony Lindgren wrote:
>> * Benoit Cousson <b-cousson@ti.com> [120919 19:24]:
>>> Hi Tony,
>>>
>>> I was about to take the DTS patch, but was wondering if you will pull
>>> the driver changes for 3.7.
>>
>> I suggest that you do a separate branch on top of Paul's hwmod series
>> when he posts those if that works for you?
> 
> Benoit, I see that you have pulled in the DTS patch.
> 
> Do you guys want me to rebase the remaining patches with Rob's change on
> Tony's master branch and re-submit?
> 

Jon,

Sorry for delayed response, But I tried using your omap_test application
to validate this patch series, but it is failing for me.

How did you test it? Are you running same test application at your end?

I am debugging this issue, i just thought I should tell you this before
its too late.


Below is the log -

[root@arago /]# echo 3 > /tmp/omap-test/timer/one
[   79.612223] omap_dm_timer_request_specific: Please use
omap_dm_timer_request_by_cap()
[   79.620636] Timer 3 not available!

[root@arago /]#
[root@arago /]# echo 3 > /tmp/omap-test/timer/all
[  135.111949] Testing 48042000.timer with 24000000 Hz clock ...
[root@arago /]# [  137.457389] Timer read test PASSED! No errors, 100 loops
[  137.463267] Timer interrupt test PASSED!
[  137.467650] Testing 48042000.timer with 32768 Hz clock ...
[  139.816892] Timer read test PASSED! No errors, 100 loops
[  139.830776] Timer interrupt test PASSED!
[  139.835245] Testing 48044000.timer with 24000000 Hz clock ...
[  142.183912] Timer read test PASSED! No errors, 100 loops
[  142.189734] Timer interrupt test PASSED!
[  142.194076] Testing 48044000.timer with 32768 Hz clock ...
[  144.543451] Timer read test PASSED! No errors, 100 loops
[  144.557334] Timer interrupt test PASSED!
[  144.561806] Testing 48046000.timer with 24000000 Hz clock ...
[  146.910469] Timer read test PASSED! No errors, 100 loops
[  147.910493] Timer interrupt test FAILED! No interrupt occurred in 1 sec
[  147.917598] Testing 48046000.timer with 32768 Hz clock ...
[  150.262203] Timer read test PASSED! No errors, 100 loops
[  151.262049] Timer interrupt test FAILED! No interrupt occurred in 1 sec
[  151.269298] Testing 48048000.timer with 24000000 Hz clock ...
[  153.613596] Timer read test PASSED! No errors, 100 loops
[  154.613618] Timer interrupt test FAILED! No interrupt occurred in 1 sec
[  154.620725] Testing 48048000.timer with 32768 Hz clock ...
[  156.965324] Timer read test PASSED! No errors, 100 loops
[  157.965176] Timer interrupt test FAILED! No interrupt occurred in 1 sec
[  157.972419] Testing 4804a000.timer with 24000000 Hz clock ...

[root@arago /]# [  160.316753] Timer read test PASSED! No errors, 100 loops

[root@arago /]# [  161.316728] Timer interrupt test FAILED! No interrupt
occurred in 1 sec
[  161.323912] Testing 4804a000.timer with 32768 Hz clock ...

[root@arago /]# [  163.668490] Timer read test PASSED! No errors, 100 loops
[  164.668328] Timer interrupt test FAILED! No interrupt occurred in 1 sec
[  164.675545] Tested 5 timers, skipped 6 timers and detected 6 errors
[  164.682202] Test iteration 0 complete in 29 secs
[  164.687104] Test summary: Iterations 1, Errors 6



> Cheers
> Jon
> 
> 
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
> 

Re: [PATCH V2 0/7] ARM: OMAP2+: Add device-tree support for timers

[Jon Hunter]

On 09/28/2012 01:51 PM, Vaibhav Hiremath wrote:
> 
> 
> On 9/26/2012 10:23 PM, Jon Hunter wrote:
>>
>> On 09/20/2012 06:53 PM, Tony Lindgren wrote:
>>> * Benoit Cousson <b-cousson@ti.com> [120919 19:24]:
>>>> Hi Tony,
>>>>
>>>> I was about to take the DTS patch, but was wondering if you will pull
>>>> the driver changes for 3.7.
>>>
>>> I suggest that you do a separate branch on top of Paul's hwmod series
>>> when he posts those if that works for you?
>>
>> Benoit, I see that you have pulled in the DTS patch.
>>
>> Do you guys want me to rebase the remaining patches with Rob's change on
>> Tony's master branch and re-submit?
>>
> 
> Jon,
> 
> Sorry for delayed response, But I tried using your omap_test application
> to validate this patch series, but it is failing for me.
> 
> How did you test it? Are you running same test application at your end?

Check your email on Sept 14th. I sent you the latest version of the test
code. I will resend in case it got lost in deep space.

> I am debugging this issue, i just thought I should tell you this before
> its too late.
> 
> 
> Below is the log -
> 
> [root@arago /]# echo 3 > /tmp/omap-test/timer/one
> [   79.612223] omap_dm_timer_request_specific: Please use
> omap_dm_timer_request_by_cap()
> [   79.620636] Timer 3 not available!

Yes that's expected as omap_dm_timer_request_specific is not supported
with DT. Don't spend anytime debugging you just need the latest test.

Cheers
Jon

Re: [PATCH V2 0/7] ARM: OMAP2+: Add device-tree support for timers

[Jon Hunter]

On 09/28/2012 01:51 PM, Vaibhav Hiremath wrote:
> 
> 
> On 9/26/2012 10:23 PM, Jon Hunter wrote:
>>
>> On 09/20/2012 06:53 PM, Tony Lindgren wrote:
>>> * Benoit Cousson <b-cousson-l0cyMroinI0@public.gmane.org> [120919 19:24]:
>>>> Hi Tony,
>>>>
>>>> I was about to take the DTS patch, but was wondering if you will pull
>>>> the driver changes for 3.7.
>>>
>>> I suggest that you do a separate branch on top of Paul's hwmod series
>>> when he posts those if that works for you?
>>
>> Benoit, I see that you have pulled in the DTS patch.
>>
>> Do you guys want me to rebase the remaining patches with Rob's change on
>> Tony's master branch and re-submit?
>>
> 
> Jon,
> 
> Sorry for delayed response, But I tried using your omap_test application
> to validate this patch series, but it is failing for me.
> 
> How did you test it? Are you running same test application at your end?

Sorry, I now see you are using the latest test code! I was too hasty
when I saw the first error ;-)

> I am debugging this issue, i just thought I should tell you this before
> its too late.

Thanks.

> Below is the log -
> 
> [root@arago /]# echo 3 > /tmp/omap-test/timer/one
> [   79.612223] omap_dm_timer_request_specific: Please use
> omap_dm_timer_request_by_cap()
> [   79.620636] Timer 3 not available!

This is expected because omap_dm_timer_request_specific() is no longer
supported. I should remove in the omap-test/timer/one going forward.

> [root@arago /]#
> [root@arago /]# echo 3 > /tmp/omap-test/timer/all
> [  135.111949] Testing 48042000.timer with 24000000 Hz clock ...
> [root@arago /]# [  137.457389] Timer read test PASSED! No errors, 100 loops
> [  137.463267] Timer interrupt test PASSED!
> [  137.467650] Testing 48042000.timer with 32768 Hz clock ...
> [  139.816892] Timer read test PASSED! No errors, 100 loops
> [  139.830776] Timer interrupt test PASSED!
> [  139.835245] Testing 48044000.timer with 24000000 Hz clock ...
> [  142.183912] Timer read test PASSED! No errors, 100 loops
> [  142.189734] Timer interrupt test PASSED!
> [  142.194076] Testing 48044000.timer with 32768 Hz clock ...
> [  144.543451] Timer read test PASSED! No errors, 100 loops
> [  144.557334] Timer interrupt test PASSED!
> [  144.561806] Testing 48046000.timer with 24000000 Hz clock ...
> [  146.910469] Timer read test PASSED! No errors, 100 loops
> [  147.910493] Timer interrupt test FAILED! No interrupt occurred in 1 sec
> [  147.917598] Testing 48046000.timer with 32768 Hz clock ...
> [  150.262203] Timer read test PASSED! No errors, 100 loops
> [  151.262049] Timer interrupt test FAILED! No interrupt occurred in 1 sec
> [  151.269298] Testing 48048000.timer with 24000000 Hz clock ...
> [  153.613596] Timer read test PASSED! No errors, 100 loops
> [  154.613618] Timer interrupt test FAILED! No interrupt occurred in 1 sec
> [  154.620725] Testing 48048000.timer with 32768 Hz clock ...
> [  156.965324] Timer read test PASSED! No errors, 100 loops
> [  157.965176] Timer interrupt test FAILED! No interrupt occurred in 1 sec
> [  157.972419] Testing 4804a000.timer with 24000000 Hz clock ...
> 
> [root@arago /]# [  160.316753] Timer read test PASSED! No errors, 100 loops
> 
> [root@arago /]# [  161.316728] Timer interrupt test FAILED! No interrupt
> occurred in 1 sec
> [  161.323912] Testing 4804a000.timer with 32768 Hz clock ...
> 
> [root@arago /]# [  163.668490] Timer read test PASSED! No errors, 100 loops
> [  164.668328] Timer interrupt test FAILED! No interrupt occurred in 1 sec
> [  164.675545] Tested 5 timers, skipped 6 timers and detected 6 errors
> [  164.682202] Test iteration 0 complete in 29 secs
> [  164.687104] Test summary: Iterations 1, Errors 6

What is interesting is that it is the interrupt test that is failing for
timers 5-7. Any chance there is a problem with the interrupt mapping? I
checked the documentation for AM335x and I don't see anything obvious
that is wrong with the binding unless the documentation itself is wrong.

Given that the interrupts work on timers 3 and 4 it appears to be a
interrupt configuration problem somewhere. We could adapt the test to
see if an interrupt is pending in the timer peripheral when it fails.
This would tell us that the timer is working but the interrupt is not
being enabled correctly in the interrupt controller.

Cheers
Jon

RE: [PATCH V2 0/7] ARM: OMAP2+: Add device-tree support for timers

[Hiremath, Vaibhav]

On Sat, Sep 29, 2012 at 03:17:51, Hunter, Jon wrote:
> 
> On 09/28/2012 01:51 PM, Vaibhav Hiremath wrote:
> > 
> > 
> > On 9/26/2012 10:23 PM, Jon Hunter wrote:
> >>
> >> On 09/20/2012 06:53 PM, Tony Lindgren wrote:
> >>> * Benoit Cousson <b-cousson@ti.com> [120919 19:24]:
> >>>> Hi Tony,
> >>>>
> >>>> I was about to take the DTS patch, but was wondering if you will pull
> >>>> the driver changes for 3.7.
> >>>
> >>> I suggest that you do a separate branch on top of Paul's hwmod series
> >>> when he posts those if that works for you?
> >>
> >> Benoit, I see that you have pulled in the DTS patch.
> >>
> >> Do you guys want me to rebase the remaining patches with Rob's change on
> >> Tony's master branch and re-submit?
> >>
> > 
> > Jon,
> > 
> > Sorry for delayed response, But I tried using your omap_test application
> > to validate this patch series, but it is failing for me.
> > 
> > How did you test it? Are you running same test application at your end?
> 
> Sorry, I now see you are using the latest test code! I was too hasty
> when I saw the first error ;-)
> 

Jon, have patience ;-)
I understand, sometimes it happens un-intentionally.

> > I am debugging this issue, i just thought I should tell you this before
> > its too late.
> 
> Thanks.
> 
> > Below is the log -
> > 
> > [root@arago /]# echo 3 > /tmp/omap-test/timer/one
> > [   79.612223] omap_dm_timer_request_specific: Please use
> > omap_dm_timer_request_by_cap()
> > [   79.620636] Timer 3 not available!
> 
> This is expected because omap_dm_timer_request_specific() is no longer
> supported. I should remove in the omap-test/timer/one going forward.
> 
> > [root@arago /]#
> > [root@arago /]# echo 3 > /tmp/omap-test/timer/all
> > [  135.111949] Testing 48042000.timer with 24000000 Hz clock ...
> > [root@arago /]# [  137.457389] Timer read test PASSED! No errors, 100 loops
> > [  137.463267] Timer interrupt test PASSED!
> > [  137.467650] Testing 48042000.timer with 32768 Hz clock ...
> > [  139.816892] Timer read test PASSED! No errors, 100 loops
> > [  139.830776] Timer interrupt test PASSED!
> > [  139.835245] Testing 48044000.timer with 24000000 Hz clock ...
> > [  142.183912] Timer read test PASSED! No errors, 100 loops
> > [  142.189734] Timer interrupt test PASSED!
> > [  142.194076] Testing 48044000.timer with 32768 Hz clock ...
> > [  144.543451] Timer read test PASSED! No errors, 100 loops
> > [  144.557334] Timer interrupt test PASSED!
> > [  144.561806] Testing 48046000.timer with 24000000 Hz clock ...
> > [  146.910469] Timer read test PASSED! No errors, 100 loops
> > [  147.910493] Timer interrupt test FAILED! No interrupt occurred in 1 sec
> > [  147.917598] Testing 48046000.timer with 32768 Hz clock ...
> > [  150.262203] Timer read test PASSED! No errors, 100 loops
> > [  151.262049] Timer interrupt test FAILED! No interrupt occurred in 1 sec
> > [  151.269298] Testing 48048000.timer with 24000000 Hz clock ...
> > [  153.613596] Timer read test PASSED! No errors, 100 loops
> > [  154.613618] Timer interrupt test FAILED! No interrupt occurred in 1 sec
> > [  154.620725] Testing 48048000.timer with 32768 Hz clock ...
> > [  156.965324] Timer read test PASSED! No errors, 100 loops
> > [  157.965176] Timer interrupt test FAILED! No interrupt occurred in 1 sec
> > [  157.972419] Testing 4804a000.timer with 24000000 Hz clock ...
> > 
> > [root@arago /]# [  160.316753] Timer read test PASSED! No errors, 100 loops
> > 
> > [root@arago /]# [  161.316728] Timer interrupt test FAILED! No interrupt
> > occurred in 1 sec
> > [  161.323912] Testing 4804a000.timer with 32768 Hz clock ...
> > 
> > [root@arago /]# [  163.668490] Timer read test PASSED! No errors, 100 loops
> > [  164.668328] Timer interrupt test FAILED! No interrupt occurred in 1 sec
> > [  164.675545] Tested 5 timers, skipped 6 timers and detected 6 errors
> > [  164.682202] Test iteration 0 complete in 29 secs
> > [  164.687104] Test summary: Iterations 1, Errors 6
> 
> What is interesting is that it is the interrupt test that is failing for
> timers 5-7. Any chance there is a problem with the interrupt mapping? I
> checked the documentation for AM335x and I don't see anything obvious
> that is wrong with the binding unless the documentation itself is wrong.
> 
> Given that the interrupts work on timers 3 and 4 it appears to be a
> interrupt configuration problem somewhere. We could adapt the test to
> see if an interrupt is pending in the timer peripheral when it fails.
> This would tell us that the timer is working but the interrupt is not
> being enabled correctly in the interrupt controller.
> 

I am also surprised to see this, and as you mentioned, nothing I looks 
obviously wrong to me in  timer5-7. 
I have to debug this further and will keep you updated.

Thanks,
Vaibhav

> Cheers
> Jon
> 

Re: [PATCH V2 0/7] ARM: OMAP2+: Add device-tree support for timers

[Tony Lindgren]

* Jon Hunter <jon-hunter@ti.com> [120928 14:48]:
> 
> What is interesting is that it is the interrupt test that is failing for
> timers 5-7. Any chance there is a problem with the interrupt mapping? I
> checked the documentation for AM335x and I don't see anything obvious
> that is wrong with the binding unless the documentation itself is wrong.

This could also be caused by some timers not being able to wake up
the system from idle?

Regards,

Tony

Re: [PATCH V2 0/7] ARM: OMAP2+: Add device-tree support for timers

[Jon Hunter]

On 09/28/2012 01:51 PM, Vaibhav Hiremath wrote:

[snip]

> Jon,
> 
> Sorry for delayed response, But I tried using your omap_test application
> to validate this patch series, but it is failing for me.
> 
> How did you test it? Are you running same test application at your end?
> 
> I am debugging this issue, i just thought I should tell you this before
> its too late.

By the way, I have not seen any such issues on OMAP2/3/4 and so this
appears to be specific to AM335x. So I would not be too concerned, we
just need to understand why interrupts on some timers are not working on
the AM335x. Probably a configuration issue some where and that can
always be fixed separately.

Cheers
Jon

Re: [PATCH V2 0/7] ARM: OMAP2+: Add device-tree support for timers

[Jon Hunter]

Hi All,

I appear to be having problems receiving emails being sent to me by the
mailing lists. I did not receive any of the responses to this patch set,
but I know see online that there have been a few responses. So sorry for
not responding.

I have been complaining to our IT department but all they tell me is
that they see no issues on their side and it is a problem with the
mailing list. I find it hard to believe that I am subscribe to all 3
mailing lists in CC and I don't get a single copy of any response. I
will complain again. If anyone has any way I can prove it is a problem
on the TI side please let me know.

Thanks
Jon