From: Dmitry Osipenko <digetx@gmail.com>
To: Sowjanya Komatineni <skomatineni@nvidia.com>,
thierry.reding@gmail.com, jonathanh@nvidia.com,
tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com,
linus.walleij@linaro.org, stefan@agner.ch, mark.rutland@arm.com
Cc: pdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org,
linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,
jckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
mperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v7 10/20] clk: tegra: clk-dfll: Add suspend and resume support
Date: Wed, 31 Jul 2019 13:12:29 +0300 [thread overview]
Message-ID: <523ba069-5663-6593-d954-475720864eab@gmail.com> (raw)
In-Reply-To: <1564532424-10449-11-git-send-email-skomatineni@nvidia.com>
31.07.2019 3:20, Sowjanya Komatineni пишет:
> This patch implements DFLL suspend and resume operation.
>
> During system suspend entry, CPU clock will switch CPU to safe
> clock source of PLLP and disables DFLL clock output.
>
> DFLL driver suspend confirms DFLL disable state and errors out on
> being active.
>
> DFLL is re-initialized during the DFLL driver resume as it goes
> through complete reset during suspend entry.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/clk/tegra/clk-dfll.c | 56 ++++++++++++++++++++++++++++++
> drivers/clk/tegra/clk-dfll.h | 2 ++
> drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 1 +
> 3 files changed, 59 insertions(+)
>
> diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
> index f8688c2ddf1a..9900097ec2aa 100644
> --- a/drivers/clk/tegra/clk-dfll.c
> +++ b/drivers/clk/tegra/clk-dfll.c
> @@ -1513,6 +1513,62 @@ static int dfll_init(struct tegra_dfll *td)
> return ret;
> }
>
> +/**
> + * tegra_dfll_suspend - check DFLL is disabled
> + * @dev: DFLL device *
> + *
> + * DFLL clock should be disabled by the CPUFreq driver. So, make
> + * sure it is disabled and disable all clocks needed by the DFLL.
> + */
> +int tegra_dfll_suspend(struct device *dev)
> +{
> + struct tegra_dfll *td = dev_get_drvdata(dev);
> +
> + if (dfll_is_running(td)) {
> + dev_err(td->dev, "dfll is enabled while shouldn't be\n");
> + return -EBUSY;
> + }
> +
> + reset_control_assert(td->dvco_rst);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(tegra_dfll_suspend);
> +
> +/**
> + * tegra_dfll_resume - reinitialize DFLL on resume
> + * @dev: DFLL instance
> + *
> + * DFLL is disabled and reset during suspend and resume.
> + * So, reinitialize the DFLL IP block back for use.
> + * DFLL clock is enabled later in closed loop mode by CPUFreq
> + * driver before switching its clock source to DFLL output.
> + */
> +int tegra_dfll_resume(struct device *dev)
> +{
> + struct tegra_dfll *td = dev_get_drvdata(dev);
> +
> + reset_control_deassert(td->dvco_rst);
> +
> + pm_runtime_irq_safe(td->dev);
1. Interrupts are allowed here.
2. It's enough to invoke that function once during probe.
3. That function bumps runtime-enable count of the parent, which
immediately should raise some questions.
Corollary: you should remove pm_runtime_irq_safe() because it is not needed.
> + pm_runtime_get_sync(td->dev);
> +
> + dfll_set_mode(td, DFLL_DISABLED);
> + dfll_set_default_params(td);
> +
> + if (td->soc->init_clock_trimmers)
> + td->soc->init_clock_trimmers();
> +
> + dfll_set_open_loop_config(td);
> +
> + dfll_init_out_if(td);
> +
> + pm_runtime_put_sync(td->dev);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(tegra_dfll_resume);
> +
> /*
> * DT data fetch
> */
> diff --git a/drivers/clk/tegra/clk-dfll.h b/drivers/clk/tegra/clk-dfll.h
> index 1b14ebe7268b..fb209eb5f365 100644
> --- a/drivers/clk/tegra/clk-dfll.h
> +++ b/drivers/clk/tegra/clk-dfll.h
> @@ -42,5 +42,7 @@ int tegra_dfll_register(struct platform_device *pdev,
> struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev);
> int tegra_dfll_runtime_suspend(struct device *dev);
> int tegra_dfll_runtime_resume(struct device *dev);
> +int tegra_dfll_suspend(struct device *dev);
> +int tegra_dfll_resume(struct device *dev);
>
> #endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */
> diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> index e84b6d52cbbd..2ac2679d696d 100644
> --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> @@ -631,6 +631,7 @@ static int tegra124_dfll_fcpu_remove(struct platform_device *pdev)
> static const struct dev_pm_ops tegra124_dfll_pm_ops = {
> SET_RUNTIME_PM_OPS(tegra_dfll_runtime_suspend,
> tegra_dfll_runtime_resume, NULL)
> + SET_SYSTEM_SLEEP_PM_OPS(tegra_dfll_suspend, tegra_dfll_resume)
> };
>
> static struct platform_driver tegra124_dfll_fcpu_driver = {
>
next prev parent reply other threads:[~2019-07-31 10:12 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-31 0:20 [PATCH v7 00/20] SC7 entry and exit support for Tegra210 Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 01/20] pinctrl: tegra: Add suspend and resume support Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 02/20] pinctrl: tegra210: Add Tegra210 pinctrl pm ops Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 03/20] clk: tegra: divider: Save and restore divider rate Sowjanya Komatineni
2019-07-31 10:49 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 04/20] clk: tegra: pllout: Save and restore pllout context Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 05/20] clk: tegra: pll: Save and restore pll context Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 06/20] clk: tegra: Support for OSC context save and restore Sowjanya Komatineni
2019-07-31 11:11 ` Dmitry Osipenko
2019-07-31 21:04 ` Sowjanya Komatineni
2019-08-01 10:53 ` Dmitry Osipenko
2019-08-01 18:06 ` Sowjanya Komatineni
2019-08-01 18:42 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 07/20] clk: tegra: clk-periph: Add save and restore support Sowjanya Komatineni
2019-07-31 9:50 ` Dmitry Osipenko
2019-07-31 10:44 ` Dmitry Osipenko
2019-07-31 23:09 ` Sowjanya Komatineni
2019-08-01 17:58 ` Sowjanya Komatineni
2019-08-01 19:00 ` Dmitry Osipenko
2019-08-01 19:42 ` Sowjanya Komatineni
2019-08-01 20:17 ` Dmitry Osipenko
2019-08-01 20:31 ` Sowjanya Komatineni
2019-08-01 20:54 ` Dmitry Osipenko
2019-08-01 21:30 ` Sowjanya Komatineni
2019-08-01 23:19 ` Sowjanya Komatineni
2019-08-01 23:49 ` Sowjanya Komatineni
2019-08-02 12:38 ` Dmitry Osipenko
2019-08-02 18:33 ` Sowjanya Komatineni
2019-08-02 20:13 ` Dmitry Osipenko
2019-08-02 20:17 ` Dmitry Osipenko
2019-08-02 20:32 ` Sowjanya Komatineni
2019-08-02 21:15 ` Dmitry Osipenko
2019-08-02 21:18 ` Sowjanya Komatineni
2019-08-02 23:51 ` Sowjanya Komatineni
2019-08-03 10:33 ` Dmitry Osipenko
2019-08-03 17:01 ` Sowjanya Komatineni
2019-08-03 23:44 ` Sowjanya Komatineni
2019-08-04 12:24 ` Dmitry Osipenko
2019-08-04 12:31 ` Dmitry Osipenko
2019-08-02 12:32 ` Dmitry Osipenko
2019-08-02 18:43 ` Sowjanya Komatineni
2019-08-02 20:20 ` Dmitry Osipenko
2019-08-02 20:37 ` Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 08/20] clk: tegra: clk-super: Fix to enable PLLP branches to CPU Sowjanya Komatineni
2019-07-31 10:14 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 09/20] clk: tegra: clk-super: Add save and restore support Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 10/20] clk: tegra: clk-dfll: Add suspend and resume support Sowjanya Komatineni
2019-07-31 10:12 ` Dmitry Osipenko [this message]
2019-07-31 0:20 ` [PATCH v7 11/20] cpufreq: tegra124: " Sowjanya Komatineni
2019-07-31 10:23 ` Dmitry Osipenko
2019-07-31 11:14 ` Dmitry Osipenko
2019-07-31 21:05 ` Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 12/20] clk: tegra210: Use fence_udelay during PLLU init Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 13/20] clk: tegra210: Add suspend and resume support Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 14/20] soc/tegra: pmc: Allow to support more tegras wake Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 15/20] soc/tegra: pmc: Add pmc wake support for tegra210 Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 16/20] arm64: tegra: Enable wake from deep sleep on RTC alarm Sowjanya Komatineni
2019-07-31 11:04 ` Dmitry Osipenko
2019-07-31 21:08 ` Sowjanya Komatineni
2019-08-01 10:43 ` Dmitry Osipenko
2019-08-01 17:56 ` Sowjanya Komatineni
2019-08-01 18:39 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 17/20] soc/tegra: pmc: Configure core power request polarity Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 18/20] soc/tegra: pmc: Configure deep sleep control settings Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 19/20] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 20/20] arm64: dts: tegra210-p3450: Jetson Nano " Sowjanya Komatineni
2019-07-31 21:10 [PATCH v7 00/20] SC7 entry and exit support for Tegra210 Sowjanya Komatineni
2019-07-31 21:10 ` [PATCH v7 10/20] clk: tegra: clk-dfll: Add suspend and resume support Sowjanya Komatineni
2019-08-01 10:18 ` Dmitry Osipenko
2019-08-01 10:37 ` Dmitry Osipenko
2019-08-01 16:10 ` Sowjanya Komatineni
2019-08-01 17:10 ` Dmitry Osipenko
2019-08-01 17:53 ` Sowjanya Komatineni
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