[PATCH] PCI: layerscape: Add 'dma-coherent' property

[PATCH] PCI: layerscape: Add 'dma-coherent' property

[Liu Gang]

Add 'dma-coherent' description for PCI nodes.

The 'dma-coherent' indicates that the hardware IP block can ensure
the coherency of the data transferred from/to the IP block. This
can avoid the software cache flush/invalid actions, and improve
the performance significantly.

The PCI IP block of ls1043a has this capability, so adding
this feature to improve the PCI performance.

Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
---
 Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index ef683b2..41e9f55 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -24,6 +24,9 @@ Required properties:
   The first entry must be a link to the SCFG device node
   The second entry must be '0' or '1' based on physical PCIe controller index.
   This is used to get SCFG PEXN registers
+- dma-coherent: Indicates that the hardware IP block can ensure the coherency
+  of the data transferred from/to the IP block. This can avoid the software
+  cache flush/invalid actions, and improve the performance significantly.
 
 Example:
 
@@ -38,6 +41,7 @@ Example:
 		#address-cells = <3>;
 		#size-cells = <2>;
 		device_type = "pci";
+		dma-coherent;
 		num-lanes = <4>;
 		bus-range = <0x0 0xff>;
 		ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
-- 
2.1.0.27.g96db324

[PATCH] arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes

[Liu Gang]

The 'dma-coherent' indicates that the hardware IP block can ensure
the coherency of the data transferred from/to the IP block. This
can avoid the software cache flush/invalid actions, and improve
the performance significantly.

The PCI IP block of ls1043a has this capability, so adding this
feature to improve the PCI performance.

Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index de0323b..21a30f7 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -479,6 +479,7 @@
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
+			dma-coherent;
 			num-lanes = <4>;
 			bus-range = <0x0 0xff>;
 			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
@@ -503,6 +504,7 @@
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
+			dma-coherent;
 			num-lanes = <2>;
 			bus-range = <0x0 0xff>;
 			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
@@ -527,6 +529,7 @@
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
+			dma-coherent;
 			num-lanes = <2>;
 			bus-range = <0x0 0xff>;
 			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
-- 
2.1.0.27.g96db324

Re: [PATCH] arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes

[Scott Wood]

On 06/07/2016 02:06 AM, Liu Gang wrote:
> The 'dma-coherent' indicates that the hardware IP block can ensure
> the coherency of the data transferred from/to the IP block. This
> can avoid the software cache flush/invalid actions, and improve
> the performance significantly.
> 
> The PCI IP block of ls1043a has this capability, so adding this
> feature to improve the PCI performance.
> 
> Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
>  1 file changed, 3 insertions(+)

Why not ls2080a as well?
What about non-PCI devices?

Pretty much everything on these chips should be coherent as long as it's
properly configured.

-Scott

RE: [PATCH] arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes

[Gang Liu]

> From: Scott Wood
> 
> On 06/07/2016 02:06 AM, Liu Gang wrote:
> > The 'dma-coherent' indicates that the hardware IP block can ensure the
> > coherency of the data transferred from/to the IP block. This can avoid
> > the software cache flush/invalid actions, and improve the performance
> > significantly.
> >
> > The PCI IP block of ls1043a has this capability, so adding this
> > feature to improve the PCI performance.
> >
> > Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
> >  1 file changed, 3 insertions(+)
> 
> Why not ls2080a as well?
[Liu Gang] ls2080 should also include this property, we can add it after verification.
 
> What about non-PCI devices?
> 
> Pretty much everything on these chips should be coherent as long as it's
> properly configured.
[Liu Gang] you are right. For the layerscape platforms including CCI or CCN internal bus,
theoretically, pretty much IP blocks (PCI/non-PCI) should be coherent. But this depends
on the properly hardware and software configurations. (ls1012a PCI devices cannot implement
the coherent duo to hardware issue)
So I think we'd better to add this property after each IP block's verification.

Thanks!
Liu Gang
>
> -Scott

Re: [PATCH] PCI: layerscape: Add 'dma-coherent' property

[Rob Herring]

On Tue, Jun 07, 2016 at 02:55:45PM +0800, Liu Gang wrote:
> Add 'dma-coherent' description for PCI nodes.
> 
> The 'dma-coherent' indicates that the hardware IP block can ensure
> the coherency of the data transferred from/to the IP block. This
> can avoid the software cache flush/invalid actions, and improve
> the performance significantly.
> 
> The PCI IP block of ls1043a has this capability, so adding
> this feature to improve the PCI performance.
> 
> Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
> ---
>  Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
>  1 file changed, 4 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>

> 
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index ef683b2..41e9f55 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -24,6 +24,9 @@ Required properties:
>    The first entry must be a link to the SCFG device node
>    The second entry must be '0' or '1' based on physical PCIe controller index.
>    This is used to get SCFG PEXN registers
> +- dma-coherent: Indicates that the hardware IP block can ensure the coherency
> +  of the data transferred from/to the IP block. This can avoid the software
> +  cache flush/invalid actions, and improve the performance significantly.
>  
>  Example:
>  
> @@ -38,6 +41,7 @@ Example:
>  		#address-cells = <3>;
>  		#size-cells = <2>;
>  		device_type = "pci";
> +		dma-coherent;
>  		num-lanes = <4>;
>  		bus-range = <0x0 0xff>;
>  		ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
> -- 
> 2.1.0.27.g96db324
> 

Re: [PATCH] PCI: layerscape: Add 'dma-coherent' property

[Robin Murphy]

On 07/06/16 07:55, Liu Gang wrote:
> Add 'dma-coherent' description for PCI nodes.
>
> The 'dma-coherent' indicates that the hardware IP block can ensure
> the coherency of the data transferred from/to the IP block. This
> can avoid the software cache flush/invalid actions, and improve
> the performance significantly.

Note that depending on the exact details it may actually be *necessary* 
for correctness - if the properties of the system are such that 
cacheable writes from the root complex might allocate directly into some 
level of cache without going to RAM, then having the CPU think the 
device is non-coherent and thus invalidate the cache before reading back 
from the buffer will result in data loss. But yeah, the performance is 
the most visible aspect ;)

Robin.

> The PCI IP block of ls1043a has this capability, so adding
> this feature to improve the PCI performance.
>
> Signed-off-by: Liu Gang <Gang.Liu-3arQi8VN3Tc@public.gmane.org>
> ---
>   Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index ef683b2..41e9f55 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -24,6 +24,9 @@ Required properties:
>     The first entry must be a link to the SCFG device node
>     The second entry must be '0' or '1' based on physical PCIe controller index.
>     This is used to get SCFG PEXN registers
> +- dma-coherent: Indicates that the hardware IP block can ensure the coherency
> +  of the data transferred from/to the IP block. This can avoid the software
> +  cache flush/invalid actions, and improve the performance significantly.
>
>   Example:
>
> @@ -38,6 +41,7 @@ Example:
>   		#address-cells = <3>;
>   		#size-cells = <2>;
>   		device_type = "pci";
> +		dma-coherent;
>   		num-lanes = <4>;
>   		bus-range = <0x0 0xff>;
>   		ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
>

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Re: [PATCH] PCI: layerscape: Add 'dma-coherent' property

[Shawn Guo]

On Tue, Jun 07, 2016 at 02:55:45PM +0800, Liu Gang wrote:
> Add 'dma-coherent' description for PCI nodes.
> 
> The 'dma-coherent' indicates that the hardware IP block can ensure
> the coherency of the data transferred from/to the IP block. This
> can avoid the software cache flush/invalid actions, and improve
> the performance significantly.
> 
> The PCI IP block of ls1043a has this capability, so adding
> this feature to improve the PCI performance.
> 
> Signed-off-by: Liu Gang <Gang.Liu-3arQi8VN3Tc@public.gmane.org>

Applied both, thanks.
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