[PATCH 0/6] ARM: NUC900: Add NUC970 SoC support

[PATCH 0/6] ARM: NUC900: Add NUC970 SoC support

[Wan Zongshun]

Hi,

This patch series added Nuvoton new SoC NUC970 development board
support, this nuc970 belongs to nuc900 series, but many features are
not compatible with old nuc900 SoCs like nuc910, nuc920.

Those patches are basing on old w90x900 codes, and are using standard
linux subsystem interface, such as dts, driver/clk, driver/clocksource
, driver/irqchip drivers.

The old w90x900 plat such as nuc910,nuc960 codes will also be changed
to new style according to nuc970 codes after those patches was accepted.

Wan Zongshun (6):
  ARM: NUC900: Add nuc970 machine support
  ARM: dts: nuc900: Add nuc970 dts files
  Clocksource: add nuc970 clocksource driver
  irqchip: add irqchip driver for nuc900
  clk: add Clock driver for nuc970
  nuc900: add nuc970 platform defconfig file

 .../devicetree/bindings/arm/nuvoton/nuc970.txt     |   30 +
 arch/arm/boot/dts/Makefile                         |    1 +
 arch/arm/boot/dts/nuc970-evb.dts                   |   20 +
 arch/arm/boot/dts/nuc970.dtsi                      |   93 ++
 arch/arm/configs/nuc970_defconfig                  | 1278 ++++++++++++++++++++
 arch/arm/mach-w90x900/Kconfig                      |   25 +
 arch/arm/mach-w90x900/Makefile                     |    3 +
 arch/arm/mach-w90x900/include/mach/irqs.h          |   69 ++
 .../mach-w90x900/include/mach/nuc970-regs-aic.h    |   53 +
 .../mach-w90x900/include/mach/nuc970-regs-gcr.h    |   56 +
 .../mach-w90x900/include/mach/nuc970-regs-timer.h  |   44 +
 arch/arm/mach-w90x900/mach-nuc970.c                |  144 +++
 drivers/clk/Makefile                               |    1 +
 drivers/clk/nuc900/Makefile                        |    6 +
 drivers/clk/nuc900/clk-apll.c                      |  168 +++
 drivers/clk/nuc900/clk-ccf.h                       |   53 +
 drivers/clk/nuc900/clk-nuc970.c                    |  920 ++++++++++++++
 drivers/clk/nuc900/clk-upll.c                      |   83 ++
 drivers/clocksource/Kconfig                        |    8 +
 drivers/clocksource/Makefile                       |    1 +
 drivers/clocksource/timer-nuc900.c                 |  207 ++++
 drivers/irqchip/Makefile                           |    1 +
 drivers/irqchip/irq-nuc900.c                       |  104 ++
 include/dt-bindings/clock/nuc970-clock.h           |  233 ++++
 24 files changed, 3601 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/nuvoton/nuc970.txt
 create mode 100644 arch/arm/boot/dts/nuc970-evb.dts
 create mode 100644 arch/arm/boot/dts/nuc970.dtsi
 create mode 100644 arch/arm/configs/nuc970_defconfig
 create mode 100644 arch/arm/mach-w90x900/include/mach/nuc970-regs-aic.h
 create mode 100644 arch/arm/mach-w90x900/include/mach/nuc970-regs-gcr.h
 create mode 100644 arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
 create mode 100644 arch/arm/mach-w90x900/mach-nuc970.c
 create mode 100644 drivers/clk/nuc900/Makefile
 create mode 100644 drivers/clk/nuc900/clk-apll.c
 create mode 100644 drivers/clk/nuc900/clk-ccf.h
 create mode 100644 drivers/clk/nuc900/clk-nuc970.c
 create mode 100644 drivers/clk/nuc900/clk-upll.c
 create mode 100644 drivers/clocksource/timer-nuc900.c
 create mode 100644 drivers/irqchip/irq-nuc900.c
 create mode 100644 include/dt-bindings/clock/nuc970-clock.h

-- 
2.7.4

[PATCH 1/6] ARM: NUC900: Add nuc970 machine support

[Wan Zongshun]

NUC970 is a new SoC of Nuvoton nuc900 series, this patch is
to add machine file support for it.

Signed-off-by: Wan Zongshun <mcuos.com@gmail.com>
---
 arch/arm/mach-w90x900/Kconfig                      |  25 ++++
 arch/arm/mach-w90x900/Makefile                     |   3 +
 .../mach-w90x900/include/mach/nuc970-regs-gcr.h    |  56 ++++++++
 arch/arm/mach-w90x900/mach-nuc970.c                | 144 +++++++++++++++++++++
 4 files changed, 228 insertions(+)
 create mode 100644 arch/arm/mach-w90x900/include/mach/nuc970-regs-gcr.h
 create mode 100644 arch/arm/mach-w90x900/mach-nuc970.c

diff --git a/arch/arm/mach-w90x900/Kconfig b/arch/arm/mach-w90x900/Kconfig
index 69bab32..050833e 100644
--- a/arch/arm/mach-w90x900/Kconfig
+++ b/arch/arm/mach-w90x900/Kconfig
@@ -15,6 +15,21 @@ config CPU_NUC960
 	help
 	  Support for NUCP960 of Nuvoton NUC900 CPUs.
 
+config SOC_NUC970
+	bool
+        select GENERIC_IRQ_CHIP
+        select SOC_BUS
+        select IRQ_DOMAIN
+        select MULTI_IRQ_HANDLER
+        select USE_OF
+        select HAVE_CLK_PREPARE
+        select HAVE_MACH_CLKDEV
+	select COMMON_CLK
+        select NUC900_TIMER
+	help
+	  Support for NUCP970 of Nuvoton NUC900 CPUs.
+
+
 menu "W90P910 Machines"
 
 config MACH_W90P910EVB
@@ -46,4 +61,14 @@ config MACH_W90N960EVB
 
 endmenu
 
+menu "NUC970 Machines"
+
+config MACH_NUC970EVB
+	bool "Nuvoton NUC970 Evaluation Board"
+	select SOC_NUC970
+	help
+	   Say Y here if you are using the Nuvoton NUC970EVB
+
+endmenu
+
 endif
diff --git a/arch/arm/mach-w90x900/Makefile b/arch/arm/mach-w90x900/Makefile
index 828c032..6c99e6f 100644
--- a/arch/arm/mach-w90x900/Makefile
+++ b/arch/arm/mach-w90x900/Makefile
@@ -4,8 +4,10 @@
 
 # Object file lists.
 
+ifeq ($(CONFIG_SOC_NUC970),)
 obj-y				:= irq.o time.o mfp.o gpio.o clock.o
 obj-y				+= clksel.o dev.o cpu.o
+endif
 # W90X900 CPU support files
 
 obj-$(CONFIG_CPU_W90P910)	+= nuc910.o
@@ -17,3 +19,4 @@ obj-$(CONFIG_CPU_NUC960)	+= nuc960.o
 obj-$(CONFIG_MACH_W90P910EVB)	+= mach-nuc910evb.o
 obj-$(CONFIG_MACH_W90P950EVB)	+= mach-nuc950evb.o
 obj-$(CONFIG_MACH_W90N960EVB)	+= mach-nuc960evb.o
+obj-$(CONFIG_MACH_NUC970EVB)	+= mach-nuc970.o
diff --git a/arch/arm/mach-w90x900/include/mach/nuc970-regs-gcr.h b/arch/arm/mach-w90x900/include/mach/nuc970-regs-gcr.h
new file mode 100644
index 0000000..e7eb653
--- /dev/null
+++ b/arch/arm/mach-w90x900/include/mach/nuc970-regs-gcr.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2016 Wan Zongshun <mcuos.com@gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_REGS_GCR_H
+#define __ASM_ARCH_REGS_GCR_H
+
+/* NUC970 GCR regs */
+
+#define REG_PDID	0x000
+#define REG_PWRON	0x004
+#define REG_ARBCON	0x008
+#define REG_LVRDCR	0x020
+#define REG_MISCFCR	0x030
+#define REG_MISCIER	0x040
+#define REG_MISCISR	0x044
+#define REG_ROMSUM0	0x048
+#define REG_ROMSUM1	0x04C
+#define REG_WKUPSER	0x058
+#define REG_WKUPSSR	0x05C
+#define REG_AHBIPRST	0x060
+#define REG_APBIPRST0	0x064
+#define REG_APBIPRST1	0x068
+#define REG_RSTSTS	0x06C
+#define REG_DDR_DS_CR	0x0E0
+#define REG_PORDISCR	0x100
+#define REG_ICEDBGCR	0x104
+#define REG_WRPRTR	0x1FC
+#define REG_MFP_GPA_L	0x070
+#define REG_MFP_GPA_H	0x074
+#define REG_MFP_GPB_L	0x078
+#define REG_MFP_GPB_H	0x07C
+#define REG_MFP_GPC_L	0x080
+#define REG_MFP_GPC_H	0x084
+#define REG_MFP_GPD_L	0x088
+#define REG_MFP_GPD_H	0x08C
+#define REG_MFP_GPE_L	0x090
+#define REG_MFP_GPE_H	0x094
+#define REG_MFP_GPF_L	0x098
+#define REG_MFP_GPF_H	0x09C
+#define REG_MFP_GPG_L	0x0A0
+#define REG_MFP_GPG_H	0x0A4
+#define REG_MFP_GPH_L	0x0A8
+#define REG_MFP_GPH_H	0x0AC
+#define REG_MFP_GPI_L	0x0B0
+#define REG_MFP_GPI_H	0x0B4
+#define REG_MFP_GPJ_L	0x0B8
+
+#endif /*  __ASM_ARCH_REGS_GCR_H */
diff --git a/arch/arm/mach-w90x900/mach-nuc970.c b/arch/arm/mach-w90x900/mach-nuc970.c
new file mode 100644
index 0000000..cbae366
--- /dev/null
+++ b/arch/arm/mach-w90x900/mach-nuc970.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2016 Wan Zongshun <mcuos.com@gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/reboot.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/sys_soc.h>
+#include <linux/semaphore.h>
+
+#include <asm/system_misc.h>
+#include <asm/mach/arch.h>
+#include <mach/nuc970-regs-gcr.h>
+
+#define GCR_CHIPID		0x00
+#define GCR_CHIPID_MASK		0x00ffffff
+
+int chipid;
+int versionid;
+static void __iomem *wtcr_addr;
+
+static void __init nuc970_init(void)
+{
+
+}
+
+static int  __init *nuc900_get_id(void)
+{
+	struct device_node *np;
+	void __iomem *gcr_base;
+	int id;
+
+	np = of_find_compatible_node(NULL, NULL, "nuvoton,gcr");
+	gcr_base = of_iomap(np, 0);
+	WARN_ON(!gcr_base);
+
+	id = readl(gcr_base + GCR_CHIPID);
+
+	chipid = id & GCR_CHIPID_MASK;
+	versionid = (id >> 24) & 0xff;
+
+	iounmap(gcr_base);
+	of_node_put(np);
+
+	return 0;
+}
+
+static int __init nuc900_restart_init(void)
+{
+	struct device_node *np;
+
+	np = of_find_compatible_node(NULL, NULL, "nuvoton,gcr");
+	wtcr_addr = of_iomap(np, 0);
+	if (!wtcr_addr)
+		return -ENODEV;
+
+	of_node_put(np);
+
+	return 0;
+}
+
+static void __init nuc970_machine_init(void)
+{
+	struct device_node *root;
+	struct device *parent;
+	struct soc_device *soc_dev;
+	struct soc_device_attribute *soc_dev_attr;
+	int ret;
+
+	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+	if (!soc_dev_attr)
+		return;
+
+	root = of_find_node_by_path("/");
+	ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
+	if (ret)
+		return;
+
+	nuc900_get_id();
+
+	soc_dev_attr->family = kasprintf(GFP_KERNEL, "Nuvoton NUC900 MCUs");
+	soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%x", chipid);
+	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%x", versionid);
+
+	soc_dev = soc_device_register(soc_dev_attr);
+	if (IS_ERR(soc_dev)) {
+		kfree(soc_dev_attr->family);
+		kfree(soc_dev_attr->soc_id);
+		kfree(soc_dev_attr->revision);
+		kfree(soc_dev_attr);
+		return;
+	}
+
+	parent = soc_device_to_device(soc_dev);
+
+	if (of_machine_is_compatible("nuvoton,nuc970evb"))
+		nuc970_init();
+
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
+
+	nuc900_restart_init();
+
+}
+
+static const char *nuc970_dt_compat[] __initconst = {
+	"nuvoton,nuc970evb",
+	NULL,
+};
+
+void nuc970_restart(enum reboot_mode mode, const char *cmd)
+{
+	if (wtcr_addr) {
+		while (__raw_readl(wtcr_addr + REG_WRPRTR) != 1) {
+			__raw_writel(0x59, wtcr_addr + REG_WRPRTR);
+			__raw_writel(0x16, wtcr_addr + REG_WRPRTR);
+			__raw_writel(0x88, wtcr_addr + REG_WRPRTR);
+		}
+
+		__raw_writel(1, wtcr_addr + REG_AHBIPRST);
+	}
+
+	soft_restart(0);
+}
+
+DT_MACHINE_START(nuc970_dt, "Nuvoton nuc970 evb")
+	.atag_offset	= 0x100,
+	.init_machine	= nuc970_machine_init,
+	.restart	= nuc970_restart,
+	.dt_compat = nuc970_dt_compat,
+MACHINE_END
-- 
2.7.4

Re: [PATCH 1/6] ARM: NUC900: Add nuc970 machine support

[Arnd Bergmann]

On Saturday, June 25, 2016 6:37:17 PM CEST Wan Zongshun wrote:
> NUC970 is a new SoC of Nuvoton nuc900 series, this patch is
> to add machine file support for it.
> 
> Signed-off-by: Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Nice to see some activity on the port!

> ---
>  arch/arm/mach-w90x900/Kconfig                      |  25 ++++
>  arch/arm/mach-w90x900/Makefile                     |   3 +
>  .../mach-w90x900/include/mach/nuc970-regs-gcr.h    |  56 ++++++++
>  arch/arm/mach-w90x900/mach-nuc970.c                | 144 +++++++++++++++++++++
>  4 files changed, 228 insertions(+)
>  create mode 100644 arch/arm/mach-w90x900/include/mach/nuc970-regs-gcr.h
>  create mode 100644 arch/arm/mach-w90x900/mach-nuc970.c
> 
> diff --git a/arch/arm/mach-w90x900/Kconfig b/arch/arm/mach-w90x900/Kconfig
> index 69bab32..050833e 100644
> --- a/arch/arm/mach-w90x900/Kconfig
> +++ b/arch/arm/mach-w90x900/Kconfig
> @@ -15,6 +15,21 @@ config CPU_NUC960
>  	help
>  	  Support for NUCP960 of Nuvoton NUC900 CPUs.
>  
> +config SOC_NUC970
> +	bool
> +        select GENERIC_IRQ_CHIP
> +        select SOC_BUS
> +        select IRQ_DOMAIN
> +        select MULTI_IRQ_HANDLER
> +        select USE_OF
> +        select HAVE_CLK_PREPARE
> +        select HAVE_MACH_CLKDEV
> +	select COMMON_CLK
> +        select NUC900_TIMER
> +	help
> +	  Support for NUCP970 of Nuvoton NUC900 CPUs.
> +

[style] This looks whitespace damaged, and please sort the line alphabetically.

I see you have done this in a way that is basically compatible with
CONFIG_ARCH_MULTIPLATFORM, good.

What is HAVE_MACH_CLKDEV for?

> @@ -46,4 +61,14 @@ config MACH_W90N960EVB
>  
>  endmenu
>  
> +menu "NUC970 Machines"
> +
> +config MACH_NUC970EVB
> +	bool "Nuvoton NUC970 Evaluation Board"
> +	select SOC_NUC970
> +	help
> +	   Say Y here if you are using the Nuvoton NUC970EVB
> +
> +endmenu

I'd leave out this entry, with the way have have structured the code (correctly),
there is no need to separate SoC-specific code from board specific code, since
they are the same.

> diff --git a/arch/arm/mach-w90x900/include/mach/nuc970-regs-gcr.h b/arch/arm/mach-w90x900/include/mach/nuc970-regs-gcr.h
> new file mode 100644
> index 0000000..e7eb653
> --- /dev/null
> +++ b/arch/arm/mach-w90x900/include/mach/nuc970-regs-gcr.h

Can you move the new headers to arch/arm/mach-w90x900/ directly?

> +static int __init nuc900_restart_init(void)
> +{
> +	struct device_node *np;
> +
> +	np = of_find_compatible_node(NULL, NULL, "nuvoton,gcr");
> +	wtcr_addr = of_iomap(np, 0);
> +	if (!wtcr_addr)
> +		return -ENODEV;
> +
> +	of_node_put(np);
> +
> +	return 0;
> +}

Is this a watchdog node? If it is, the restart logic should just
move into the watchdog driver.


> +	if (of_machine_is_compatible("nuvoton,nuc970evb"))
> +		nuc970_init();

What is this for?

> +	of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);

We have actually moved away from using the soc_device as using the parent
for the other devices, just probe them separately. In fact the soc_device
could be handled by a driver in drivers/soc/nuvoton/

> +static const char *nuc970_dt_compat[] __initconst = {
> +	"nuvoton,nuc970evb",
> +	NULL,
> +};
> +
> +void nuc970_restart(enum reboot_mode mode, const char *cmd)
> +{
> +	if (wtcr_addr) {
> +		while (__raw_readl(wtcr_addr + REG_WRPRTR) != 1) {
> +			__raw_writel(0x59, wtcr_addr + REG_WRPRTR);
> +			__raw_writel(0x16, wtcr_addr + REG_WRPRTR);
> +			__raw_writel(0x88, wtcr_addr + REG_WRPRTR);
> +		}
> +
> +		__raw_writel(1, wtcr_addr + REG_AHBIPRST);
> +	}

Please use writel() instead of __raw_writel().

> +	soft_restart(0);
> +}
> +
> +DT_MACHINE_START(nuc970_dt, "Nuvoton nuc970 evb")
> +	.atag_offset	= 0x100,

The .atag_offset can be removed here.

	Arnd
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Re: [PATCH 1/6] ARM: NUC900: Add nuc970 machine support

[Wan Zongshun]

On 2016年06月29日 23:19, Arnd Bergmann wrote:
> On Saturday, June 25, 2016 6:37:17 PM CEST Wan Zongshun wrote:
>> NUC970 is a new SoC of Nuvoton nuc900 series, this patch is
>> to add machine file support for it.
>>
>> Signed-off-by: Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
> Nice to see some activity on the port!
>
>> ---
>>   arch/arm/mach-w90x900/Kconfig                      |  25 ++++
>>   arch/arm/mach-w90x900/Makefile                     |   3 +
>>   .../mach-w90x900/include/mach/nuc970-regs-gcr.h    |  56 ++++++++
>>   arch/arm/mach-w90x900/mach-nuc970.c                | 144 +++++++++++++++++++++
>>   4 files changed, 228 insertions(+)
>>   create mode 100644 arch/arm/mach-w90x900/include/mach/nuc970-regs-gcr.h
>>   create mode 100644 arch/arm/mach-w90x900/mach-nuc970.c
>>
>> diff --git a/arch/arm/mach-w90x900/Kconfig b/arch/arm/mach-w90x900/Kconfig
>> index 69bab32..050833e 100644
>> --- a/arch/arm/mach-w90x900/Kconfig
>> +++ b/arch/arm/mach-w90x900/Kconfig
>> @@ -15,6 +15,21 @@ config CPU_NUC960
>>   	help
>>   	  Support for NUCP960 of Nuvoton NUC900 CPUs.
>>
>> +config SOC_NUC970
>> +	bool
>> +        select GENERIC_IRQ_CHIP
>> +        select SOC_BUS
>> +        select IRQ_DOMAIN
>> +        select MULTI_IRQ_HANDLER
>> +        select USE_OF
>> +        select HAVE_CLK_PREPARE
>> +        select HAVE_MACH_CLKDEV
>> +	select COMMON_CLK
>> +        select NUC900_TIMER
>> +	help
>> +	  Support for NUCP970 of Nuvoton NUC900 CPUs.
>> +
>
> [style] This looks whitespace damaged, and please sort the line alphabetically.

Sure, changed.

>
> I see you have done this in a way that is basically compatible with
> CONFIG_ARCH_MULTIPLATFORM, good.
>
> What is HAVE_MACH_CLKDEV for?
>
>> @@ -46,4 +61,14 @@ config MACH_W90N960EVB
>>
>>   endmenu
>>
>> +menu "NUC970 Machines"
>> +
>> +config MACH_NUC970EVB
>> +	bool "Nuvoton NUC970 Evaluation Board"
>> +	select SOC_NUC970
>> +	help
>> +	   Say Y here if you are using the Nuvoton NUC970EVB
>> +
>> +endmenu
>
> I'd leave out this entry, with the way have have structured the code (correctly),
> there is no need to separate SoC-specific code from board specific code, since
> they are the same.
>

Sure, removed it.

>> diff --git a/arch/arm/mach-w90x900/include/mach/nuc970-regs-gcr.h b/arch/arm/mach-w90x900/include/mach/nuc970-regs-gcr.h
>> new file mode 100644
>> index 0000000..e7eb653
>> --- /dev/null
>> +++ b/arch/arm/mach-w90x900/include/mach/nuc970-regs-gcr.h
>
> Can you move the new headers to arch/arm/mach-w90x900/ directly?
>
>> +static int __init nuc900_restart_init(void)
>> +{
>> +	struct device_node *np;
>> +
>> +	np = of_find_compatible_node(NULL, NULL, "nuvoton,gcr");
>> +	wtcr_addr = of_iomap(np, 0);
>> +	if (!wtcr_addr)
>> +		return -ENODEV;
>> +
>> +	of_node_put(np);
>> +
>> +	return 0;
>> +}
>
> Is this a watchdog node? If it is, the restart logic should just
> move into the watchdog driver.

It is not watchdog node, just be global System control register node.

>
>
>> +	if (of_machine_is_compatible("nuvoton,nuc970evb"))
>> +		nuc970_init();
>
> What is this for?

Currently, no used, remove it.

>
>> +	of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
>
> We have actually moved away from using the soc_device as using the parent
> for the other devices, just probe them separately. In fact the soc_device
> could be handled by a driver in drivers/soc/nuvoton/

Do you think I should add nuc900 soc driver in this folder?
If I want to add nuc900 soc driver in drivers/soc/nuvoton/, can I keep 
my current dts structure no change, or Must I add a new node name soc {}?

I went through the code:soc-realview.c for reference, but I have no idea
about how to re-structure my dts file to match this type soc driver.

>
>> +static const char *nuc970_dt_compat[] __initconst = {
>> +	"nuvoton,nuc970evb",
>> +	NULL,
>> +};
>> +
>> +void nuc970_restart(enum reboot_mode mode, const char *cmd)
>> +{
>> +	if (wtcr_addr) {
>> +		while (__raw_readl(wtcr_addr + REG_WRPRTR) != 1) {
>> +			__raw_writel(0x59, wtcr_addr + REG_WRPRTR);
>> +			__raw_writel(0x16, wtcr_addr + REG_WRPRTR);
>> +			__raw_writel(0x88, wtcr_addr + REG_WRPRTR);
>> +		}
>> +
>> +		__raw_writel(1, wtcr_addr + REG_AHBIPRST);
>> +	}
>
> Please use writel() instead of __raw_writel().

Does this change apply to all others drivers? or just machine file to 
use writel()?

>
>> +	soft_restart(0);
>> +}
>> +
>> +DT_MACHINE_START(nuc970_dt, "Nuvoton nuc970 evb")
>> +	.atag_offset	= 0x100,

Removed it, thanks!

>
> The .atag_offset can be removed here.
>
> 	Arnd
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
>
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Re: [PATCH 1/6] ARM: NUC900: Add nuc970 machine support

[Arnd Bergmann]

On Tuesday, July 5, 2016 3:38:23 PM CEST Wan Zongshun wrote:
> On 2016年06月29日 23:19, Arnd Bergmann wrote:
> >> diff --git a/arch/arm/mach-w90x900/include/mach/nuc970-regs-gcr.h b/arch/arm/mach-w90x900/include/mach/nuc970-regs-gcr.h
> >> new file mode 100644
> >> index 0000000..e7eb653
> >> --- /dev/null
> >> +++ b/arch/arm/mach-w90x900/include/mach/nuc970-regs-gcr.h
> >
> > Can you move the new headers to arch/arm/mach-w90x900/ directly?
> >
> >> +static int __init nuc900_restart_init(void)
> >> +{
> >> +	struct device_node *np;
> >> +
> >> +	np = of_find_compatible_node(NULL, NULL, "nuvoton,gcr");
> >> +	wtcr_addr = of_iomap(np, 0);
> >> +	if (!wtcr_addr)
> >> +		return -ENODEV;
> >> +
> >> +	of_node_put(np);
> >> +
> >> +	return 0;
> >> +}
> >
> > Is this a watchdog node? If it is, the restart logic should just
> > move into the watchdog driver.
> 
> It is not watchdog node, just be global System control register node.

Ok. Then I'd say it should go into drivers/power/reset/

If you make the the gcr a syscon node, you can probably use the
syscon-reboot driver directly, or as a reference.

> >> +	of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
> >
> > We have actually moved away from using the soc_device as using the parent
> > for the other devices, just probe them separately. In fact the soc_device
> > could be handled by a driver in drivers/soc/nuvoton/
> 
> Do you think I should add nuc900 soc driver in this folder?

Yes.

> If I want to add nuc900 soc driver in drivers/soc/nuvoton/, can I keep 
> my current dts structure no change, or Must I add a new node name soc {}?
>
> I went through the code:soc-realview.c for reference, but I have no idea
> about how to re-structure my dts file to match this type soc driver.

You don't need to change the DT for this, all the driver needs to
do now is to find out the information about the soc and register it
as a soc_device so it shows up in sysfs.

> >> +static const char *nuc970_dt_compat[] __initconst = {
> >> +	"nuvoton,nuc970evb",
> >> +	NULL,
> >> +};
> >> +
> >> +void nuc970_restart(enum reboot_mode mode, const char *cmd)
> >> +{
> >> +	if (wtcr_addr) {
> >> +		while (__raw_readl(wtcr_addr + REG_WRPRTR) != 1) {
> >> +			__raw_writel(0x59, wtcr_addr + REG_WRPRTR);
> >> +			__raw_writel(0x16, wtcr_addr + REG_WRPRTR);
> >> +			__raw_writel(0x88, wtcr_addr + REG_WRPRTR);
> >> +		}
> >> +
> >> +		__raw_writel(1, wtcr_addr + REG_AHBIPRST);
> >> +	}
> >
> > Please use writel() instead of __raw_writel().
> 
> Does this change apply to all others drivers? or just machine file to 
> use writel()?

All drivers. You don't need to immediately change existing drivers, we
can clean them up some other day, but please use readl/writel for new code.

	Arnd
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[PATCH 2/6] ARM: dts: nuc900: Add nuc970 dts files

[Wan Zongshun]

This patch is to add dts support for nuc970 platform.

Signed-off-by: Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 .../devicetree/bindings/arm/nuvoton/nuc970.txt     |  30 +++
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/nuc970-evb.dts                   |  20 ++
 arch/arm/boot/dts/nuc970.dtsi                      |  93 ++++++++
 include/dt-bindings/clock/nuc970-clock.h           | 233 +++++++++++++++++++++
 5 files changed, 377 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/nuvoton/nuc970.txt
 create mode 100644 arch/arm/boot/dts/nuc970-evb.dts
 create mode 100644 arch/arm/boot/dts/nuc970.dtsi
 create mode 100644 include/dt-bindings/clock/nuc970-clock.h

diff --git a/Documentation/devicetree/bindings/arm/nuvoton/nuc970.txt b/Documentation/devicetree/bindings/arm/nuvoton/nuc970.txt
new file mode 100644
index 0000000..df8637a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/nuvoton/nuc970.txt
@@ -0,0 +1,30 @@
+Nuvoton NUC970 SoC platform Device Tree Bindings
+------------------------------------------
+
+Boards with the NUC970 SoC shall have the following properties:
+
+Root node required properties:
+- compatible: Should be "nuvoton,nuc970evb", "nuvoton,nuc970"
+
+Timer required properties:
+- compatible: Should be "nuvoton,tmr"
+- reg: Should contain registers location and length
+- interrupts: hwirq is direct mapping to irq number
+- clocks: phandle to input clock.
+
+Clock required properties:
+- compatible: Should be "nuvoton,clk"
+- reg: Should contain registers location and length
+
+Interrupt-controller required properties
+- compatible: Should be "nuvoton,aic"
+- reg: Should contain registers location and length
+- interrupt-cells: set to 1
+
+GCR register required properties:
+- compatible: Should be "nuvoton,gcr"
+- reg: Should contain registers location and length
+
+Uart required properties:
+- compatible: Should be "nuvoton,nuc970-uart"
+- reg: Should contain registers location and length
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 06b6c2d..c2e2a53 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -891,6 +891,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
 dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \
 	aspeed-ast2500-evb.dtb
+dtb-$(CONFIG_SOC_NUC970) += nuc970-evb.dtb
 endif
 
 dtstree		:= $(srctree)/$(src)
diff --git a/arch/arm/boot/dts/nuc970-evb.dts b/arch/arm/boot/dts/nuc970-evb.dts
new file mode 100644
index 0000000..bd56ad1
--- /dev/null
+++ b/arch/arm/boot/dts/nuc970-evb.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2016 Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "nuc970.dtsi"
+
+/ {
+	model = "NUC970 EVB Board";
+	compatible = "nuvoton,nuc970evb", "nuvoton,nuc970";
+
+};
+
diff --git a/arch/arm/boot/dts/nuc970.dtsi b/arch/arm/boot/dts/nuc970.dtsi
new file mode 100644
index 0000000..8a6c225
--- /dev/null
+++ b/arch/arm/boot/dts/nuc970.dtsi
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2016 Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/nuc970-clock.h>
+
+/ {
+	compatible = "nuvoton,nuc970evb", "nuvoton,nuc970";
+
+	interrupt-parent = <&aic>;
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	memory {
+		reg = <0x00000000 0x04000000>;
+	};
+
+	cpus {
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
+		};
+	};
+
+	ahb@B0000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xB0000000 0x9000>;
+		ranges;
+
+		gcr: gcr@B0000000 {
+			compatible = "nuvoton,gcr";
+			reg = <0xB0000000 0x200>;
+		};
+
+		clks: clk@B0000200 {
+			compatible = "nuvoton,clk";
+			reg = <0xB0000200 0x200>;
+			#clock-cells = <1>;
+		};
+
+	};
+
+	apb@B8000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xB8000000 0xF000>;
+		ranges;
+
+		aic: interrupt-controller@B8002000 {
+			compatible = "nuvoton,aic";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0xB8002000 0x1000>;
+		};
+
+
+		tmr@0xB8001000 {
+			compatible = "nuvoton,tmr";
+			reg = <0xB8001000 0x1000>;
+			interrupts = <16>;
+			clocks = <&clks TIMER0_GATE>,
+				 <&clks TIMER1_GATE>;
+			clock-names = "timer0", "timer1";
+
+		};
+
+		uart0: serial@B8000000 {
+			compatible = "nuvoton,nuc970-uart";
+			reg = <0xB8000000 0x1000>;
+			interrupts = <36>;
+			clocks = <&clks UART0_GATE>,
+				 <&clks UART0_ECLK_GATE>;
+			clock-names = "uart0", "uart0_eclk";
+			clock-frequency = <12000000>;
+		};
+	};
+};
diff --git a/include/dt-bindings/clock/nuc970-clock.h b/include/dt-bindings/clock/nuc970-clock.h
new file mode 100644
index 0000000..cbfcc77
--- /dev/null
+++ b/include/dt-bindings/clock/nuc970-clock.h
@@ -0,0 +1,233 @@
+/*
+ * Copyright 2016 Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_NUC970_H
+#define __DT_BINDINGS_CLOCK_NUC970_H
+
+/*SOURCE*/
+
+#define	XIN			0
+#define	APLL			1
+#define	UPLL			2
+#define	XIN32K			3
+#define	XIN128_DIV		4
+
+/*ECLK*/
+
+#define	USB_APLLDIV		5
+#define	USB_UPLLDIV		6
+#define	USB_ECLK_MUX		7
+#define	USB_ECLK_DIV		8
+#define	USB_ECLK_GATE		9
+#define	SD_APLLDIV		10
+#define	SD_UPLLDIV		11
+#define	SD_ECLK_MUX		12
+#define	SD_ECLK_DIV		13
+#define	SD_ECLK_GATE		14
+#define	LCD_APLLDIV		15
+#define	LCD_UPLLDIV		16
+#define	LCD_ECLK_MUX		17
+#define	LCD_ECLK_DIV		18
+#define	LCD_ECLK_GATE		19
+#define	ADC_APLLDIV		20
+#define	ADC_UPLLDIV		21
+#define	ADC_ECLK_MUX		22
+#define	ADC_ECLK_DIV		23
+#define	ADC_ECLK_GATE		24
+#define	AUDIO_APLLDIV		25
+#define	AUDIO_UPLLDIV		26
+#define	AUDIO_ECLK_MUX		27
+#define	AUDIO_ECLK_DIV		28
+#define	AUDIO_ECLK_GATE		29
+#define	CAP_APLLDIV		30
+#define	CAP_UPLLDIV		31
+#define	CAP_ECLK_MUX		32
+#define	CAP_ECLK_DIV		33
+#define	CAP_ECLK_GATE		34
+#define	SDH_APLLDIV		35
+#define	SDH_UPLLDIV		36
+#define	SDH_ECLK_MUX		37
+#define	SDH_ECLK_DIV		38
+#define	SDH_ECLK_GATE		39
+#define	EMMC_APLLDIV		40
+#define	EMMC_UPLLDIV		41
+#define	EMMC_ECLK_MUX		42
+#define	EMMC_ECLK_DIV		43
+#define	EMMC_ECLK_GATE		44
+#define	UART0_APLLDIV		45
+#define	UART0_UPLLDIV		46
+#define	UART0_ECLK_MUX		47
+#define	UART0_ECLK_DIV		48
+#define	UART0_ECLK_GATE		49
+#define	UART1_APLLDIV		50
+#define	UART1_UPLLDIV		51
+#define	UART1_ECLK_MUX		52
+#define	UART1_ECLK_DIV		53
+#define	UART1_ECLK_GATE		54
+#define	UART2_APLLDIV		55
+#define	UART2_UPLLDIV		56
+#define	UART2_ECLK_MUX		57
+#define	UART2_ECLK_DIV		58
+#define	UART2_ECLK_GATE		59
+#define	UART3_APLLDIV		60
+#define	UART3_UPLLDIV		61
+#define	UART3_ECLK_MUX		62
+#define	UART3_ECLK_DIV		63
+#define	UART3_ECLK_GATE		64
+#define	UART4_APLLDIV		65
+#define	UART4_UPLLDIV		66
+#define	UART4_ECLK_MUX		67
+#define	UART4_ECLK_DIV		68
+#define	UART4_ECLK_GATE		69
+#define	UART5_APLLDIV		70
+#define	UART5_UPLLDIV		71
+#define	UART5_ECLK_MUX		72
+#define	UART5_ECLK_DIV		73
+#define	UART5_ECLK_GATE		74
+#define	UART6_APLLDIV		75
+#define	UART6_UPLLDIV		76
+#define	UART6_ECLK_MUX		77
+#define	UART6_ECLK_DIV		78
+#define	UART6_ECLK_GATE		79
+#define	UART7_APLLDIV		80
+#define	UART7_UPLLDIV		81
+#define	UART7_ECLK_MUX		82
+#define	UART7_ECLK_DIV		83
+#define	UART7_ECLK_GATE		84
+#define	UART8_APLLDIV		85
+#define	UART8_UPLLDIV		86
+#define	UART8_ECLK_MUX		87
+#define	UART8_ECLK_DIV		88
+#define	UART8_ECLK_GATE		89
+#define	UART9_APLLDIV		90
+#define	UART9_UPLLDIV		91
+#define	UART9_ECLK_MUX		92
+#define	UART9_ECLK_DIV		93
+#define	UART9_ECLK_GATE		94
+#define	UART10_APLLDIV		95
+#define	UART10_UPLLDIV		96
+#define	UART10_ECLK_MUX		97
+#define	UART10_ECLK_DIV		98
+#define	UART10_ECLK_GATE	99
+#define	SYSTEM_APLLDIV		100
+#define	SYSTEM_UPLLDIV		101
+#define	SYSTEM_ECLK_MUX		102
+#define	SYSTEM_ECLK_DIV		103
+#define	SYSTEM_ECLK_GATE	104
+#define	GPIO_ECLK_MUX		105
+#define	GPIO_ECLK_DIV		106
+#define	GPIO_ECLK_GATE		107
+#define	KPI_ECLK_MUX		108
+#define	KPI_ECLK_DIV		109
+#define	KPI_ECLK_GATE		110
+#define	ETIMER0_ECLK_MUX	111
+#define	ETIMER0_ECLK_GATE	12
+#define	ETIMER1_ECLK_MUX	113
+#define	ETIMER1_ECLK_GATE	114
+#define	ETIMER2_ECLK_MUX	115
+#define	ETIMER2_ECLK_GATE	116
+#define	ETIMER3_ECLK_MUX	117
+#define	ETIMER3_ECLK_GATE	118
+#define	WWDT_ECLK_MUX		119
+#define	WWDT_ECLK_GATE		120
+#define	WDT_ECLK_MUX		121
+#define	WDT_ECLK_GATE		122
+#define	SMC0_ECLK_DIV		123
+#define	SMC0_ECLK_GATE		124
+#define	SMC0_GATE		125
+#define	SMC1_ECLK_DIV		126
+#define	SMC1_ECLK_GATE		127
+#define	SMC1_GATE		128
+
+/*SYS*/
+
+#define	SYS_MUX			129
+#define	SYS_DIV			130
+#define	CPU_DIV			131
+#define	CPU_GATE		132
+#define	DDR_GATE		133
+
+/*HCLK*/
+
+#define	HCLK_GATE		134
+#define	HCLK1_DIV		135
+#define	GDMA_GATE		136
+#define	EBI_GATE		137
+#define	TIC_GATE		138
+#define	SRAM_GATE		139
+#define	HCLKN_DIV		140
+#define	DRAM_GATE		141
+#define	HCLK234_DIV		142
+#define	USBH_GATE		143
+#define	EMAC1_GATE		144
+#define	EMAC1_ECLK_DIV		145
+#define	EMAC1_ECLK_GATE		146
+#define	USBD_GATE		147
+#define	FMI_GATE		148
+#define	NAND_GATE		149
+#define	EMMC_GATE		150
+#define	CRYPTO_GATE		151
+#define	JPEG_GATE		152
+#define	JPEG_ECLK_DIV		153
+#define	JPEG_ECLK_GATE		154
+#define	GE2D_GATE		155
+#define	GE2D_ECLK_DIV		156
+#define	GE2D_ECLK_GATE		157
+#define	EMAC0_GATE		158
+#define	EMAC0_ECLK_DIV		159
+#define	EMAC0_ECLK_GATE		160
+#define	SDH_GATE		161
+#define	AUDIO_GATE		162
+#define	LCD_GATE		163
+#define	CAP_GATE		164
+#define	SENSOR_GATE		165
+
+/*PCLK*/
+
+#define	PCLK_DIV		166
+#define	PCLK4096_DIV		167
+#define	I2C0_GATE		168
+#define	I2C1_GATE		169
+#define	SPI0_GATE		170
+#define	SPI1_GATE		171
+#define	UART0_GATE		172
+#define	UART1_GATE		173
+#define	UART2_GATE		174
+#define	UART3_GATE		175
+#define	UART4_GATE		176
+#define	UART5_GATE		177
+#define	UART6_GATE		178
+#define	UART7_GATE		179
+#define	UART8_GATE		180
+#define	UART9_GATE		181
+#define	UART10_GATE		182
+#define	TIMER0_GATE		183
+#define	TIMER1_GATE		184
+#define	TIMER2_GATE		185
+#define	TIMER3_GATE		186
+#define	TIMER4_GATE		187
+#define	WDT_GATE		188
+#define	RTC_GATE		189
+#define	WWDT_GATE		190
+#define	GPIO_GATE		191
+#define	ADC_GATE		192
+#define	KPI_GATE		193
+#define	MTPC_GATE		194
+#define	PWM_GATE		195
+#define	ETIMER0_GATE		196
+#define	ETIMER1_GATE		197
+#define	ETIMER2_GATE		198
+#define	ETIMER3_GATE		199
+#define	CAN0_GATE		200
+#define	CAN1_GATE		201
+#define	NUC970_CLK_MAX		202
+
+#endif
-- 
2.7.4

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Re: [PATCH 2/6] ARM: dts: nuc900: Add nuc970 dts files

[Rob Herring]

On Sat, Jun 25, 2016 at 06:37:18PM +0800, Wan Zongshun wrote:
> This patch is to add dts support for nuc970 platform.
> 
> Signed-off-by: Wan Zongshun <mcuos.com@gmail.com>
> ---
>  .../devicetree/bindings/arm/nuvoton/nuc970.txt     |  30 +++
>  arch/arm/boot/dts/Makefile                         |   1 +
>  arch/arm/boot/dts/nuc970-evb.dts                   |  20 ++
>  arch/arm/boot/dts/nuc970.dtsi                      |  93 ++++++++
>  include/dt-bindings/clock/nuc970-clock.h           | 233 +++++++++++++++++++++
>  5 files changed, 377 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/nuvoton/nuc970.txt
>  create mode 100644 arch/arm/boot/dts/nuc970-evb.dts
>  create mode 100644 arch/arm/boot/dts/nuc970.dtsi
>  create mode 100644 include/dt-bindings/clock/nuc970-clock.h
> 
> diff --git a/Documentation/devicetree/bindings/arm/nuvoton/nuc970.txt b/Documentation/devicetree/bindings/arm/nuvoton/nuc970.txt
> new file mode 100644
> index 0000000..df8637a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/nuvoton/nuc970.txt
> @@ -0,0 +1,30 @@
> +Nuvoton NUC970 SoC platform Device Tree Bindings
> +------------------------------------------
> +
> +Boards with the NUC970 SoC shall have the following properties:
> +
> +Root node required properties:
> +- compatible: Should be "nuvoton,nuc970evb", "nuvoton,nuc970"
> +
> +Timer required properties:

This should go in bindings/timer/

> +- compatible: Should be "nuvoton,tmr"

Needs an SoC specific compatible string

> +- reg: Should contain registers location and length
> +- interrupts: hwirq is direct mapping to irq number
> +- clocks: phandle to input clock.
> +
> +Clock required properties:

This should go in bindings/clock/

> +- compatible: Should be "nuvoton,clk"

SoC specific...

> +- reg: Should contain registers location and length
> +
> +Interrupt-controller required properties

And so on...

> +- compatible: Should be "nuvoton,aic"
> +- reg: Should contain registers location and length
> +- interrupt-cells: set to 1
> +
> +GCR register required properties:
> +- compatible: Should be "nuvoton,gcr"
> +- reg: Should contain registers location and length
> +
> +Uart required properties:
> +- compatible: Should be "nuvoton,nuc970-uart"
> +- reg: Should contain registers location and length

Re: [PATCH 2/6] ARM: dts: nuc900: Add nuc970 dts files

[Arnd Bergmann]

On Saturday, June 25, 2016 6:37:18 PM CEST Wan Zongshun wrote:
> This patch is to add dts support for nuc970 platform.
> 
> Signed-off-by: Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  .../devicetree/bindings/arm/nuvoton/nuc970.txt     |  30 +++
>  arch/arm/boot/dts/Makefile                         |   1 +
>  arch/arm/boot/dts/nuc970-evb.dts                   |  20 ++
>  arch/arm/boot/dts/nuc970.dtsi                      |  93 ++++++++
>  include/dt-bindings/clock/nuc970-clock.h           | 233 +++++++++++++++++++++
>  5 files changed, 377 insertions(+)

I'd suggest splitting this into multiple patches: the binding, the dts files and the header.

> +Boards with the NUC970 SoC shall have the following properties:
> +
> +Root node required properties:
> +- compatible: Should be "nuvoton,nuc970evb", "nuvoton,nuc970"

Better don't mention "nuvoton,nuc970evb", as that is the board specific
identifier: we don't want to have to list every single board.

> +Timer required properties:
> +- compatible: Should be "nuvoton,tmr"
> +- reg: Should contain registers location and length
> +- interrupts: hwirq is direct mapping to irq number
> +- clocks: phandle to input clock.
> +
> +Clock required properties:
> +- compatible: Should be "nuvoton,clk"
> +- reg: Should contain registers location and length
> +
> +Interrupt-controller required properties
> +- compatible: Should be "nuvoton,aic"
> +- reg: Should contain registers location and length
> +- interrupt-cells: set to 1
> +
> +GCR register required properties:
> +- compatible: Should be "nuvoton,gcr"
> +- reg: Should contain registers location and length

These compatible strings are all very generic, and should contain the
SoC name.

> diff --git a/arch/arm/boot/dts/nuc970.dtsi b/arch/arm/boot/dts/nuc970.dtsi
> new file mode 100644
> index 0000000..8a6c225
> --- /dev/null
> +++ b/arch/arm/boot/dts/nuc970.dtsi
> @@ -0,0 +1,93 @@
> +/*
> + * Copyright 2016 Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include "skeleton.dtsi"
> +#include <dt-bindings/clock/nuc970-clock.h>
> +
> +/ {
> +	compatible = "nuvoton,nuc970evb", "nuvoton,nuc970";
> +
> +	interrupt-parent = <&aic>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	memory {
> +		reg = <0x00000000 0x04000000>;
> +	};

Better split this into SoC-specific and board-specific contents, the
aliases and memory should go into the board.dts file, along with the
alias for the serial port.

> +	ahb@B0000000 {

Don't capatilize the hexadecimal numbers.

> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0xB0000000 0x9000>;
> +		ranges;

A simple-bus should not have a 'reg' property. You can have a 'ranges'
though, to translate the addresses in the child nodes.

	Arnd

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[PATCH 4/6] irqchip: add irqchip driver for nuc900

[Wan Zongshun]

This patch is to add irqchip driver support for nuc900 plat,
current this driver only supports nuc970 SoC.

Signed-off-by: Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/mach-w90x900/include/mach/irqs.h          |  69 ++++++++++++++
 .../mach-w90x900/include/mach/nuc970-regs-aic.h    |  53 +++++++++++
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-nuc900.c                       | 104 +++++++++++++++++++++
 4 files changed, 227 insertions(+)
 create mode 100644 arch/arm/mach-w90x900/include/mach/nuc970-regs-aic.h
 create mode 100644 drivers/irqchip/irq-nuc900.c

diff --git a/arch/arm/mach-w90x900/include/mach/irqs.h b/arch/arm/mach-w90x900/include/mach/irqs.h
index 9d5cba3..c56d4bb 100644
--- a/arch/arm/mach-w90x900/include/mach/irqs.h
+++ b/arch/arm/mach-w90x900/include/mach/irqs.h
@@ -28,6 +28,8 @@
 
 /* Main cpu interrupts */
 
+#if !defined(CONFIG_SOC_NUC970)
+
 #define IRQ_WDT		W90X900_IRQ(1)
 #define IRQ_GROUP0	W90X900_IRQ(2)
 #define IRQ_GROUP1	W90X900_IRQ(3)
@@ -83,4 +85,71 @@
 #define	IRQ_GROUP1_IRQ6	0x00000040
 #define	IRQ_GROUP1_IRQ7	0x00000080
 
+#else
+
+/*For nuc970*/
+#define IRQ_WDT		W90X900_IRQ(1)
+#define IRQ_WWDT	W90X900_IRQ(2)
+#define IRQ_LVD		W90X900_IRQ(3)
+#define IRQ_EXT0	W90X900_IRQ(4)
+#define IRQ_EXT1	W90X900_IRQ(5)
+#define IRQ_EXT2	W90X900_IRQ(6)
+#define IRQ_EXT3	W90X900_IRQ(7)
+#define IRQ_EXT4	W90X900_IRQ(8)
+#define IRQ_EXT5	W90X900_IRQ(9)
+#define IRQ_EXT6	W90X900_IRQ(10)
+#define IRQ_EXT7	W90X900_IRQ(11)
+#define IRQ_ACTL	W90X900_IRQ(12)
+#define IRQ_LCD		W90X900_IRQ(13)
+#define IRQ_CAP		W90X900_IRQ(14)
+#define IRQ_RTC		W90X900_IRQ(15)
+#define IRQ_TMR0	W90X900_IRQ(16)
+#define IRQ_TMR1	W90X900_IRQ(17)
+#define IRQ_ADC		W90X900_IRQ(18)
+#define IRQ_EMC0RX	W90X900_IRQ(19)
+#define IRQ_EMC1RX	W90X900_IRQ(20)
+#define IRQ_EMC0TX	W90X900_IRQ(21)
+#define IRQ_EMC1TX	W90X900_IRQ(22)
+#define IRQ_EHCI	W90X900_IRQ(23)
+#define IRQ_OHCI	W90X900_IRQ(24)
+#define IRQ_GDMA0	W90X900_IRQ(25)
+#define IRQ_GDMA1	W90X900_IRQ(26)
+#define IRQ_SDH		W90X900_IRQ(27)
+#define IRQ_FMI		W90X900_IRQ(28)
+#define IRQ_UDC		W90X900_IRQ(29)
+#define IRQ_TMR2	W90X900_IRQ(30)
+#define IRQ_TMR3	W90X900_IRQ(31)
+#define IRQ_TMR4	W90X900_IRQ(32)
+#define IRQ_JPEG	W90X900_IRQ(33)
+#define IRQ_GE2D	W90X900_IRQ(34)
+#define IRQ_CRYPTO	W90X900_IRQ(35)
+#define IRQ_UART0	W90X900_IRQ(36)
+#define IRQ_UART1	W90X900_IRQ(37)
+#define IRQ_UART2	W90X900_IRQ(38)
+#define IRQ_UART4	W90X900_IRQ(39)
+#define IRQ_UART6	W90X900_IRQ(40)
+#define IRQ_UART8	W90X900_IRQ(41)
+#define IRQ_UART10	W90X900_IRQ(42)
+#define IRQ_UART3	W90X900_IRQ(43)
+#define IRQ_UART5	W90X900_IRQ(44)
+#define IRQ_UART7	W90X900_IRQ(45)
+#define IRQ_UART9	W90X900_IRQ(46)
+#define IRQ_ETIMER0	W90X900_IRQ(47)
+#define IRQ_ETIMER1	W90X900_IRQ(48)
+#define IRQ_ETIMER2	W90X900_IRQ(49)
+#define IRQ_ETIMER3	W90X900_IRQ(50)
+#define IRQ_SPI0	W90X900_IRQ(51)
+#define IRQ_SPI1	W90X900_IRQ(52)
+#define IRQ_I2C0	W90X900_IRQ(53)
+#define IRQ_I2C1	W90X900_IRQ(54)
+#define IRQ_SMC0	W90X900_IRQ(55)
+#define IRQ_SMC1	W90X900_IRQ(56)
+#define IRQ_GPIO	W90X900_IRQ(57)
+#define IRQ_CAN0	W90X900_IRQ(58)
+#define IRQ_CAN1	W90X900_IRQ(59)
+#define IRQ_PWM		W90X900_IRQ(60)
+#define IRQ_KPI		W90X900_IRQ(61)
+#define NR_IRQS		(IRQ_KPI+1)
+#endif
+
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-w90x900/include/mach/nuc970-regs-aic.h b/arch/arm/mach-w90x900/include/mach/nuc970-regs-aic.h
new file mode 100644
index 0000000..7a77016
--- /dev/null
+++ b/arch/arm/mach-w90x900/include/mach/nuc970-regs-aic.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2016 Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_REGS_AIC_H
+#define __ASM_ARCH_REGS_AIC_H
+
+/*NUC970 AIC regs*/
+
+#define	REG_AIC_SCR1	0x00
+#define	REG_AIC_SCR2	0x04
+#define	REG_AIC_SCR3	0x08
+#define	REG_AIC_SCR4	0x0C
+#define	REG_AIC_SCR5	0x10
+#define	REG_AIC_SCR6	0x14
+#define	REG_AIC_SCR7	0x18
+#define	REG_AIC_SCR8	0x1C
+#define	REG_AIC_SCR9	0x20
+#define	REG_AIC_SCR10	0x24
+#define	REG_AIC_SCR11	0x28
+#define	REG_AIC_SCR12	0x2C
+#define	REG_AIC_SCR13	0x30
+#define	REG_AIC_SCR14	0x34
+#define	REG_AIC_SCR15	0x38
+#define	REG_AIC_IRSR	0x100
+#define	REG_AIC_IRSRH	0x104
+#define	REG_AIC_IASR	0x108
+#define	REG_AIC_IASRH	0x10C
+#define	REG_AIC_ISR	0x110
+#define	REG_AIC_ISRH	0x114
+#define	REG_AIC_IPER	0x118
+#define	REG_AIC_ISNR	0x120
+#define	REG_AIC_OISR	0x124
+#define	REG_AIC_IMR	0x128
+#define	REG_AIC_IMRH	0x12C
+#define	REG_AIC_MECR	0x130
+#define	REG_AIC_MECRH	0x134
+#define	REG_AIC_MDCR	0x138
+#define	REG_AIC_MDCRH	0x13C
+#define	REG_AIC_SSCR	0x140
+#define	REG_AIC_SSCRH	0x144
+#define	REG_AIC_SCCR	0x148
+#define	REG_AIC_SCCRH	0x14C
+#define	REG_AIC_EOSCR	0x150
+
+#endif /*  __ASM_ARCH_REGS_AIC_H */
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 38853a1..9ccd5af8a 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -69,3 +69,4 @@ obj-$(CONFIG_PIC32_EVIC)		+= irq-pic32-evic.o
 obj-$(CONFIG_MVEBU_ODMI)		+= irq-mvebu-odmi.o
 obj-$(CONFIG_LS_SCFG_MSI)		+= irq-ls-scfg-msi.o
 obj-$(CONFIG_EZNPS_GIC)			+= irq-eznps.o
+obj-$(CONFIG_SOC_NUC970)		+= irq-nuc900.o
diff --git a/drivers/irqchip/irq-nuc900.c b/drivers/irqchip/irq-nuc900.c
new file mode 100644
index 0000000..50308b9b
--- /dev/null
+++ b/drivers/irqchip/irq-nuc900.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2016 Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include <asm/exception.h>
+#include <asm/hardirq.h>
+
+#include <mach/nuc970-regs-aic.h>
+
+static void __iomem *aic_base;
+static struct irq_domain *aic_domain;
+#define MAKE_HWIRQ(irqnum)	(irqnum)
+
+static void nuc970_irq_mask(struct irq_data *d)
+{
+	if (d->irq < 32)
+		__raw_writel(1 << (d->irq), aic_base + REG_AIC_MDCR);
+	else
+		__raw_writel(1 << (d->irq - 32), aic_base + REG_AIC_MDCRH);
+}
+
+static void nuc970_irq_ack(struct irq_data *d)
+{
+	__raw_writel(0x01, aic_base + REG_AIC_EOSCR);
+}
+
+static void nuc970_irq_unmask(struct irq_data *d)
+{
+	if (d->irq < 32)
+		__raw_writel(1 << (d->irq), aic_base + REG_AIC_MECR);
+	else
+		__raw_writel(1 << (d->irq - 32), aic_base + REG_AIC_MECRH);
+}
+
+static struct irq_chip nuc970_irq_chip = {
+	.irq_ack	= nuc970_irq_ack,
+	.irq_mask	= nuc970_irq_mask,
+	.irq_unmask	= nuc970_irq_unmask,
+};
+
+void __exception_irq_entry aic_handle_irq(struct pt_regs *regs)
+{
+	u32 hwirq;
+
+	hwirq = __raw_readl(aic_base + REG_AIC_IPER);
+	hwirq = __raw_readl(aic_base + REG_AIC_ISNR);
+	if (!hwirq)
+		__raw_writel(0x01, aic_base + REG_AIC_EOSCR);
+
+	handle_IRQ((irq_find_mapping(aic_domain, hwirq)), regs);
+}
+
+static int aic_irq_domain_map(struct irq_domain *d, unsigned int virq,
+			      irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(virq, &nuc970_irq_chip, handle_level_irq);
+	irq_clear_status_flags(virq, IRQ_NOREQUEST);
+
+	return 0;
+}
+
+static struct irq_domain_ops aic_irq_domain_ops = {
+	.map = aic_irq_domain_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+static int __init aic_of_init(struct device_node *node,
+			      struct device_node *parent)
+{
+	aic_base = of_iomap(node, 0);
+	if (!aic_base)
+		panic("%s: unable to map IC registers\n", node->full_name);
+
+	__raw_writel(0xFFFFFFFC, aic_base + REG_AIC_MDCR);
+	__raw_writel(0xFFFFFFFF, aic_base + REG_AIC_MDCRH);
+
+	aic_domain = irq_domain_add_linear(node, NR_IRQS,
+					   &aic_irq_domain_ops, NULL);
+
+	if (!aic_domain)
+		panic("%s: unable to create IRQ domain\n", node->full_name);
+
+	set_handle_irq(aic_handle_irq);
+	return 0;
+}
+
+IRQCHIP_DECLARE(nuc970, "nuvoton,aic", aic_of_init);
-- 
2.7.4

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Re: [PATCH 4/6] irqchip: add irqchip driver for nuc900

[Arnd Bergmann]

On Saturday, June 25, 2016 6:37:20 PM CEST Wan Zongshun wrote:
> +#define IRQ_WDT		W90X900_IRQ(1)
> +#define IRQ_WWDT	W90X900_IRQ(2)
> +#define IRQ_LVD		W90X900_IRQ(3)
> +#define IRQ_EXT0	W90X900_IRQ(4)
> +#define IRQ_EXT1	W90X900_IRQ(5)
> +#define IRQ_EXT2	W90X900_IRQ(6)
> +#define IRQ_EXT3	W90X900_IRQ(7)
> +#define IRQ_EXT4	W90X900_IRQ(8)
> +#define IRQ_EXT5	W90X900_IRQ(9)
> +#define IRQ_EXT6	W90X900_IRQ(10)

I'd suggest dropping the list, the contents are now in the dts.

> diff --git a/arch/arm/mach-w90x900/include/mach/nuc970-regs-aic.h b/arch/arm/mach-w90x900/include/mach/nuc970-regs-aic.h
> new file mode 100644
> index 0000000..7a77016
> --- /dev/null
> +++ b/arch/arm/mach-w90x900/include/mach/nuc970-regs-aic.h
> @@ -0,0 +1,53 @@
> +#ifndef __ASM_ARCH_REGS_AIC_H
> +#define __ASM_ARCH_REGS_AIC_H
> +
> +/*NUC970 AIC regs*/
> +
> +#define	REG_AIC_SCR1	0x00
> +#define	REG_AIC_SCR2	0x04
> +#define	REG_AIC_SCR3	0x08
> +#define	REG_AIC_SCR4	0x0C
> +#define	REG_AIC_SCR5	0x10

And like the clk driver, these should all be in the irqchip driver instead
of a separate header.

> +
> +static void __iomem *aic_base;
> +static struct irq_domain *aic_domain;
> +#define MAKE_HWIRQ(irqnum)	(irqnum)

The macro appears to be unused.

> +static void nuc970_irq_mask(struct irq_data *d)
> +{
> +	if (d->irq < 32)
> +		__raw_writel(1 << (d->irq), aic_base + REG_AIC_MDCR);
> +	else
> +		__raw_writel(1 << (d->irq - 32), aic_base + REG_AIC_MDCRH);
> +}

writel()

	Arnd

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Re: [PATCH 4/6] irqchip: add irqchip driver for nuc900

[Wan Zongshun]

On 2016年06月29日 23:27, Arnd Bergmann wrote:
> On Saturday, June 25, 2016 6:37:20 PM CEST Wan Zongshun wrote:
>> +#define IRQ_WDT		W90X900_IRQ(1)
>> +#define IRQ_WWDT	W90X900_IRQ(2)
>> +#define IRQ_LVD		W90X900_IRQ(3)
>> +#define IRQ_EXT0	W90X900_IRQ(4)
>> +#define IRQ_EXT1	W90X900_IRQ(5)
>> +#define IRQ_EXT2	W90X900_IRQ(6)
>> +#define IRQ_EXT3	W90X900_IRQ(7)
>> +#define IRQ_EXT4	W90X900_IRQ(8)
>> +#define IRQ_EXT5	W90X900_IRQ(9)
>> +#define IRQ_EXT6	W90X900_IRQ(10)
>
> I'd suggest dropping the list, the contents are now in the dts.

Do you think I should put one irqmap header file into this
/arch/arm/boot/dts/include/dt-bindings folder, or I should removed those 
irqnumber map anywhere, just hardcode the irqnumber in dts file?

>
>> diff --git a/arch/arm/mach-w90x900/include/mach/nuc970-regs-aic.h b/arch/arm/mach-w90x900/include/mach/nuc970-regs-aic.h
>> new file mode 100644
>> index 0000000..7a77016
>> --- /dev/null
>> +++ b/arch/arm/mach-w90x900/include/mach/nuc970-regs-aic.h
>> @@ -0,0 +1,53 @@
>> +#ifndef __ASM_ARCH_REGS_AIC_H
>> +#define __ASM_ARCH_REGS_AIC_H
>> +
>> +/*NUC970 AIC regs*/
>> +
>> +#define	REG_AIC_SCR1	0x00
>> +#define	REG_AIC_SCR2	0x04
>> +#define	REG_AIC_SCR3	0x08
>> +#define	REG_AIC_SCR4	0x0C
>> +#define	REG_AIC_SCR5	0x10
>
> And like the clk driver, these should all be in the irqchip driver instead
> of a separate header.

Ok, changed.
>
>> +
>> +static void __iomem *aic_base;
>> +static struct irq_domain *aic_domain;
>> +#define MAKE_HWIRQ(irqnum)	(irqnum)
>
> The macro appears to be unused.
removed it.
>
>> +static void nuc970_irq_mask(struct irq_data *d)
>> +{
>> +	if (d->irq < 32)
>> +		__raw_writel(1 << (d->irq), aic_base + REG_AIC_MDCR);
>> +	else
>> +		__raw_writel(1 << (d->irq - 32), aic_base + REG_AIC_MDCRH);
>> +}
>
> writel()
>
> 	Arnd
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
>

Re: [PATCH 4/6] irqchip: add irqchip driver for nuc900

[Arnd Bergmann]

On Tuesday, July 5, 2016 3:47:25 PM CEST Wan Zongshun wrote:
> On 2016年06月29日 23:27, Arnd Bergmann wrote:
> > On Saturday, June 25, 2016 6:37:20 PM CEST Wan Zongshun wrote:
> >> +#define IRQ_WDT             W90X900_IRQ(1)
> >> +#define IRQ_WWDT    W90X900_IRQ(2)
> >> +#define IRQ_LVD             W90X900_IRQ(3)
> >> +#define IRQ_EXT0    W90X900_IRQ(4)
> >> +#define IRQ_EXT1    W90X900_IRQ(5)
> >> +#define IRQ_EXT2    W90X900_IRQ(6)
> >> +#define IRQ_EXT3    W90X900_IRQ(7)
> >> +#define IRQ_EXT4    W90X900_IRQ(8)
> >> +#define IRQ_EXT5    W90X900_IRQ(9)
> >> +#define IRQ_EXT6    W90X900_IRQ(10)
> >
> > I'd suggest dropping the list, the contents are now in the dts.
> 
> Do you think I should put one irqmap header file into this
> /arch/arm/boot/dts/include/dt-bindings folder, or I should removed those 
> irqnumber map anywhere, just hardcode the irqnumber in dts file?

Just hardcode it.

	Arnd

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Re: [PATCH 4/6] irqchip: add irqchip driver for nuc900

[Wan Zongshun]

On 2016年06月29日 23:27, Arnd Bergmann wrote:
> On Saturday, June 25, 2016 6:37:20 PM CEST Wan Zongshun wrote:
>> +#define IRQ_WDT		W90X900_IRQ(1)
>> +#define IRQ_WWDT	W90X900_IRQ(2)
>> +#define IRQ_LVD		W90X900_IRQ(3)
>> +#define IRQ_EXT0	W90X900_IRQ(4)
>> +#define IRQ_EXT1	W90X900_IRQ(5)
>> +#define IRQ_EXT2	W90X900_IRQ(6)
>> +#define IRQ_EXT3	W90X900_IRQ(7)
>> +#define IRQ_EXT4	W90X900_IRQ(8)
>> +#define IRQ_EXT5	W90X900_IRQ(9)
>> +#define IRQ_EXT6	W90X900_IRQ(10)
>
> I'd suggest dropping the list, the contents are now in the dts.

Arnd, I will drop this file later, since old w90x900 plat still need it.
but I will remove the Macros related to nuc970 and avoid nuc970 
interrupt using those Macro.

But I still need hack this irqs.h like below, since here NR_IRQS defined 
and it is need for nuc970 irqchip driver.

#if !defined(CONFIG_SOC_NUC900)
#define NR_IRQS		(IRQ_ADC+1)
#else
#define NR_IRQS		62
#endif

>
>> diff --git a/arch/arm/mach-w90x900/include/mach/nuc970-regs-aic.h b/arch/arm/mach-w90x900/include/mach/nuc970-regs-aic.h
>> new file mode 100644
>> index 0000000..7a77016
>> --- /dev/null
>> +++ b/arch/arm/mach-w90x900/include/mach/nuc970-regs-aic.h
>> @@ -0,0 +1,53 @@
>> +#ifndef __ASM_ARCH_REGS_AIC_H
>> +#define __ASM_ARCH_REGS_AIC_H
>> +
>> +/*NUC970 AIC regs*/
>> +
>> +#define	REG_AIC_SCR1	0x00
>> +#define	REG_AIC_SCR2	0x04
>> +#define	REG_AIC_SCR3	0x08
>> +#define	REG_AIC_SCR4	0x0C
>> +#define	REG_AIC_SCR5	0x10
>
> And like the clk driver, these should all be in the irqchip driver instead
> of a separate header.
>
>> +
>> +static void __iomem *aic_base;
>> +static struct irq_domain *aic_domain;
>> +#define MAKE_HWIRQ(irqnum)	(irqnum)
>
> The macro appears to be unused.
>
>> +static void nuc970_irq_mask(struct irq_data *d)
>> +{
>> +	if (d->irq < 32)
>> +		__raw_writel(1 << (d->irq), aic_base + REG_AIC_MDCR);
>> +	else
>> +		__raw_writel(1 << (d->irq - 32), aic_base + REG_AIC_MDCRH);
>> +}
>
> writel()
>
> 	Arnd
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
>

Re: [PATCH 4/6] irqchip: add irqchip driver for nuc900

[Arnd Bergmann]

On Saturday, July 9, 2016 11:25:19 AM CEST Wan Zongshun wrote:
> On 2016年06月29日 23:27, Arnd Bergmann wrote:
> > On Saturday, June 25, 2016 6:37:20 PM CEST Wan Zongshun wrote:
> >> +#define IRQ_WDT             W90X900_IRQ(1)
> >> +#define IRQ_WWDT    W90X900_IRQ(2)
> >> +#define IRQ_LVD             W90X900_IRQ(3)
> >> +#define IRQ_EXT0    W90X900_IRQ(4)
> >> +#define IRQ_EXT1    W90X900_IRQ(5)
> >> +#define IRQ_EXT2    W90X900_IRQ(6)
> >> +#define IRQ_EXT3    W90X900_IRQ(7)
> >> +#define IRQ_EXT4    W90X900_IRQ(8)
> >> +#define IRQ_EXT5    W90X900_IRQ(9)
> >> +#define IRQ_EXT6    W90X900_IRQ(10)
> >
> > I'd suggest dropping the list, the contents are now in the dts.
> 
> Arnd, I will drop this file later, since old w90x900 plat still need it.

Sure.

> but I will remove the Macros related to nuc970 and avoid nuc970 
> interrupt using those Macro.
> 
> But I still need hack this irqs.h like below, since here NR_IRQS defined 
> and it is need for nuc970 irqchip driver.
> 
> #if !defined(CONFIG_SOC_NUC900)
> #define NR_IRQS         (IRQ_ADC+1)
> #else
> #define NR_IRQS         62
> #endif

Have you considered using CONFIG_SPARSE_IRQ? That would avoid the need
for setting NR_IRQS entirely, but may also require more work elsewhere.

	Arnd
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Re: [PATCH 4/6] irqchip: add irqchip driver for nuc900

[Wan ZongShun]

>
>> but I will remove the Macros related to nuc970 and avoid nuc970
>> interrupt using those Macro.
>>
>> But I still need hack this irqs.h like below, since here NR_IRQS defined
>> and it is need for nuc970 irqchip driver.
>>
>> #if !defined(CONFIG_SOC_NUC900)
>> #define NR_IRQS         (IRQ_ADC+1)
>> #else
>> #define NR_IRQS         62
>> #endif
>
> Have you considered using CONFIG_SPARSE_IRQ? That would avoid the need
> for setting NR_IRQS entirely, but may also require more work elsewhere.

Sure, I will refer to your previous nuc900 series patches for SPARSE
IRQ, now I am waiting for rc1 release, and will send v3 patches.

>
>         Arnd



-- 
---
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www.mcuos.com
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Re: [PATCH 4/6] irqchip: add irqchip driver for nuc900

[Jason Cooper]

Hi Wan,

On Sat, Jun 25, 2016 at 06:37:20PM +0800, Wan Zongshun wrote:
> This patch is to add irqchip driver support for nuc900 plat,
> current this driver only supports nuc970 SoC.
> 
> Signed-off-by: Wan Zongshun <mcuos.com@gmail.com>
> ---
>  arch/arm/mach-w90x900/include/mach/irqs.h          |  69 ++++++++++++++
>  .../mach-w90x900/include/mach/nuc970-regs-aic.h    |  53 +++++++++++
>  drivers/irqchip/Makefile                           |   1 +
>  drivers/irqchip/irq-nuc900.c                       | 104 +++++++++++++++++++++
>  4 files changed, 227 insertions(+)
>  create mode 100644 arch/arm/mach-w90x900/include/mach/nuc970-regs-aic.h
>  create mode 100644 drivers/irqchip/irq-nuc900.c

When you resend after addressing Arnd's comments, please include the
irqchip maintainers in the cc.

thx,

Jason.

[PATCH 3/6] Clocksource: add nuc970 clocksource driver

[Wan Zongshun]

This patch is to add nuc970 clocksource driver support.

Signed-off-by: Wan Zongshun <mcuos.com@gmail.com>
---
 .../mach-w90x900/include/mach/nuc970-regs-timer.h  |  44 +++++
 drivers/clocksource/Kconfig                        |   8 +
 drivers/clocksource/Makefile                       |   1 +
 drivers/clocksource/timer-nuc900.c                 | 207 +++++++++++++++++++++
 4 files changed, 260 insertions(+)
 create mode 100644 arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
 create mode 100644 drivers/clocksource/timer-nuc900.c

diff --git a/arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h b/arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
new file mode 100644
index 0000000..43d7e8b
--- /dev/null
+++ b/arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2016 Wan Zongshun <mcuos.com@gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_REGS_TIMER_H
+#define __ASM_ARCH_REGS_TIMER_H
+
+/* Timer Registers */
+
+#define TMR_BA			0x0
+
+#define REG_TMR_TCSR0		(TMR_BA+0x00)
+#define REG_TMR_TICR0		(TMR_BA+0x04)
+#define REG_TMR_TDR0		(TMR_BA+0x08)
+
+
+#define REG_TMR_TCSR1		(TMR_BA+0x10)
+#define REG_TMR_TICR1		(TMR_BA+0x14)
+#define REG_TMR_TDR1		(TMR_BA+0x18)
+
+
+#define REG_TMR_TCSR2		(TMR_BA+0x20)
+#define REG_TMR_TICR2		(TMR_BA+0x24)
+#define REG_TMR_TDR2		(TMR_BA+0x28)
+
+#define REG_TMR_TCSR3		(TMR_BA+0x30)
+#define REG_TMR_TICR3		(TMR_BA+0x34)
+#define REG_TMR_TDR3		(TMR_BA+0x38)
+
+#define REG_TMR_TCSR4		(TMR_BA+0x40)
+#define REG_TMR_TICR4		(TMR_BA+0x44)
+#define REG_TMR_TDR4		(TMR_BA+0x48)
+
+#define REG_TMR_TISR		(TMR_BA+0x60)
+
+
+#endif /*  __ASM_ARCH_REGS_TIMER_H */
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 47352d2..441c5ee 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -427,4 +427,12 @@ config CLKSRC_ST_LPC
 	  Enable this option to use the Low Power controller timer
 	  as clocksource.
 
+config NUC900_TIMER
+        bool "Clocksource timer for nuc900 platform" if COMPILE_TEST
+        depends on ARM
+        select CLKSRC_OF if OF
+        select CLKSRC_MMIO
+        help
+          Enables the clocksource for the NUC900 platform.
+
 endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 473974f..fcc2cc7 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -67,3 +67,4 @@ obj-$(CONFIG_H8300_TMR16)		+= h8300_timer16.o
 obj-$(CONFIG_H8300_TPU)			+= h8300_tpu.o
 obj-$(CONFIG_CLKSRC_ST_LPC)		+= clksrc_st_lpc.o
 obj-$(CONFIG_X86_NUMACHIP)		+= numachip.o
+obj-$(CONFIG_ARCH_W90X900)		+= timer-nuc900.o
diff --git a/drivers/clocksource/timer-nuc900.c b/drivers/clocksource/timer-nuc900.c
new file mode 100644
index 0000000..6ba025c
--- /dev/null
+++ b/drivers/clocksource/timer-nuc900.c
@@ -0,0 +1,207 @@
+/*
+ * Copyright 2016 Wan Zongshun <mcuos.com@gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/clockchips.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+
+#include <linux/io.h>
+#include <asm/mach/time.h>
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include <mach/mfp.h>
+#include <mach/map.h>
+#include <mach/nuc970-regs-timer.h>
+#include <mach/hardware.h>
+#include <mach/regs-clock.h>
+
+#define RESETINT	0x1f
+#define PERIOD		(0x01 << 27)
+#define ONESHOT		(0x00 << 27)
+#define COUNTEN		(0x01 << 30)
+#define INTEN		(0x01 << 29)
+
+#define TICKS_PER_SEC	100
+/* Divider = prescale + 1 */
+#define PRESCALE	0x63
+
+#define	TDR_SHIFT	24
+#define	TDR_MASK	((1 << TDR_SHIFT) - 1)
+
+static unsigned int timer0_load;
+static void __iomem *tmr_base;
+
+static int nuc970_clockevent_set_oneshot(struct clock_event_device *evt)
+{
+	unsigned int val;
+
+	val = __raw_readl(tmr_base + REG_TMR_TCSR0);
+	val &= ~(0x03 << 27);
+
+	val |= (ONESHOT | COUNTEN | INTEN | PRESCALE);
+
+	__raw_writel(val, tmr_base + REG_TMR_TCSR0);
+	return 0;
+}
+
+static int nuc970_clockevent_set_periodic(struct clock_event_device *evt)
+{
+	unsigned int val;
+
+	val = __raw_readl(tmr_base + REG_TMR_TCSR0);
+	val &= ~(0x03 << 27);
+
+	__raw_writel(timer0_load, tmr_base + REG_TMR_TICR0);
+	val |= (PERIOD | COUNTEN | INTEN | PRESCALE);
+
+	__raw_writel(val, tmr_base + REG_TMR_TCSR0);
+
+	return 0;
+}
+
+static int nuc970_clockevent_setnextevent(unsigned long evt,
+		struct clock_event_device *clk)
+{
+	unsigned int tcsr, tdelta;
+
+	tcsr = __raw_readl(tmr_base + REG_TMR_TCSR0);
+	tdelta = __raw_readl(tmr_base + REG_TMR_TICR0) -
+			     __raw_readl(tmr_base + REG_TMR_TDR0);
+
+	__raw_writel(evt, tmr_base + REG_TMR_TICR0);
+
+	if (!(tcsr & COUNTEN) && ((tdelta > 2) || (tdelta == 0)))
+		__raw_writel(__raw_readl(tmr_base + REG_TMR_TCSR0) | COUNTEN,
+			     tmr_base + REG_TMR_TCSR0);
+
+	return 0;
+}
+
+static int nuc970_clockevent_shutdown(struct clock_event_device *evt)
+{
+	unsigned int val = __raw_readl(tmr_base + REG_TMR_TCSR0) &
+				       ~(0x03 << 27);
+
+	__raw_writel(val, tmr_base + REG_TMR_TCSR0);
+
+	return 0;
+}
+
+static struct clock_event_device nuc970_clockevent_device = {
+	.name			= "nuc970-timer0",
+	.shift			= 32,
+	.features		= CLOCK_EVT_FEAT_PERIODIC |
+				  CLOCK_EVT_FEAT_ONESHOT,
+	.set_state_shutdown	= nuc970_clockevent_shutdown,
+	.set_state_periodic	= nuc970_clockevent_set_periodic,
+	.set_state_oneshot	= nuc970_clockevent_set_oneshot,
+	.set_next_event		= nuc970_clockevent_setnextevent,
+	.tick_resume		= nuc970_clockevent_shutdown,
+	.rating			= 300,
+};
+
+/*IRQ handler for the timer*/
+static irqreturn_t nuc970_timer0_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = &nuc970_clockevent_device;
+
+	__raw_writel(0x01, tmr_base + REG_TMR_TISR);
+
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction nuc970_timer0_irq = {
+	.name		= "nuc970-timer0",
+	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
+	.handler	= nuc970_timer0_interrupt,
+};
+
+static void __init nuc970_clock_source_event_init(void __iomem *base, int irq,
+						  struct clk *clk_timer0,
+						  struct clk *clk_timer1)
+{
+	unsigned int val;
+	unsigned int rate = 0;
+
+	/* Get the timer base address */
+	tmr_base = base;
+
+	/*Clocksource init*/
+	WARN_ON(clk_prepare_enable(clk_timer1));
+
+	__raw_writel(0x00, tmr_base + REG_TMR_TCSR1);
+
+	rate = clk_get_rate(clk_timer1) / (PRESCALE + 1);
+
+	__raw_writel(0xffffffff, tmr_base + REG_TMR_TICR1);
+
+	val = __raw_readl(tmr_base + REG_TMR_TCSR1);
+	val |= (COUNTEN | PERIOD | PRESCALE);
+	__raw_writel(val, tmr_base + REG_TMR_TCSR1);
+
+	clocksource_mmio_init(tmr_base + REG_TMR_TDR1, "nuc970-timer1",
+			      rate, 200, TDR_SHIFT,
+			      clocksource_mmio_readl_down);
+
+	/*Clockevents init*/
+	WARN_ON(clk_prepare_enable(clk_timer0));
+
+	__raw_writel(0x00, tmr_base + REG_TMR_TCSR0);
+
+	rate = clk_get_rate(clk_timer0) / (PRESCALE + 1);
+
+	timer0_load = (rate / TICKS_PER_SEC);
+
+	__raw_writel(RESETINT, tmr_base + REG_TMR_TISR);
+
+	setup_irq(irq, &nuc970_timer0_irq);
+
+	nuc970_clockevent_device.cpumask = cpumask_of(0);
+
+	clockevents_config_and_register(&nuc970_clockevent_device, rate,
+					0xf, 0xffffffff);
+}
+
+static void __init nuc970_timer_of_init(struct device_node *node)
+{
+	struct clk *clk_timer0, *clk_timer1;
+	void __iomem *base;
+	int irq;
+
+	base = of_iomap(node, 0);
+	if (!base)
+		panic("%s: Unable to map timer base\n", node->full_name);
+
+	clk_timer0 = of_clk_get_by_name(node, "timer0");
+	if (IS_ERR(clk_timer0))
+		panic("%s: Unable to get clk_timer0\n", node->full_name);
+
+	clk_timer1 = of_clk_get_by_name(node, "timer1");
+	if (IS_ERR(clk_timer1))
+		panic("%s: Unable to get clk_timer1\n", node->full_name);
+
+	irq = irq_of_parse_and_map(node, 0);
+	if (irq <= 0)
+		panic("%s: Unable to get irq\n", node->full_name);
+
+	nuc970_clock_source_event_init(base, irq, clk_timer0, clk_timer1);
+}
+
+CLOCKSOURCE_OF_DECLARE(nuc970, "nuvoton,tmr", nuc970_timer_of_init);
-- 
2.7.4

Re: [PATCH 3/6] Clocksource: add nuc970 clocksource driver

[Daniel Lezcano]

On 06/25/2016 12:37 PM, Wan Zongshun wrote:
> This patch is to add nuc970 clocksource driver support.

Hi Wan,

add a detailed description of how works this timer and its general 
design. If there is a pointer or a reference to a manual that would be 
awesome.


> Signed-off-by: Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>   .../mach-w90x900/include/mach/nuc970-regs-timer.h  |  44 +++++
>   drivers/clocksource/Kconfig                        |   8 +
>   drivers/clocksource/Makefile                       |   1 +
>   drivers/clocksource/timer-nuc900.c                 | 207 +++++++++++++++++++++
>   4 files changed, 260 insertions(+)
>   create mode 100644 arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
>   create mode 100644 drivers/clocksource/timer-nuc900.c
>
> diff --git a/arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h b/arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
> new file mode 100644
> index 0000000..43d7e8b
> --- /dev/null
> +++ b/arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
> @@ -0,0 +1,44 @@
> +/*
> + * Copyright 2016 Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#ifndef __ASM_ARCH_REGS_TIMER_H
> +#define __ASM_ARCH_REGS_TIMER_H
> +
> +/* Timer Registers */
> +
> +#define TMR_BA			0x0
> +
> +#define REG_TMR_TCSR0		(TMR_BA+0x00)
> +#define REG_TMR_TICR0		(TMR_BA+0x04)
> +#define REG_TMR_TDR0		(TMR_BA+0x08)
> +
> +
> +#define REG_TMR_TCSR1		(TMR_BA+0x10)
> +#define REG_TMR_TICR1		(TMR_BA+0x14)
> +#define REG_TMR_TDR1		(TMR_BA+0x18)
> +
> +
> +#define REG_TMR_TCSR2		(TMR_BA+0x20)
> +#define REG_TMR_TICR2		(TMR_BA+0x24)
> +#define REG_TMR_TDR2		(TMR_BA+0x28)
> +
> +#define REG_TMR_TCSR3		(TMR_BA+0x30)
> +#define REG_TMR_TICR3		(TMR_BA+0x34)
> +#define REG_TMR_TDR3		(TMR_BA+0x38)
> +
> +#define REG_TMR_TCSR4		(TMR_BA+0x40)
> +#define REG_TMR_TICR4		(TMR_BA+0x44)
> +#define REG_TMR_TDR4		(TMR_BA+0x48)
> +
> +#define REG_TMR_TISR		(TMR_BA+0x60)

Are these macros used only in the timer driver or somewhere else ?

> +#endif /*  __ASM_ARCH_REGS_TIMER_H */
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 47352d2..441c5ee 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -427,4 +427,12 @@ config CLKSRC_ST_LPC
>   	  Enable this option to use the Low Power controller timer
>   	  as clocksource.
>
> +config NUC900_TIMER
> +        bool "Clocksource timer for nuc900 platform" if COMPILE_TEST
> +        depends on ARM
> +        select CLKSRC_OF if OF
> +        select CLKSRC_MMIO
> +        help
> +          Enables the clocksource for the NUC900 platform.
> +
>   endmenu
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 473974f..fcc2cc7 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -67,3 +67,4 @@ obj-$(CONFIG_H8300_TMR16)		+= h8300_timer16.o
>   obj-$(CONFIG_H8300_TPU)			+= h8300_tpu.o
>   obj-$(CONFIG_CLKSRC_ST_LPC)		+= clksrc_st_lpc.o
>   obj-$(CONFIG_X86_NUMACHIP)		+= numachip.o
> +obj-$(CONFIG_ARCH_W90X900)		+= timer-nuc900.o

obj-$(CONFIG_NUC900_TIMER)

> diff --git a/drivers/clocksource/timer-nuc900.c b/drivers/clocksource/timer-nuc900.c
> new file mode 100644
> index 0000000..6ba025c
> --- /dev/null
> +++ b/drivers/clocksource/timer-nuc900.c
> @@ -0,0 +1,207 @@
> +/*
> + * Copyright 2016 Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include <linux/init.h>
> +#include <linux/irq.h>
> +#include <linux/interrupt.h>
> +#include <linux/jiffies.h>
> +#include <linux/clockchips.h>
> +#include <linux/types.h>
> +#include <linux/clk.h>
> +
> +#include <linux/io.h>
> +#include <asm/mach/time.h>
> +
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +
> +#include <mach/mfp.h>
> +#include <mach/map.h>
> +#include <mach/nuc970-regs-timer.h>
> +#include <mach/hardware.h>
> +#include <mach/regs-clock.h>

Please do a cleanup with these headers.

> +#define RESETINT	0x1f
> +#define PERIOD		(0x01 << 27)

PERIODIC

> +#define ONESHOT		(0x00 << 27)
> +#define COUNTEN		(0x01 << 30)
> +#define INTEN		(0x01 << 29)
> +
> +#define TICKS_PER_SEC	100
> +/* Divider = prescale + 1 */
> +#define PRESCALE	0x63
> +
> +#define	TDR_SHIFT	24
> +#define	TDR_MASK	((1 << TDR_SHIFT) - 1)
> +
> +static unsigned int timer0_load;
> +static void __iomem *tmr_base;
> +

Structure and container_of:

struct nuc970_clockevents {
	struct clock_event_device clkevt;
	unsigned int timer0_load;
	void __iomem *tmr_base;
};

struct nuc970_clockevents *clkevt_to_nuc970(
	struct clock_event_device *ced)
{
	return container_of(ced, struct nuc970_clockevents, clkevt);
}

> +static int nuc970_clockevent_set_oneshot(struct clock_event_device *evt)
> +{
> +	unsigned int val;

	struct nuc970_clockevents *nuc = clkevt_to_nuc970(evt);

	val = __raw_readl(nuc->tmr_base + REG_TMR_TCSR0);
> +
> +	
> +	val &= ~(0x03 << 27);

(0x03 << 27)  ==> #define BLABLA_MASK (0x03 << 27)

> +
> +	val |= (ONESHOT | COUNTEN | INTEN | PRESCALE);
> +
> +	__raw_writel(val, tmr_base + REG_TMR_TCSR0);
> +	return 0;
> +}
> +
> +static int nuc970_clockevent_set_periodic(struct clock_event_device *evt)
> +{
> +	unsigned int val;
> +
> +	val = __raw_readl(tmr_base + REG_TMR_TCSR0);
> +	val &= ~(0x03 << 27);
> +
> +	__raw_writel(timer0_load, tmr_base + REG_TMR_TICR0);
> +	val |= (PERIOD | COUNTEN | INTEN | PRESCALE);
> +
> +	__raw_writel(val, tmr_base + REG_TMR_TCSR0);
> +
> +	return 0;
> +}

May be you can factour out:

static int nuc970_clockevent_set(bool periodic, void __iomem *addr)
{
	unsigned int val;

	val = __raw_readl(addr + REG_TMR_TCSR0);
	val &= ULTRA_MASK;

	val |= (COUNTEN | INTEN | PRESCALE);
	val |= periodic ? PERIODIC : ONESHOT;

	return __raw_writel(timer0_load, tmr_base + REG_TMR_TICR0);
}

> +
> +static int nuc970_clockevent_setnextevent(unsigned long evt,
> +		struct clock_event_device *clk)
> +{
> +	unsigned int tcsr, tdelta;
> +
> +	tcsr = __raw_readl(tmr_base + REG_TMR_TCSR0);
> +	tdelta = __raw_readl(tmr_base + REG_TMR_TICR0) -
> +			     __raw_readl(tmr_base + REG_TMR_TDR0);
> +
> +	__raw_writel(evt, tmr_base + REG_TMR_TICR0);
> +
> +	if (!(tcsr & COUNTEN) && ((tdelta > 2) || (tdelta == 0)))
> +		__raw_writel(__raw_readl(tmr_base + REG_TMR_TCSR0) | COUNTEN,
> +			     tmr_base + REG_TMR_TCSR0);
> +
> +	return 0;
> +}
> +
> +static int nuc970_clockevent_shutdown(struct clock_event_device *evt)
> +{
> +	unsigned int val = __raw_readl(tmr_base + REG_TMR_TCSR0) &
> +				       ~(0x03 << 27);
> +
> +	__raw_writel(val, tmr_base + REG_TMR_TCSR0);
> +
> +	return 0;
> +}
> +
> +static struct clock_event_device nuc970_clockevent_device = {
> +	.name			= "nuc970-timer0",
> +	.shift			= 32,
> +	.features		= CLOCK_EVT_FEAT_PERIODIC |
> +				  CLOCK_EVT_FEAT_ONESHOT,
> +	.set_state_shutdown	= nuc970_clockevent_shutdown,
> +	.set_state_periodic	= nuc970_clockevent_set_periodic,
> +	.set_state_oneshot	= nuc970_clockevent_set_oneshot,
> +	.set_next_event		= nuc970_clockevent_setnextevent,
> +	.tick_resume		= nuc970_clockevent_shutdown,
> +	.rating			= 300,
> +};
> +
> +/*IRQ handler for the timer*/
> +static irqreturn_t nuc970_timer0_interrupt(int irq, void *dev_id)
> +{
> +	struct clock_event_device *evt = &nuc970_clockevent_device;
> +
> +	__raw_writel(0x01, tmr_base + REG_TMR_TISR);
> +
> +	evt->event_handler(evt);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static struct irqaction nuc970_timer0_irq = {
> +	.name		= "nuc970-timer0",
> +	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
> +	.handler	= nuc970_timer0_interrupt,
> +};
> +
> +static void __init nuc970_clock_source_event_init(void __iomem *base, int irq,
> +						  struct clk *clk_timer0,
> +						  struct clk *clk_timer1)
> +{
> +	unsigned int val;
> +	unsigned int rate = 0;
> +
> +	/* Get the timer base address */
> +	tmr_base = base;
> +
> +	/*Clocksource init*/
> +	WARN_ON(clk_prepare_enable(clk_timer1));

Error check, pr_err, return error

> +
> +	__raw_writel(0x00, tmr_base + REG_TMR_TCSR1);
> +
> +	rate = clk_get_rate(clk_timer1) / (PRESCALE + 1);

	rate check ?

> +
> +	__raw_writel(0xffffffff, tmr_base + REG_TMR_TICR1);
> +
> +	val = __raw_readl(tmr_base + REG_TMR_TCSR1);
> +	val |= (COUNTEN | PERIOD | PRESCALE);
> +	__raw_writel(val, tmr_base + REG_TMR_TCSR1);
> +
> +	clocksource_mmio_init(tmr_base + REG_TMR_TDR1, "nuc970-timer1",
> +			      rate, 200, TDR_SHIFT,
> +			      clocksource_mmio_readl_down);

Error check, rollback previous actions and return error

> +
> +	/*Clockevents init*/
> +	WARN_ON(clk_prepare_enable(clk_timer0));
> +
> +	__raw_writel(0x00, tmr_base + REG_TMR_TCSR0);
> +
> +	rate = clk_get_rate(clk_timer0) / (PRESCALE + 1);
> +
> +	timer0_load = (rate / TICKS_PER_SEC);
> +
> +	__raw_writel(RESETINT, tmr_base + REG_TMR_TISR);
> +
> +	setup_irq(irq, &nuc970_timer0_irq);

s/setup_irq/request_irq/

> +	nuc970_clockevent_device.cpumask = cpumask_of(0);
> +
> +	clockevents_config_and_register(&nuc970_clockevent_device, rate,
> +					0xf, 0xffffffff);

	return 0;

> +}
> +
> +static void __init nuc970_timer_of_init(struct device_node *node)
> +{
> +	struct clk *clk_timer0, *clk_timer1;
> +	void __iomem *base;
> +	int irq;
> +
> +	base = of_iomap(node, 0);
> +	if (!base)
> +		panic("%s: Unable to map timer base\n", node->full_name);

No panic. Error checking, pr_err and then rollback.

I changed the init functions to return an error and will take care of 
changing this driver but meanwhile please handle the errors and rollback.

> +
> +	clk_timer0 = of_clk_get_by_name(node, "timer0");
> +	if (IS_ERR(clk_timer0))
> +		panic("%s: Unable to get clk_timer0\n", node->full_name);
> +
> +	clk_timer1 = of_clk_get_by_name(node, "timer1");
> +	if (IS_ERR(clk_timer1))
> +		panic("%s: Unable to get clk_timer1\n", node->full_name);
> +
> +	irq = irq_of_parse_and_map(node, 0);
> +	if (irq <= 0)
> +		panic("%s: Unable to get irq\n", node->full_name);
> +
> +	nuc970_clock_source_event_init(base, irq, clk_timer0, clk_timer1);
> +}
> +
> +CLOCKSOURCE_OF_DECLARE(nuc970, "nuvoton,tmr", nuc970_timer_of_init);
>

Thanks !

   -- Daniel


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Re: [PATCH 3/6] Clocksource: add nuc970 clocksource driver

[Wan Zongshun]

On 2016年06月28日 03:46, Daniel Lezcano wrote:
> On 06/25/2016 12:37 PM, Wan Zongshun wrote:
>> This patch is to add nuc970 clocksource driver support.
>
> Hi Wan,
>
> add a detailed description of how works this timer and its general
> design. If there is a pointer or a reference to a manual that would be
> awesome.

Daniel,

I add a document link to you, and I will update this link in my patch later.

https://github.com/zswan/nuc900-document/blob/master/NUC970_TechnicalReferenceManual_EN_Rev1.30.pdf

>
>
>> Signed-off-by: Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>>   .../mach-w90x900/include/mach/nuc970-regs-timer.h  |  44 +++++
>>   drivers/clocksource/Kconfig                        |   8 +
>>   drivers/clocksource/Makefile                       |   1 +
>>   drivers/clocksource/timer-nuc900.c                 | 207
>> +++++++++++++++++++++
>>   4 files changed, 260 insertions(+)
>>   create mode 100644
>> arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
>>   create mode 100644 drivers/clocksource/timer-nuc900.c
>>
>> diff --git a/arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
>> b/arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
>> new file mode 100644
>> index 0000000..43d7e8b
>> --- /dev/null
>> +++ b/arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
>> @@ -0,0 +1,44 @@
>> +/*
>> + * Copyright 2016 Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> + *
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>> +
>> +#ifndef __ASM_ARCH_REGS_TIMER_H
>> +#define __ASM_ARCH_REGS_TIMER_H
>> +
>> +/* Timer Registers */
>> +
>> +#define TMR_BA            0x0
>> +
>> +#define REG_TMR_TCSR0        (TMR_BA+0x00)
>> +#define REG_TMR_TICR0        (TMR_BA+0x04)
>> +#define REG_TMR_TDR0        (TMR_BA+0x08)
>> +
>> +
>> +#define REG_TMR_TCSR1        (TMR_BA+0x10)
>> +#define REG_TMR_TICR1        (TMR_BA+0x14)
>> +#define REG_TMR_TDR1        (TMR_BA+0x18)
>> +
>> +
>> +#define REG_TMR_TCSR2        (TMR_BA+0x20)
>> +#define REG_TMR_TICR2        (TMR_BA+0x24)
>> +#define REG_TMR_TDR2        (TMR_BA+0x28)
>> +
>> +#define REG_TMR_TCSR3        (TMR_BA+0x30)
>> +#define REG_TMR_TICR3        (TMR_BA+0x34)
>> +#define REG_TMR_TDR3        (TMR_BA+0x38)
>> +
>> +#define REG_TMR_TCSR4        (TMR_BA+0x40)
>> +#define REG_TMR_TICR4        (TMR_BA+0x44)
>> +#define REG_TMR_TDR4        (TMR_BA+0x48)
>> +
>> +#define REG_TMR_TISR        (TMR_BA+0x60)
>
> Are these macros used only in the timer driver or somewhere else ?

They are using by the timer driver, and I will try to move 
mach-w90x900/include/mach/nuc970-regs-timer.h out of mach/ folder.

Do you think I should move those macros into this driver file?

>
>> +#endif /*  __ASM_ARCH_REGS_TIMER_H */
>> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
>> index 47352d2..441c5ee 100644
>> --- a/drivers/clocksource/Kconfig
>> +++ b/drivers/clocksource/Kconfig
>> @@ -427,4 +427,12 @@ config CLKSRC_ST_LPC
>>         Enable this option to use the Low Power controller timer
>>         as clocksource.
>>
>> +config NUC900_TIMER
>> +        bool "Clocksource timer for nuc900 platform" if COMPILE_TEST
>> +        depends on ARM
>> +        select CLKSRC_OF if OF
>> +        select CLKSRC_MMIO
>> +        help
>> +          Enables the clocksource for the NUC900 platform.
>> +
>>   endmenu
>> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
>> index 473974f..fcc2cc7 100644
>> --- a/drivers/clocksource/Makefile
>> +++ b/drivers/clocksource/Makefile
>> @@ -67,3 +67,4 @@ obj-$(CONFIG_H8300_TMR16)        += h8300_timer16.o
>>   obj-$(CONFIG_H8300_TPU)            += h8300_tpu.o
>>   obj-$(CONFIG_CLKSRC_ST_LPC)        += clksrc_st_lpc.o
>>   obj-$(CONFIG_X86_NUMACHIP)        += numachip.o
>> +obj-$(CONFIG_ARCH_W90X900)        += timer-nuc900.o
>
> obj-$(CONFIG_NUC900_TIMER)

Sure, changed.
>
>> diff --git a/drivers/clocksource/timer-nuc900.c
>> b/drivers/clocksource/timer-nuc900.c
>> new file mode 100644
>> index 0000000..6ba025c
>> --- /dev/null
>> +++ b/drivers/clocksource/timer-nuc900.c
>> @@ -0,0 +1,207 @@
>> +/*
>> + * Copyright 2016 Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> + *
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>> +
>> +#include <linux/init.h>
>> +#include <linux/irq.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/jiffies.h>
>> +#include <linux/clockchips.h>
>> +#include <linux/types.h>
>> +#include <linux/clk.h>
>> +
>> +#include <linux/io.h>
>> +#include <asm/mach/time.h>
>> +
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_irq.h>
>> +
>> +#include <mach/mfp.h>
>> +#include <mach/map.h>
>> +#include <mach/nuc970-regs-timer.h>
>> +#include <mach/hardware.h>
>> +#include <mach/regs-clock.h>
>
> Please do a cleanup with these headers.

Ok.

>
>> +#define RESETINT    0x1f
>> +#define PERIOD        (0x01 << 27)
>
> PERIODIC

Ok.
>
>> +#define ONESHOT        (0x00 << 27)
>> +#define COUNTEN        (0x01 << 30)
>> +#define INTEN        (0x01 << 29)
>> +
>> +#define TICKS_PER_SEC    100
>> +/* Divider = prescale + 1 */
>> +#define PRESCALE    0x63
>> +
>> +#define    TDR_SHIFT    24
>> +#define    TDR_MASK    ((1 << TDR_SHIFT) - 1)
>> +
>> +static unsigned int timer0_load;
>> +static void __iomem *tmr_base;
>> +
>
> Structure and container_of:
>
> struct nuc970_clockevents {
>      struct clock_event_device clkevt;
>      unsigned int timer0_load;
>      void __iomem *tmr_base;
> };
>
> struct nuc970_clockevents *clkevt_to_nuc970(
>      struct clock_event_device *ced)
> {
>      return container_of(ced, struct nuc970_clockevents, clkevt);
> }

Looks better, thanks.

>
>> +static int nuc970_clockevent_set_oneshot(struct clock_event_device *evt)
>> +{
>> +    unsigned int val;
>
>      struct nuc970_clockevents *nuc = clkevt_to_nuc970(evt);
>
>      val = __raw_readl(nuc->tmr_base + REG_TMR_TCSR0);
>> +
>> +
>> +    val &= ~(0x03 << 27);
>
> (0x03 << 27)  ==> #define BLABLA_MASK (0x03 << 27)
Ok.
>
>> +
>> +    val |= (ONESHOT | COUNTEN | INTEN | PRESCALE);
>> +
>> +    __raw_writel(val, tmr_base + REG_TMR_TCSR0);
>> +    return 0;
>> +}
>> +
>> +static int nuc970_clockevent_set_periodic(struct clock_event_device
>> *evt)
>> +{
>> +    unsigned int val;
>> +
>> +    val = __raw_readl(tmr_base + REG_TMR_TCSR0);
>> +    val &= ~(0x03 << 27);
>> +
>> +    __raw_writel(timer0_load, tmr_base + REG_TMR_TICR0);
>> +    val |= (PERIOD | COUNTEN | INTEN | PRESCALE);
>> +
>> +    __raw_writel(val, tmr_base + REG_TMR_TCSR0);
>> +
>> +    return 0;
>> +}
>
> May be you can factour out:
>
> static int nuc970_clockevent_set(bool periodic, void __iomem *addr)
> {
>      unsigned int val;
>
>      val = __raw_readl(addr + REG_TMR_TCSR0);
>      val &= ULTRA_MASK;
>
>      val |= (COUNTEN | INTEN | PRESCALE);
>      val |= periodic ? PERIODIC : ONESHOT;
>
>      return __raw_writel(timer0_load, tmr_base + REG_TMR_TICR0);
> }

Ok, will change.

>
>> +
>> +static int nuc970_clockevent_setnextevent(unsigned long evt,
>> +        struct clock_event_device *clk)
>> +{
>> +    unsigned int tcsr, tdelta;
>> +
>> +    tcsr = __raw_readl(tmr_base + REG_TMR_TCSR0);
>> +    tdelta = __raw_readl(tmr_base + REG_TMR_TICR0) -
>> +                 __raw_readl(tmr_base + REG_TMR_TDR0);
>> +
>> +    __raw_writel(evt, tmr_base + REG_TMR_TICR0);
>> +
>> +    if (!(tcsr & COUNTEN) && ((tdelta > 2) || (tdelta == 0)))
>> +        __raw_writel(__raw_readl(tmr_base + REG_TMR_TCSR0) | COUNTEN,
>> +                 tmr_base + REG_TMR_TCSR0);
>> +
>> +    return 0;
>> +}
>> +
>> +static int nuc970_clockevent_shutdown(struct clock_event_device *evt)
>> +{
>> +    unsigned int val = __raw_readl(tmr_base + REG_TMR_TCSR0) &
>> +                       ~(0x03 << 27);
>> +
>> +    __raw_writel(val, tmr_base + REG_TMR_TCSR0);
>> +
>> +    return 0;
>> +}
>> +
>> +static struct clock_event_device nuc970_clockevent_device = {
>> +    .name            = "nuc970-timer0",
>> +    .shift            = 32,
>> +    .features        = CLOCK_EVT_FEAT_PERIODIC |
>> +                  CLOCK_EVT_FEAT_ONESHOT,
>> +    .set_state_shutdown    = nuc970_clockevent_shutdown,
>> +    .set_state_periodic    = nuc970_clockevent_set_periodic,
>> +    .set_state_oneshot    = nuc970_clockevent_set_oneshot,
>> +    .set_next_event        = nuc970_clockevent_setnextevent,
>> +    .tick_resume        = nuc970_clockevent_shutdown,
>> +    .rating            = 300,
>> +};
>> +
>> +/*IRQ handler for the timer*/
>> +static irqreturn_t nuc970_timer0_interrupt(int irq, void *dev_id)
>> +{
>> +    struct clock_event_device *evt = &nuc970_clockevent_device;
>> +
>> +    __raw_writel(0x01, tmr_base + REG_TMR_TISR);
>> +
>> +    evt->event_handler(evt);
>> +
>> +    return IRQ_HANDLED;
>> +}
>> +
>> +static struct irqaction nuc970_timer0_irq = {
>> +    .name        = "nuc970-timer0",
>> +    .flags        = IRQF_TIMER | IRQF_IRQPOLL,
>> +    .handler    = nuc970_timer0_interrupt,
>> +};
>> +
>> +static void __init nuc970_clock_source_event_init(void __iomem *base,
>> int irq,
>> +                          struct clk *clk_timer0,
>> +                          struct clk *clk_timer1)
>> +{
>> +    unsigned int val;
>> +    unsigned int rate = 0;
>> +
>> +    /* Get the timer base address */
>> +    tmr_base = base;
>> +
>> +    /*Clocksource init*/
>> +    WARN_ON(clk_prepare_enable(clk_timer1));
>
> Error check, pr_err, return error

Ok, changed.

>
>> +
>> +    __raw_writel(0x00, tmr_base + REG_TMR_TCSR1);
>> +
>> +    rate = clk_get_rate(clk_timer1) / (PRESCALE + 1);
>
>      rate check ?
>
>> +
>> +    __raw_writel(0xffffffff, tmr_base + REG_TMR_TICR1);
>> +
>> +    val = __raw_readl(tmr_base + REG_TMR_TCSR1);
>> +    val |= (COUNTEN | PERIOD | PRESCALE);
>> +    __raw_writel(val, tmr_base + REG_TMR_TCSR1);
>> +
>> +    clocksource_mmio_init(tmr_base + REG_TMR_TDR1, "nuc970-timer1",
>> +                  rate, 200, TDR_SHIFT,
>> +                  clocksource_mmio_readl_down);
>
> Error check, rollback previous actions and return error
>
>> +
>> +    /*Clockevents init*/
>> +    WARN_ON(clk_prepare_enable(clk_timer0));
>> +
>> +    __raw_writel(0x00, tmr_base + REG_TMR_TCSR0);
>> +
>> +    rate = clk_get_rate(clk_timer0) / (PRESCALE + 1);
>> +
>> +    timer0_load = (rate / TICKS_PER_SEC);
>> +
>> +    __raw_writel(RESETINT, tmr_base + REG_TMR_TISR);
>> +
>> +    setup_irq(irq, &nuc970_timer0_irq);
>
> s/setup_irq/request_irq/

Do you think I should use request_irq instead of setup_irq?

>
>> +    nuc970_clockevent_device.cpumask = cpumask_of(0);
>> +
>> +    clockevents_config_and_register(&nuc970_clockevent_device, rate,
>> +                    0xf, 0xffffffff);
>
>      return 0;
>
>> +}
>> +
>> +static void __init nuc970_timer_of_init(struct device_node *node)
>> +{
>> +    struct clk *clk_timer0, *clk_timer1;
>> +    void __iomem *base;
>> +    int irq;
>> +
>> +    base = of_iomap(node, 0);
>> +    if (!base)
>> +        panic("%s: Unable to map timer base\n", node->full_name);
>
> No panic. Error checking, pr_err and then rollback.
>
> I changed the init functions to return an error and will take care of
> changing this driver but meanwhile please handle the errors and rollback.

Ok.
>
>> +
>> +    clk_timer0 = of_clk_get_by_name(node, "timer0");
>> +    if (IS_ERR(clk_timer0))
>> +        panic("%s: Unable to get clk_timer0\n", node->full_name);
>> +
>> +    clk_timer1 = of_clk_get_by_name(node, "timer1");
>> +    if (IS_ERR(clk_timer1))
>> +        panic("%s: Unable to get clk_timer1\n", node->full_name);
>> +
>> +    irq = irq_of_parse_and_map(node, 0);
>> +    if (irq <= 0)
>> +        panic("%s: Unable to get irq\n", node->full_name);
>> +
>> +    nuc970_clock_source_event_init(base, irq, clk_timer0, clk_timer1);
>> +}
>> +
>> +CLOCKSOURCE_OF_DECLARE(nuc970, "nuvoton,tmr", nuc970_timer_of_init);
>>
>
> Thanks !
>
>    -- Daniel
>
>
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Re: [PATCH 3/6] Clocksource: add nuc970 clocksource driver

[Daniel Lezcano]

On 07/05/2016 10:21 AM, Wan Zongshun wrote:

[ ... ]

>>> +    setup_irq(irq, &nuc970_timer0_irq);
>>
>> s/setup_irq/request_irq/
> 
> Do you think I should use request_irq instead of setup_irq?

Yes.


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Re: [PATCH 3/6] Clocksource: add nuc970 clocksource driver

[Arnd Bergmann]

On Saturday, June 25, 2016 6:37:19 PM CEST Wan Zongshun wrote:
> This patch is to add nuc970 clocksource driver support.
> 
> Signed-off-by: Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  .../mach-w90x900/include/mach/nuc970-regs-timer.h  |  44 +++++
>  drivers/clocksource/Kconfig                        |   8 +
>  drivers/clocksource/Makefile                       |   1 +
>  drivers/clocksource/timer-nuc900.c                 | 207 +++++++++++++++++++++
>  4 files changed, 260 insertions(+)
>  create mode 100644 arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
>  create mode 100644 drivers/clocksource/timer-nuc900.c
> 
> diff --git a/arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h b/arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
> new file mode 100644
> index 0000000..43d7e8b
> --- /dev/null
> +++ b/arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h

Please move the contents of the header file into the driver. We try to not
have any new mach/*.h headers.

> +
> +static unsigned int timer0_load;
> +static void __iomem *tmr_base;
> +
> +static int nuc970_clockevent_set_oneshot(struct clock_event_device *evt)
> +{
> +	unsigned int val;
> +
> +	val = __raw_readl(tmr_base + REG_TMR_TCSR0);
> +	val &= ~(0x03 << 27);
> +
> +	val |= (ONESHOT | COUNTEN | INTEN | PRESCALE);
> +
> +	__raw_writel(val, tmr_base + REG_TMR_TCSR0);
> +	return 0;
> +}
> +

writel() instead of __raw_writel()

	Arnd
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Re: [PATCH 3/6] Clocksource: add nuc970 clocksource driver

[Daniel Lezcano]

On 06/29/2016 05:25 PM, Arnd Bergmann wrote:
> On Saturday, June 25, 2016 6:37:19 PM CEST Wan Zongshun wrote:
>> This patch is to add nuc970 clocksource driver support.
>>
>> Signed-off-by: Wan Zongshun <mcuos.com@gmail.com>
>> ---
>>   .../mach-w90x900/include/mach/nuc970-regs-timer.h  |  44 +++++
>>   drivers/clocksource/Kconfig                        |   8 +
>>   drivers/clocksource/Makefile                       |   1 +
>>   drivers/clocksource/timer-nuc900.c                 | 207 +++++++++++++++++++++
>>   4 files changed, 260 insertions(+)
>>   create mode 100644 arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
>>   create mode 100644 drivers/clocksource/timer-nuc900.c
>>
>> diff --git a/arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h b/arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
>> new file mode 100644
>> index 0000000..43d7e8b
>> --- /dev/null
>> +++ b/arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
>
> Please move the contents of the header file into the driver. We try to not
> have any new mach/*.h headers.
>
>> +
>> +static unsigned int timer0_load;
>> +static void __iomem *tmr_base;
>> +
>> +static int nuc970_clockevent_set_oneshot(struct clock_event_device *evt)
>> +{
>> +	unsigned int val;
>> +
>> +	val = __raw_readl(tmr_base + REG_TMR_TCSR0);
>> +	val &= ~(0x03 << 27);
>> +
>> +	val |= (ONESHOT | COUNTEN | INTEN | PRESCALE);
>> +
>> +	__raw_writel(val, tmr_base + REG_TMR_TCSR0);
>> +	return 0;
>> +}
>> +
>
> writel() instead of __raw_writel()

Wan Zongshun,

FYI : https://lkml.org/lkml/2015/12/18/422

Not sure it does a noticeable difference on arm926.

Thanks Arnd for the clarification.

   -- Daniel


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Re: [PATCH 3/6] Clocksource: add nuc970 clocksource driver

[Wan Zongshun]

On 2016年06月29日 23:25, Arnd Bergmann wrote:
> On Saturday, June 25, 2016 6:37:19 PM CEST Wan Zongshun wrote:
>> This patch is to add nuc970 clocksource driver support.
>>
>> Signed-off-by: Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>>   .../mach-w90x900/include/mach/nuc970-regs-timer.h  |  44 +++++
>>   drivers/clocksource/Kconfig                        |   8 +
>>   drivers/clocksource/Makefile                       |   1 +
>>   drivers/clocksource/timer-nuc900.c                 | 207 +++++++++++++++++++++
>>   4 files changed, 260 insertions(+)
>>   create mode 100644 arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
>>   create mode 100644 drivers/clocksource/timer-nuc900.c
>>
>> diff --git a/arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h b/arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
>> new file mode 100644
>> index 0000000..43d7e8b
>> --- /dev/null
>> +++ b/arch/arm/mach-w90x900/include/mach/nuc970-regs-timer.h
>
> Please move the contents of the header file into the driver. We try to not
> have any new mach/*.h headers.

Ok, done.

>
>> +
>> +static unsigned int timer0_load;
>> +static void __iomem *tmr_base;
>> +
>> +static int nuc970_clockevent_set_oneshot(struct clock_event_device *evt)
>> +{
>> +	unsigned int val;
>> +
>> +	val = __raw_readl(tmr_base + REG_TMR_TCSR0);
>> +	val &= ~(0x03 << 27);
>> +
>> +	val |= (ONESHOT | COUNTEN | INTEN | PRESCALE);
>> +
>> +	__raw_writel(val, tmr_base + REG_TMR_TCSR0);
>> +	return 0;
>> +}
>> +
>
> writel() instead of __raw_writel()

Ok, so this change will apply to all drivers.

>
> 	Arnd
>
> _______________________________________________
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> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
>
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[PATCH 5/6] clk: add Clock driver for nuc970

[Wan Zongshun]

Signed-off-by: Wan Zongshun <mcuos.com@gmail.com>
---
 drivers/clk/Makefile            |   1 +
 drivers/clk/nuc900/Makefile     |   6 +
 drivers/clk/nuc900/clk-apll.c   | 168 ++++++++
 drivers/clk/nuc900/clk-ccf.h    |  53 +++
 drivers/clk/nuc900/clk-nuc970.c | 920 ++++++++++++++++++++++++++++++++++++++++
 drivers/clk/nuc900/clk-upll.c   |  83 ++++
 6 files changed, 1231 insertions(+)
 create mode 100644 drivers/clk/nuc900/Makefile
 create mode 100644 drivers/clk/nuc900/clk-apll.c
 create mode 100644 drivers/clk/nuc900/clk-ccf.h
 create mode 100644 drivers/clk/nuc900/clk-nuc970.c
 create mode 100644 drivers/clk/nuc900/clk-upll.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index dcc5e69..042377d 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -88,3 +88,4 @@ obj-$(CONFIG_ARCH_ZX)			+= zte/
 obj-$(CONFIG_ARCH_ZYNQ)			+= zynq/
 obj-$(CONFIG_H8300)		+= h8300/
 obj-$(CONFIG_ARC_PLAT_AXS10X)		+= axs10x/
+obj-$(CONFIG_ARCH_W90X900)		+= nuc900/
diff --git a/drivers/clk/nuc900/Makefile b/drivers/clk/nuc900/Makefile
new file mode 100644
index 0000000..a6785ab
--- /dev/null
+++ b/drivers/clk/nuc900/Makefile
@@ -0,0 +1,6 @@
+#
+# Makefile for nuvoton specific clk
+#
+
+obj-$(CONFIG_SOC_NUC970) += clk-apll.o clk-upll.o clk-nuc970.o
+
diff --git a/drivers/clk/nuc900/clk-apll.c b/drivers/clk/nuc900/clk-apll.c
new file mode 100644
index 0000000..4e1c202
--- /dev/null
+++ b/drivers/clk/nuc900/clk-apll.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright 2016 Wan Zongshun <mcuos.com@gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+
+#include "clk-ccf.h"
+
+struct clk_apll {
+	struct clk_hw	hw;
+	void __iomem	*base;
+};
+
+#define to_clk_apll(clk) (container_of(clk, struct clk_apll, clk))
+
+static int clk_apll_set_rate(struct clk_hw *hw, unsigned long rate,
+			     unsigned long parent_rate)
+{
+	struct clk_apll *pll = to_clk_apll(hw);
+	unsigned long reg;
+
+	reg = readl(pll->base) & ~0x0FFFFFFF;
+
+	switch (rate) {
+	/*usbh*/
+	case 96000000:
+		reg |= 0x8027;
+		break;
+	/*i2s*/
+	case 98400000:
+		reg |= 0x8028;
+		break;
+	/*i2s*/
+	case 169500000:
+		reg |= 0x21f0;
+		break;
+	/*system default, 264MHz*/
+	case 264000000:
+		reg |= 0x15;
+		break;
+	case 300000000:
+		reg |= 0x18;
+		break;
+	default:
+		reg |= 0x15;
+		break;
+	}
+
+	writel(reg, pll->base);
+
+	return 0;
+}
+
+static unsigned long clk_apll_recalc_rate(struct clk_hw *hw,
+					  unsigned long parent_rate)
+{
+	struct clk_apll *pll = to_clk_apll(hw);
+	unsigned long reg = readl(pll->base) & 0x0FFFFFFF;
+	unsigned long rate;
+
+	if (parent_rate != 12000000)
+		return 0;
+
+	switch (reg) {
+	/*system default, 264MHz*/
+	case 0x15:
+		rate = 264000000;
+		break;
+	case 0x18:
+		rate = 300000000;
+		break;
+	/*usbh*/
+	case 0x8027:
+		rate = 96000000;
+		break;
+	/*i2s*/
+	case 0x8028:
+		rate = 98400000;
+		break;
+	/*i2s*/
+	case 0x21f0:
+		rate = 169500000;
+		break;
+	default:
+		rate = 264000000;
+		break;
+	}
+
+	return rate;
+}
+
+static long clk_apll_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
+{
+	return rate;
+}
+
+static int clk_apll_enable(struct clk_hw *hw)
+{
+	struct clk_apll *pll = to_clk_apll(hw);
+	unsigned long val;
+
+	val = __raw_readl(pll->base);
+	val &= ~0x10000000;
+	val |= 0x40000000;
+	__raw_writel(val, pll->base);
+
+	return 0;
+}
+
+static void clk_apll_disable(struct clk_hw *hw)
+{
+	struct clk_apll *pll = to_clk_apll(hw);
+	unsigned long val;
+
+	val = __raw_readl(pll->base);
+	val |= 0x10000000;
+	val &= ~0x40000000;
+	__raw_writel(val, pll->base);
+}
+
+static struct clk_ops clk_apll_ops = {
+	.recalc_rate = clk_apll_recalc_rate,
+	.enable = clk_apll_enable,
+	.disable = clk_apll_disable,
+	.set_rate = clk_apll_set_rate,
+	.round_rate = clk_apll_round_rate,
+};
+
+struct clk *nuc970_clk_apll(const char *name, const char *parent,
+			    void __iomem *base)
+{
+	struct clk_apll *pll;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	pll = kmalloc(sizeof(*pll), GFP_KERNEL);
+	if (!pll)
+		return ERR_PTR(-ENOMEM);
+
+	pll->base = base;
+
+	init.name = name;
+	init.ops = &clk_apll_ops;
+	init.flags = 0;
+	init.parent_names = &parent;
+	init.num_parents = 1;
+
+	pll->hw.init = &init;
+
+	clk = clk_register(NULL, &pll->hw);
+	if (IS_ERR(clk))
+		kfree(pll);
+
+	return clk;
+}
diff --git a/drivers/clk/nuc900/clk-ccf.h b/drivers/clk/nuc900/clk-ccf.h
new file mode 100644
index 0000000..2808933
--- /dev/null
+++ b/drivers/clk/nuc900/clk-ccf.h
@@ -0,0 +1,53 @@
+#ifndef __MACH_NUC970_CLK_H
+#define __MACH_NUC970_CLK_H
+
+#include <linux/spinlock.h>
+#include <linux/clk-provider.h>
+
+static spinlock_t nuc970_lock;
+
+extern struct clk *nuc970_clk_apll(const char *name, const char *parent,
+				   void __iomem *base);
+extern struct clk *nuc970_clk_upll(const char *name, const char *parent,
+				   void __iomem *base);
+
+static inline struct clk *nuc970_clk_fixed(const char *name, int rate)
+{
+	return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
+}
+
+static inline struct clk *nuc970_clk_mux(const char *name, void __iomem *reg,
+					 u8 shift, u8 width,
+					 const char * const *parents,
+					 int num_parents)
+{
+	return clk_register_mux(NULL, name, parents, num_parents, 0, reg, shift,
+				width, 0, &nuc970_lock);
+}
+
+static inline struct clk *nuc970_clk_divider(const char *name,
+					     const char *parent,
+					     void __iomem *reg, u8 shift,
+					     u8 width)
+{
+	return clk_register_divider(NULL, name, parent, 0,
+				    reg, shift, width, 0, &nuc970_lock);
+}
+
+static inline struct clk *nuc970_clk_fixed_factor(const char *name,
+						  const char *parent,
+						  unsigned int mult,
+						  unsigned int div)
+{
+	return clk_register_fixed_factor(NULL, name, parent,
+					 CLK_SET_RATE_PARENT, mult, div);
+}
+
+static inline struct clk *nuc970_clk_gate(const char *name, const char *parent,
+					  void __iomem *reg, u8 shift)
+{
+	return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+				 shift, 0, &nuc970_lock);
+}
+
+#endif
diff --git a/drivers/clk/nuc900/clk-nuc970.c b/drivers/clk/nuc900/clk-nuc970.c
new file mode 100644
index 0000000..a4faf0d
--- /dev/null
+++ b/drivers/clk/nuc900/clk-nuc970.c
@@ -0,0 +1,920 @@
+/*
+ * Copyright 2016 Wan Zongshun <mcuos.com@gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clk-provider.h>
+#include <linux/spinlock.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <dt-bindings/clock/nuc970-clock.h>
+#include "clk-ccf.h"
+
+/* Clock Control Registers  */
+static void __iomem *clkctrl;
+#define CLK_BA clkctrl
+
+#define REG_CLK_PMCON	(CLK_BA + 0x000)
+#define REG_CLK_HCLKEN	(CLK_BA + 0x010)
+#define REG_CLK_PCLKEN0	(CLK_BA + 0x018)
+#define REG_CLK_PCLKEN1	(CLK_BA + 0x01C)
+#define REG_CLK_DIV0	(CLK_BA + 0x020)
+#define REG_CLK_DIV1	(CLK_BA + 0x024)
+#define REG_CLK_DIV2	(CLK_BA + 0x028)
+#define REG_CLK_DIV3	(CLK_BA + 0x02C)
+#define REG_CLK_DIV4	(CLK_BA + 0x030)
+#define REG_CLK_DIV5	(CLK_BA + 0x034)
+#define REG_CLK_DIV6	(CLK_BA + 0x038)
+#define REG_CLK_DIV7	(CLK_BA + 0x03C)
+#define REG_CLK_DIV8	(CLK_BA + 0x040)
+#define REG_CLK_DIV9	(CLK_BA + 0x044)
+#define REG_CLK_APLLCON	(CLK_BA + 0x060)
+#define REG_CLK_UPLLCON	(CLK_BA + 0x064)
+
+static const char *const sys_sel_clks[] = { "xin",
+					    "dummy",
+					    "apll",
+					    "upll" };
+
+static const char *const lcd_sel_clks[] = { "xin",
+					    "dummy",
+					    "lcd_aplldiv",
+					    "lcd_uplldiv" };
+
+static const char *const audio_sel_clks[] = { "xin",
+					      "dummy",
+					      "audio_aplldiv",
+					      "audio_uplldiv" };
+
+static const char *const usb_sel_clks[] = { "xin",
+					    "dummy",
+					    "usb_aplldiv",
+					    "usb_uplldiv" };
+
+static const char *const adc_sel_clks[] = { "xin",
+					    "dummy",
+					    "adc_aplldiv",
+					    "adc_uplldiv" };
+
+static const char *const cap_sel_clks[] = { "xin",
+					    "dummy",
+					    "cap_aplldiv",
+					    "cap_uplldiv" };
+
+static const char *const sdh_sel_clks[] = { "xin",
+					    "dummy",
+					    "sdh_aplldiv",
+					    "sdh_uplldiv" };
+
+static const char *const emmc_sel_clks[] = { "xin",
+					     "dummy",
+					     "emmc_aplldiv",
+					     "emmc_uplldiv" };
+
+static const char *const uart0_sel_clks[] = { "xin",
+					      "dummy",
+					      "uart0_aplldiv",
+					      "uart0_uplldiv" };
+
+static const char *const uart1_sel_clks[] = { "xin",
+					      "dummy",
+					      "uart1_aplldiv",
+					      "uart1_uplldiv" };
+
+static const char *const uart2_sel_clks[] = { "xin",
+					      "dummy",
+					      "uart2_aplldiv",
+					      "uart2_uplldiv" };
+
+static const char *const uart3_sel_clks[] = { "xin",
+					      "dummy",
+					      "uart3_aplldiv",
+					      "uart3_uplldiv" };
+
+static const char *const uart4_sel_clks[] = { "xin",
+					      "dummy",
+					      "uart4_aplldiv",
+					      "uart4_uplldiv" };
+
+static const char *const uart5_sel_clks[] = { "xin",
+					      "dummy",
+					      "uart5_aplldiv",
+					      "uart5_uplldiv" };
+
+static const char *const uart6_sel_clks[] = { "xin",
+					      "dummy",
+					      "uart6_aplldiv",
+					      "uart6_uplldiv" };
+
+static const char *const uart7_sel_clks[] = { "xin",
+					      "dummy",
+					      "uart7_aplldiv",
+					      "uart7_uplldiv" };
+
+static const char *const uart8_sel_clks[] = { "xin",
+					      "dummy",
+					      "uart8_aplldiv",
+					      "uart8_uplldiv" };
+
+static const char *const uart9_sel_clks[] = { "xin",
+					      "dummy",
+					      "uart9_aplldiv",
+					      "uart9_uplldiv" };
+
+static const char *const uart10_sel_clks[] = { "xin",
+					       "dummy",
+					       "uart10_aplldiv",
+					       "uart10_uplldiv" };
+
+static const char *const system_sel_clks[] = { "xin",
+					       "dummy",
+					       "system_aplldiv",
+					       "system_uplldiv" };
+
+static const char *const gpio_sel_clks[] = { "xin", "xin32k"};
+static const char *const kpi_sel_clks[] = { "xin", "xin32k"};
+static const char *const etimer_sel_clks[] = { "xin",
+					       "pclk_div",
+					      "pclk4096_div",
+					      "xin32k" };
+
+static const char *const wwdt_sel_clks[] = { "xin",
+					     "xin128_div",
+					     "pclk4096_div",
+					     "xin32k" };
+
+static struct clk *clk[NUC970_CLK_MAX];
+static struct clk_onecell_data clk_data;
+
+static void __init nuc970_clocks_init(struct device_node *np)
+{
+	int i;
+
+	clkctrl = of_iomap(np, 0);
+	WARN_ON(!clkctrl);
+
+	/* source */
+	clk[XIN]	= nuc970_clk_fixed("xin", 12000000);
+	clk[XIN32K]	= nuc970_clk_fixed("xin32k", 32768);
+	clk[APLL]	= nuc970_clk_apll("apll", "xin", REG_CLK_APLLCON);
+	clk[UPLL]	= nuc970_clk_upll("upll", "xin", REG_CLK_UPLLCON);
+	clk[XIN128_DIV]	= nuc970_clk_fixed_factor("xin128_div", "xin", 1, 128);
+	clk[SYS_MUX]	= nuc970_clk_mux("sys_mux", REG_CLK_DIV0, 3, 2,
+					 sys_sel_clks,
+					 ARRAY_SIZE(sys_sel_clks));
+	clk[SYS_DIV]	= nuc970_clk_divider("sys_div", "sys_mux",
+					     REG_CLK_DIV0, 0, 2);
+	clk[DDR_GATE]	= nuc970_clk_gate("ddr_gate", "sys_div",
+					  REG_CLK_HCLKEN, 10);
+	/* CPU */
+	clk[CPU_DIV]  = nuc970_clk_divider("cpu_div", "sys_div",
+					   REG_CLK_DIV0, 16, 1);
+	clk[CPU_GATE] = nuc970_clk_gate("cpu_gate", "cpu_div",
+					REG_CLK_HCLKEN, 0);
+	/*HCLK1 & PCLK*/
+	clk[HCLK1_DIV]	= nuc970_clk_fixed_factor("hclk1_div", "cpu_div", 1, 2);
+	clk[GDMA_GATE]	= nuc970_clk_gate("gdma_hclk_gate", "hclk1_div",
+					  REG_CLK_HCLKEN, 12);
+	clk[EBI_GATE]	= nuc970_clk_gate("ebi_hclk_gate", "hclk1_div",
+					  REG_CLK_HCLKEN, 9);
+	clk[TIC_GATE]	= nuc970_clk_gate("tic_hclk_gate", "hclk1_div",
+					  REG_CLK_HCLKEN, 7);
+	/* HCLK & HCLK234 */
+	clk[HCLKN_DIV]		= nuc970_clk_fixed_factor("hclkn_div",
+							  "sys_div", 1, 2);
+	clk[DRAM_GATE]		= nuc970_clk_gate("dram_gate", "hclkn_div",
+						  REG_CLK_HCLKEN, 10);
+	clk[HCLK_GATE]		= nuc970_clk_gate("hclk_gate", "hclkn_div",
+						  REG_CLK_HCLKEN, 1);
+	clk[SRAM_GATE]		= nuc970_clk_gate("sram_gate", "hclk_gate",
+						  REG_CLK_HCLKEN, 8);
+	clk[HCLK234_DIV]	= nuc970_clk_divider("hclk234_div", "hclkn_div",
+						     REG_CLK_DIV0, 20, 4);
+	/* HCLK3 */
+	clk[USBH_GATE]		= nuc970_clk_gate("usbh_hclk_gate",
+						  "hclk234_div",
+						  REG_CLK_HCLKEN, 18);
+	clk[USBD_GATE]		= nuc970_clk_gate("usbd_hclk_gate",
+						  "hclk234_div",
+						  REG_CLK_HCLKEN, 19);
+	clk[FMI_GATE]		= nuc970_clk_gate("fmi_hclk_gate",
+						  "hclk234_div",
+						  REG_CLK_HCLKEN, 20);
+	clk[NAND_GATE]		= nuc970_clk_gate("nand_hclk_gate",
+						  "hclk234_div",
+						  REG_CLK_HCLKEN, 21);
+	clk[EMMC_GATE]		= nuc970_clk_gate("emmc_hclk_gate",
+						  "hclk234_div",
+						  REG_CLK_HCLKEN, 22);
+	clk[CRYPTO_GATE]	= nuc970_clk_gate("crypto_hclk_gate",
+						  "hclk234_div",
+						  REG_CLK_HCLKEN, 23);
+	clk[EMAC1_GATE]		= nuc970_clk_gate("emac1_hclk_gate",
+						  "hclk234_div",
+						  REG_CLK_HCLKEN, 17);
+	clk[EMAC1_ECLK_DIV]	= nuc970_clk_divider("emac1_eclk_div",
+						     "hclk234_div",
+						     REG_CLK_DIV8, 0, 8);
+	clk[EMAC1_ECLK_GATE]	= nuc970_clk_gate("emac1_eclk_gate",
+						  "emac1_eclk_div",
+						  REG_CLK_HCLKEN, 17);
+	clk[JPEG_GATE]		= nuc970_clk_gate("jpeg_hclk_gate",
+						  "hclk234_div",
+						  REG_CLK_HCLKEN, 29);
+	clk[JPEG_ECLK_DIV]	= nuc970_clk_divider("jpeg_eclk_div",
+						     "hclk234_div",
+						     REG_CLK_DIV3, 28, 3);
+	clk[JPEG_ECLK_GATE]	= nuc970_clk_gate("jpeg_eclk_gate",
+						  "jpeg_eclk_div",
+						  REG_CLK_HCLKEN, 29);
+	clk[GE2D_GATE]		= nuc970_clk_gate("ge2d_hclk_gate",
+						  "hclk234_div",
+						  REG_CLK_HCLKEN, 28);
+	clk[GE2D_ECLK_DIV]	= nuc970_clk_divider("ge2d_eclk_div",
+						     "hclk234_div",
+						     REG_CLK_DIV2, 28, 2);
+	clk[GE2D_ECLK_GATE]	= nuc970_clk_gate("ge2d_eclk_gate",
+						  "ge2d_eclk_div",
+						  REG_CLK_HCLKEN, 28);
+	/* HCLK4 */
+	clk[SDH_GATE]		= nuc970_clk_gate("sdh_hclk_gate",
+						  "hclk234_div",
+						  REG_CLK_HCLKEN, 30);
+	clk[AUDIO_GATE]		= nuc970_clk_gate("audio_hclk_gate",
+						  "hclk234_div",
+						  REG_CLK_HCLKEN, 24);
+	clk[LCD_GATE]		= nuc970_clk_gate("lcd_hclk_gate",
+						  "hclk234_div",
+						  REG_CLK_HCLKEN, 25);
+	clk[CAP_GATE]		= nuc970_clk_gate("cap_hclk_gate",
+						  "hclk234_div",
+						  REG_CLK_HCLKEN, 26);
+	clk[SENSOR_GATE]	= nuc970_clk_gate("sensor_hclk_gate",
+						  "hclk234_div",
+						  REG_CLK_HCLKEN, 27);
+	clk[EMAC0_GATE]		= nuc970_clk_gate("emac0_hclk_gate",
+						  "hclk234_div",
+						  REG_CLK_HCLKEN, 16);
+	clk[EMAC0_ECLK_DIV]	= nuc970_clk_divider("emac0_eclk_div",
+						     "hclk234_div",
+						     REG_CLK_DIV8, 0, 8);
+	clk[EMAC0_ECLK_GATE]	= nuc970_clk_gate("emac0_eclk_gate",
+						  "emac0_eclk_div",
+						  REG_CLK_HCLKEN, 16);
+	/* ECLK */
+	/* USB */
+	clk[USB_APLLDIV]	= nuc970_clk_divider("usb_aplldiv", "apll",
+						     REG_CLK_DIV2, 0, 3);
+	clk[USB_UPLLDIV]	= nuc970_clk_divider("usb_uplldiv", "upll",
+						     REG_CLK_DIV2, 0, 3);
+	clk[USB_ECLK_MUX]	= nuc970_clk_mux("usb_eclk_mux", REG_CLK_DIV2,
+						 3, 2, usb_sel_clks,
+						 ARRAY_SIZE(usb_sel_clks));
+	clk[USB_ECLK_DIV]	= nuc970_clk_divider("usb_eclk_div",
+						     "usb_eclk_mux",
+						     REG_CLK_DIV2, 8, 4);
+	clk[USB_ECLK_GATE]	= nuc970_clk_gate("usb_eclk_gate",
+						  "usb_eclk_div",
+						  REG_CLK_HCLKEN, 18);
+	/* SDH */
+	clk[SDH_APLLDIV]	= nuc970_clk_divider("sdh_aplldiv", "apll",
+						     REG_CLK_DIV9, 0, 3);
+	clk[SDH_UPLLDIV]	= nuc970_clk_divider("sdh_uplldiv", "upll",
+						     REG_CLK_DIV9, 0, 3);
+	clk[SDH_ECLK_MUX]	= nuc970_clk_mux("sdh_eclk_mux", REG_CLK_DIV9,
+						 3, 2, sdh_sel_clks,
+						 ARRAY_SIZE(sdh_sel_clks));
+	clk[SDH_ECLK_DIV]	= nuc970_clk_divider("sdh_eclk_div",
+						     "sdh_eclk_mux",
+						     REG_CLK_DIV9, 8, 8);
+	clk[SDH_ECLK_GATE]	= nuc970_clk_gate("sdh_eclk_gate",
+						  "sdh_eclk_div",
+						  REG_CLK_HCLKEN, 30);
+	/* EMMC */
+	clk[EMMC_APLLDIV]	= nuc970_clk_divider("emmc_aplldiv", "apll",
+						     REG_CLK_DIV3, 0, 3);
+	clk[EMMC_UPLLDIV]	= nuc970_clk_divider("emmc_uplldiv", "upll",
+						     REG_CLK_DIV3, 0, 3);
+	clk[EMMC_ECLK_MUX]	= nuc970_clk_mux("emmc_eclk_mux", REG_CLK_DIV3,
+						 3, 2, emmc_sel_clks,
+						 ARRAY_SIZE(emmc_sel_clks));
+	clk[EMMC_ECLK_DIV]	= nuc970_clk_divider("emmc_eclk_div",
+						     "emmc_eclk_mux",
+						     REG_CLK_DIV3, 8, 8);
+	clk[EMMC_ECLK_GATE]	= nuc970_clk_gate("emmc_eclk_gate",
+						  "emmc_eclk_div",
+						  REG_CLK_HCLKEN, 22);
+	/* ADC */
+	clk[ADC_APLLDIV]	= nuc970_clk_divider("adc_aplldiv", "apll",
+						     REG_CLK_DIV7, 16, 3);
+	clk[ADC_UPLLDIV]	= nuc970_clk_divider("adc_uplldiv", "upll",
+						     REG_CLK_DIV7, 16, 3);
+	clk[ADC_ECLK_MUX]	= nuc970_clk_mux("adc_eclk_mux", REG_CLK_DIV7,
+						 19, 2, adc_sel_clks,
+						 ARRAY_SIZE(adc_sel_clks));
+	clk[ADC_ECLK_DIV]	= nuc970_clk_divider("adc_eclk_div",
+						     "adc_eclk_mux",
+						     REG_CLK_DIV7, 24, 8);
+	clk[ADC_ECLK_GATE]	= nuc970_clk_gate("adc_eclk_gate",
+						  "adc_eclk_div",
+						  REG_CLK_PCLKEN1, 24);
+	/* LCD */
+	clk[LCD_APLLDIV]	= nuc970_clk_divider("lcd_aplldiv", "apll",
+						     REG_CLK_DIV1, 0, 3);
+	clk[LCD_UPLLDIV]	= nuc970_clk_divider("lcd_uplldiv", "upll",
+					     REG_CLK_DIV1, 0, 3);
+	clk[LCD_ECLK_MUX]	= nuc970_clk_mux("lcd_eclk_mux", REG_CLK_DIV1,
+						 3, 2, lcd_sel_clks,
+						 ARRAY_SIZE(lcd_sel_clks));
+	clk[LCD_ECLK_DIV]	= nuc970_clk_divider("lcd_eclk_div",
+						     "lcd_eclk_mux",
+						     REG_CLK_DIV1, 8, 8);
+	clk[LCD_ECLK_GATE]	= nuc970_clk_gate("lcd_eclk_gate",
+						  "lcd_eclk_div",
+						  REG_CLK_HCLKEN, 25);
+	/* AUDIO */
+	clk[AUDIO_APLLDIV]	= nuc970_clk_divider("audio_aplldiv", "apll",
+						     REG_CLK_DIV1, 16, 3);
+	clk[AUDIO_UPLLDIV]	= nuc970_clk_divider("audio_uplldiv", "upll",
+						     REG_CLK_DIV1, 16, 3);
+	clk[AUDIO_ECLK_MUX]	= nuc970_clk_mux("audio_eclk_mux", REG_CLK_DIV1,
+						 19, 2, audio_sel_clks,
+						 ARRAY_SIZE(audio_sel_clks));
+	clk[AUDIO_ECLK_DIV]	= nuc970_clk_divider("audio_eclk_div",
+						     "audio_eclk_mux",
+						     REG_CLK_DIV1, 24, 8);
+	clk[AUDIO_ECLK_GATE]	= nuc970_clk_gate("audio_eclk_gate",
+						  "audio_eclk_div",
+						  REG_CLK_HCLKEN, 24);
+	/* CAP */
+	clk[CAP_APLLDIV]	= nuc970_clk_divider("cap_aplldiv", "apll",
+						     REG_CLK_DIV3, 16, 3);
+	clk[CAP_UPLLDIV]	= nuc970_clk_divider("cap_uplldiv", "upll",
+						     REG_CLK_DIV3, 16, 3);
+	clk[CAP_ECLK_MUX]	= nuc970_clk_mux("cap_eclk_mux", REG_CLK_DIV3,
+						 19, 2, cap_sel_clks,
+						 ARRAY_SIZE(cap_sel_clks));
+	clk[CAP_ECLK_DIV]	= nuc970_clk_divider("cap_eclk_div",
+						     "cap_eclk_mux",
+						     REG_CLK_DIV3, 24, 4);
+	clk[CAP_ECLK_GATE]	= nuc970_clk_gate("cap_eclk_gate",
+						  "cap_eclk_div",
+						  REG_CLK_HCLKEN, 26);
+	/* UART0 */
+	clk[UART0_APLLDIV]	= nuc970_clk_divider("uart0_aplldiv",
+						     "apll", REG_CLK_DIV4,
+						     0, 3);
+	clk[UART0_UPLLDIV]	= nuc970_clk_divider("uart0_uplldiv", "upll",
+						     REG_CLK_DIV4, 0, 3);
+	clk[UART0_ECLK_MUX]	= nuc970_clk_mux("uart0_eclk_mux", REG_CLK_DIV4,
+						 3, 2, uart0_sel_clks,
+						 ARRAY_SIZE(uart0_sel_clks));
+	clk[UART0_ECLK_DIV]	= nuc970_clk_divider("uart0_eclk_div",
+						     "uart0_eclk_mux",
+						     REG_CLK_DIV4, 5, 3);
+	clk[UART0_ECLK_GATE]	= nuc970_clk_gate("uart0_eclk_gate",
+						  "uart0_eclk_div",
+						  REG_CLK_PCLKEN0, 16);
+	/* UART1 */
+	clk[UART1_APLLDIV]	= nuc970_clk_divider("uart1_aplldiv", "apll",
+						     REG_CLK_DIV4, 8, 3);
+	clk[UART1_UPLLDIV]	= nuc970_clk_divider("uart1_uplldiv", "upll",
+						     REG_CLK_DIV4, 8, 3);
+	clk[UART1_ECLK_MUX]	= nuc970_clk_mux("uart1_eclk_mux", REG_CLK_DIV4,
+						 11, 2, uart1_sel_clks,
+						 ARRAY_SIZE(uart1_sel_clks));
+	clk[UART1_ECLK_DIV]	= nuc970_clk_divider("uart1_eclk_div",
+						     "uart1_eclk_mux",
+						     REG_CLK_DIV4, 13, 3);
+	clk[UART1_ECLK_GATE]	= nuc970_clk_gate("uart1_eclk_gate",
+						  "uart1_eclk_div",
+						  REG_CLK_PCLKEN0, 17);
+	/* UART2 */
+	clk[UART2_APLLDIV]	= nuc970_clk_divider("uart2_aplldiv", "apll",
+						     REG_CLK_DIV4, 16, 3);
+	clk[UART2_UPLLDIV]	= nuc970_clk_divider("uart2_uplldiv", "upll",
+						     REG_CLK_DIV4, 16, 3);
+	clk[UART2_ECLK_MUX]	= nuc970_clk_mux("uart2_eclk_mux", REG_CLK_DIV4,
+						 19, 2, uart2_sel_clks,
+						 ARRAY_SIZE(uart2_sel_clks));
+	clk[UART2_ECLK_DIV]	= nuc970_clk_divider("uart2_eclk_div",
+						     "uart2_eclk_mux",
+						     REG_CLK_DIV4, 21, 3);
+	clk[UART2_ECLK_GATE]	= nuc970_clk_gate("uart2_eclk_gate",
+						  "uart2_eclk_div",
+						  REG_CLK_PCLKEN0, 18);
+	/* UART3 */
+	clk[UART3_APLLDIV]	= nuc970_clk_divider("uart3_aplldiv", "apll",
+						     REG_CLK_DIV4, 24, 3);
+	clk[UART3_UPLLDIV]	= nuc970_clk_divider("uart3_uplldiv", "upll",
+						     REG_CLK_DIV4, 24, 3);
+	clk[UART3_ECLK_MUX]	= nuc970_clk_mux("uart3_eclk_mux", REG_CLK_DIV4,
+						 27, 2, uart3_sel_clks,
+						 ARRAY_SIZE(uart3_sel_clks));
+	clk[UART3_ECLK_DIV]	= nuc970_clk_divider("uart3_eclk_div",
+						     "uart3_eclk_mux",
+						     REG_CLK_DIV4, 29, 3);
+	clk[UART3_ECLK_GATE]	= nuc970_clk_gate("uart3_eclk_gate",
+						  "uart3_eclk_div",
+						  REG_CLK_PCLKEN0, 19);
+	/* UART4 */
+	clk[UART4_APLLDIV]	= nuc970_clk_divider("uart4_aplldiv", "apll",
+						     REG_CLK_DIV5, 0, 3);
+	clk[UART4_UPLLDIV]	= nuc970_clk_divider("uart4_uplldiv", "upll",
+						     REG_CLK_DIV5, 0, 3);
+	clk[UART4_ECLK_MUX]	= nuc970_clk_mux("uart4_eclk_mux", REG_CLK_DIV5,
+						 3, 2, uart4_sel_clks,
+						 ARRAY_SIZE(uart4_sel_clks));
+	clk[UART4_ECLK_DIV]	= nuc970_clk_divider("uart4_eclk_div",
+						     "uart4_eclk_mux",
+						     REG_CLK_DIV5, 5, 3);
+	clk[UART4_ECLK_GATE]	= nuc970_clk_gate("uart4_eclk_gate",
+						  "uart4_eclk_div",
+						  REG_CLK_PCLKEN0, 20);
+	/* UART5 */
+	clk[UART5_APLLDIV]	= nuc970_clk_divider("uart5_aplldiv", "apll",
+						     REG_CLK_DIV5, 8, 3);
+	clk[UART5_UPLLDIV]	= nuc970_clk_divider("uart5_uplldiv", "upll",
+						     REG_CLK_DIV5, 8, 3);
+	clk[UART5_ECLK_MUX]	= nuc970_clk_mux("uart5_eclk_mux", REG_CLK_DIV5,
+						 11, 2, uart5_sel_clks,
+						 ARRAY_SIZE(uart5_sel_clks));
+	clk[UART5_ECLK_DIV]	= nuc970_clk_divider("uart5_eclk_div",
+						     "uart5_eclk_mux",
+						     REG_CLK_DIV5, 13, 3);
+	clk[UART5_ECLK_GATE]	= nuc970_clk_gate("uart5_eclk_gate",
+						  "uart5_eclk_div",
+						  REG_CLK_PCLKEN0, 21);
+	/* UART6 */
+	clk[UART6_APLLDIV]	= nuc970_clk_divider("uart6_aplldiv", "apll",
+						     REG_CLK_DIV5, 16, 3);
+	clk[UART6_UPLLDIV]	= nuc970_clk_divider("uart6_uplldiv", "upll",
+						     REG_CLK_DIV5, 16, 3);
+	clk[UART6_ECLK_MUX]	= nuc970_clk_mux("uart6_eclk_mux", REG_CLK_DIV5,
+						 19, 2, uart6_sel_clks,
+						 ARRAY_SIZE(uart6_sel_clks));
+	clk[UART6_ECLK_DIV]	= nuc970_clk_divider("uart6_eclk_div",
+						     "uart6_eclk_mux",
+						     REG_CLK_DIV5, 21, 3);
+	clk[UART6_ECLK_GATE]	= nuc970_clk_gate("uart6_eclk_gate",
+						  "uart6_eclk_div",
+						  REG_CLK_PCLKEN0, 22);
+	/* UART7 */
+	clk[UART7_APLLDIV]	= nuc970_clk_divider("uart7_aplldiv", "apll",
+						     REG_CLK_DIV5, 24, 3);
+	clk[UART7_UPLLDIV]	= nuc970_clk_divider("uart7_uplldiv", "upll",
+						     REG_CLK_DIV5, 24, 3);
+	clk[UART7_ECLK_MUX]	= nuc970_clk_mux("uart7_eclk_mux", REG_CLK_DIV5,
+						 27, 2, uart7_sel_clks,
+						 ARRAY_SIZE(uart7_sel_clks));
+	clk[UART7_ECLK_DIV]	= nuc970_clk_divider("uart7_eclk_div",
+						     "uart7_eclk_mux",
+						     REG_CLK_DIV5, 29, 3);
+	clk[UART7_ECLK_GATE]	= nuc970_clk_gate("uart7_eclk_gate",
+						  "uart7_eclk_div",
+						  REG_CLK_PCLKEN0, 23);
+	/* UART8 */
+	clk[UART8_APLLDIV]	= nuc970_clk_divider("uart8_aplldiv", "apll",
+						     REG_CLK_DIV6, 0, 3);
+	clk[UART8_UPLLDIV]	= nuc970_clk_divider("uart8_uplldiv", "upll",
+						     REG_CLK_DIV6, 0, 3);
+	clk[UART8_ECLK_MUX]	= nuc970_clk_mux("uart8_eclk_mux", REG_CLK_DIV6,
+						 3, 2, uart8_sel_clks,
+						 ARRAY_SIZE(uart8_sel_clks));
+	clk[UART8_ECLK_DIV]	= nuc970_clk_divider("uart8_eclk_div",
+						     "uart8_eclk_mux",
+						     REG_CLK_DIV6, 5, 3);
+	clk[UART8_ECLK_GATE]	= nuc970_clk_gate("uart8_eclk_gate",
+						  "uart8_eclk_div",
+						  REG_CLK_PCLKEN0, 24);
+	/* UART9 */
+	clk[UART9_APLLDIV]	= nuc970_clk_divider("uart9_aplldiv", "apll",
+						     REG_CLK_DIV6, 8, 3);
+	clk[UART9_UPLLDIV]	= nuc970_clk_divider("uart9_uplldiv", "upll",
+						     REG_CLK_DIV6, 8, 3);
+	clk[UART9_ECLK_MUX]	= nuc970_clk_mux("uart9_eclk_mux", REG_CLK_DIV6,
+						 11, 2, uart9_sel_clks,
+						 ARRAY_SIZE(uart9_sel_clks));
+	clk[UART9_ECLK_DIV]	= nuc970_clk_divider("uart9_eclk_div",
+						     "uart9_eclk_mux",
+						     REG_CLK_DIV6, 13, 3);
+	clk[UART9_ECLK_GATE]	= nuc970_clk_gate("uart9_eclk_gate",
+						  "uart9_eclk_div",
+						  REG_CLK_PCLKEN0, 25);
+	/* UART10 */
+	clk[UART10_APLLDIV]	 = nuc970_clk_divider("uart10_aplldiv", "apll",
+						      REG_CLK_DIV6, 16, 3);
+	clk[UART10_UPLLDIV]	 = nuc970_clk_divider("uart10_uplldiv", "upll",
+						      REG_CLK_DIV6, 16, 3);
+	clk[UART10_ECLK_MUX]	= nuc970_clk_mux("uart10_eclk_mux",
+						 REG_CLK_DIV6, 19, 2,
+						 uart10_sel_clks,
+						 ARRAY_SIZE(uart10_sel_clks));
+	clk[UART10_ECLK_DIV]	= nuc970_clk_divider("uart10_eclk_div",
+						     "uart10_eclk_mux",
+						     REG_CLK_DIV6, 21, 3);
+	clk[UART10_ECLK_GATE]	= nuc970_clk_gate("uart10_eclk_gate",
+						  "uart10_eclk_div",
+						  REG_CLK_PCLKEN0, 26);
+	/* SYSTEM */
+	clk[SYSTEM_APLLDIV]	= nuc970_clk_divider("system_aplldiv", "apll",
+						     REG_CLK_DIV0, 0, 3);
+	clk[SYSTEM_UPLLDIV]	= nuc970_clk_divider("system_uplldiv", "upll",
+						     REG_CLK_DIV0, 0, 3);
+	clk[SYSTEM_ECLK_MUX]	= nuc970_clk_mux("system_eclk_mux",
+						 REG_CLK_DIV0, 3, 2,
+						 system_sel_clks,
+						 ARRAY_SIZE(system_sel_clks));
+	clk[SYSTEM_ECLK_DIV]	= nuc970_clk_divider("system_eclk_div",
+						     "system_eclk_mux",
+						     REG_CLK_DIV0, 8, 4);
+	/* GPIO */
+	clk[GPIO_ECLK_MUX]	= nuc970_clk_mux("gpio_eclk_mux", REG_CLK_DIV7,
+						 7, 1, gpio_sel_clks,
+						 ARRAY_SIZE(gpio_sel_clks));
+	clk[GPIO_ECLK_DIV]	= nuc970_clk_divider("gpio_eclk_div",
+						     "gpio_eclk_mux",
+						     REG_CLK_DIV7, 0, 7);
+	clk[GPIO_ECLK_GATE]	= nuc970_clk_gate("gpio_eclk_gate",
+						  "gpio_eclk_div",
+						  REG_CLK_PCLKEN0, 3);
+	/* KPI */
+	clk[KPI_ECLK_MUX]	= nuc970_clk_mux("kpi_eclk_mux", REG_CLK_DIV7,
+						 15, 1, kpi_sel_clks,
+						 ARRAY_SIZE(kpi_sel_clks));
+	clk[KPI_ECLK_DIV]	= nuc970_clk_divider("kpi_eclk_div",
+						     "kpi_eclk_mux",
+						     REG_CLK_DIV7, 8, 7);
+	clk[KPI_ECLK_GATE]	= nuc970_clk_gate("kpi_eclk_gate",
+						  "kpi_eclk_div",
+						  REG_CLK_PCLKEN1, 25);
+	/* ETIMER0 */
+	clk[ETIMER0_ECLK_MUX]	= nuc970_clk_mux("etimer0_eclk_mux",
+						 REG_CLK_DIV8, 16, 2,
+						 etimer_sel_clks,
+						 ARRAY_SIZE(etimer_sel_clks));
+	clk[ETIMER0_ECLK_GATE]	= nuc970_clk_gate("etimer0_eclk_gate",
+						  "etimer0_eclk_mux",
+						  REG_CLK_PCLKEN0, 4);
+	/* ETIMER1 */
+	clk[ETIMER1_ECLK_MUX]	= nuc970_clk_mux("etimer1_eclk_mux",
+						 REG_CLK_DIV8, 18, 2,
+						 etimer_sel_clks,
+						 ARRAY_SIZE(etimer_sel_clks));
+	clk[ETIMER1_ECLK_GATE]	= nuc970_clk_gate("etimer1_eclk_gate",
+						  "etimer1_eclk_mux",
+						  REG_CLK_PCLKEN0, 5);
+	/* ETIMER2 */
+	clk[ETIMER2_ECLK_MUX]	= nuc970_clk_mux("etimer2_eclk_mux",
+						 REG_CLK_DIV8, 20, 2,
+						 etimer_sel_clks,
+						 ARRAY_SIZE(etimer_sel_clks));
+	clk[ETIMER2_ECLK_GATE]	= nuc970_clk_gate("etimer2_eclk_gate",
+						  "etimer2_eclk_mux",
+						  REG_CLK_PCLKEN0, 6);
+	/* ETIMER3 */
+	clk[ETIMER3_ECLK_MUX]	= nuc970_clk_mux("etimer3_eclk_mux",
+						 REG_CLK_DIV8, 22, 2,
+						 etimer_sel_clks,
+						 ARRAY_SIZE(etimer_sel_clks));
+	clk[ETIMER3_ECLK_GATE]	= nuc970_clk_gate("etimer3_eclk_gate",
+						  "etimer3_eclk_mux",
+						  REG_CLK_PCLKEN0, 7);
+	/* WWDT */
+	clk[WWDT_ECLK_MUX]	= nuc970_clk_mux("wwdt_eclk_mux", REG_CLK_DIV8,
+						 10, 2, wwdt_sel_clks,
+						 ARRAY_SIZE(wwdt_sel_clks));
+	clk[WWDT_ECLK_GATE]	= nuc970_clk_gate("wwdt_eclk_gate",
+						  "wwdt_eclk_mux",
+						  REG_CLK_PCLKEN0, 1);
+	/* WDT */
+	clk[WDT_ECLK_MUX]	= nuc970_clk_mux("wdt_eclk_mux", REG_CLK_DIV8,
+						 8, 2, wwdt_sel_clks,
+						 ARRAY_SIZE(wwdt_sel_clks));
+	clk[WDT_ECLK_GATE]	= nuc970_clk_gate("wdt_eclk_gate",
+						  "wdt_eclk_mux",
+						  REG_CLK_PCLKEN0, 0);
+	/* SMARTCARD */
+	clk[SMC0_ECLK_DIV]	= nuc970_clk_divider("smc0_eclk_div", "xin",
+						     REG_CLK_DIV6, 24, 4);
+	clk[SMC0_ECLK_GATE]	= nuc970_clk_gate("smc0_eclk_gate",
+						  "smc0_eclk_div",
+						  REG_CLK_PCLKEN1, 12);
+	clk[SMC1_ECLK_DIV]	= nuc970_clk_divider("smc1_eclk_div", "xin",
+						     REG_CLK_DIV6, 28, 4);
+	clk[SMC1_ECLK_GATE]	= nuc970_clk_gate("smc1_eclk_gate",
+						  "smc1_eclk_div",
+						  REG_CLK_PCLKEN1, 13);
+	/* PCLK */
+	clk[PCLK_DIV]		= nuc970_clk_divider("pclk_div", "hclk1_div",
+						     REG_CLK_DIV0, 24, 4);
+	clk[PCLK4096_DIV]	= nuc970_clk_fixed_factor("pclk4096_div",
+							  "pclk_div", 1, 4096);
+	clk[I2C0_GATE]		= nuc970_clk_gate("i2c0_gate", "pclk_div",
+						  REG_CLK_PCLKEN1, 0);
+	clk[I2C1_GATE]		= nuc970_clk_gate("i2c1_gate", "pclk_div",
+						  REG_CLK_PCLKEN1, 1);
+	clk[SPI0_GATE]		= nuc970_clk_gate("spi0_gate", "pclk_div",
+						  REG_CLK_PCLKEN1, 4);
+	clk[SPI1_GATE]		= nuc970_clk_gate("spi1_gate", "pclk_div",
+						  REG_CLK_PCLKEN1, 5);
+	clk[UART0_GATE]		= nuc970_clk_gate("uart0_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 16);
+	clk[UART1_GATE]		= nuc970_clk_gate("uart1_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 17);
+	clk[UART2_GATE]		= nuc970_clk_gate("uart2_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 18);
+	clk[UART3_GATE]		= nuc970_clk_gate("uart3_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 19);
+	clk[UART4_GATE]		= nuc970_clk_gate("uart4_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 20);
+	clk[UART5_GATE]		= nuc970_clk_gate("uart5_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 21);
+	clk[UART6_GATE]		= nuc970_clk_gate("uart6_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 22);
+	clk[UART7_GATE]		= nuc970_clk_gate("uart7_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 23);
+	clk[UART8_GATE]		= nuc970_clk_gate("uart8_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 24);
+	clk[UART9_GATE]		= nuc970_clk_gate("uart9_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 25);
+	clk[UART10_GATE]	= nuc970_clk_gate("uart10_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 26);
+	clk[WDT_GATE]		= nuc970_clk_gate("wdt_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 0);
+	clk[WWDT_GATE]		= nuc970_clk_gate("wwdt_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 1);
+	clk[RTC_GATE]		= nuc970_clk_gate("rtc_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 2);
+	clk[GPIO_GATE]		= nuc970_clk_gate("gpio_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 3);
+	clk[ADC_GATE]		= nuc970_clk_gate("adc_gate", "pclk_div",
+						  REG_CLK_PCLKEN1, 24);
+	clk[KPI_GATE]		= nuc970_clk_gate("kpi_gate", "pclk_div",
+						  REG_CLK_PCLKEN1, 25);
+	clk[MTPC_GATE]		= nuc970_clk_gate("mtpc_gate", "pclk_div",
+						  REG_CLK_PCLKEN1, 26);
+	clk[PWM_GATE]		= nuc970_clk_gate("pwm_gate", "pclk_div",
+						  REG_CLK_PCLKEN1, 27);
+	clk[ETIMER0_GATE]	= nuc970_clk_gate("etimer0_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 4);
+	clk[ETIMER1_GATE]	= nuc970_clk_gate("etimer1_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 5);
+	clk[ETIMER2_GATE]	= nuc970_clk_gate("etimer2_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 6);
+	clk[ETIMER3_GATE]	= nuc970_clk_gate("etimer3_gate", "pclk_div",
+						  REG_CLK_PCLKEN0, 7);
+	clk[CAN0_GATE]		= nuc970_clk_gate("can0_gate", "pclk_div",
+						  REG_CLK_PCLKEN1, 8);
+	clk[CAN1_GATE]		= nuc970_clk_gate("can1_gate", "pclk_div",
+						  REG_CLK_PCLKEN1, 9);
+	clk[TIMER0_GATE]	= nuc970_clk_gate("timer0_gate", "xin",
+						  REG_CLK_PCLKEN0, 8);
+	clk[TIMER1_GATE]	= nuc970_clk_gate("timer1_gate", "xin",
+						  REG_CLK_PCLKEN0, 9);
+	clk[TIMER2_GATE]	= nuc970_clk_gate("timer2_gate", "xin",
+						  REG_CLK_PCLKEN0, 10);
+	clk[TIMER3_GATE]	= nuc970_clk_gate("timer3_gate", "xin",
+						  REG_CLK_PCLKEN0, 11);
+	clk[TIMER4_GATE]	= nuc970_clk_gate("timer4_gate", "xin",
+						  REG_CLK_PCLKEN0, 12);
+	clk[SMC0_GATE]		= nuc970_clk_gate("smc0_gate", "pclk_div",
+						  REG_CLK_PCLKEN1, 12);
+	clk[SMC1_GATE]		= nuc970_clk_gate("smc1_gate", "pclk_div",
+						  REG_CLK_PCLKEN1, 13);
+
+	for (i = 0; i < ARRAY_SIZE(clk); i++)
+		if (IS_ERR(clk[i]))
+			pr_err("nuc970 clk %d: register failed with %ld\n",
+				i, PTR_ERR(clk[i]));
+
+	clk_data.clks = clk;
+	clk_data.clk_num = ARRAY_SIZE(clk);
+	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+	/* Register clock device */
+	clk_register_clkdev(clk[TIMER0_GATE], "timer0", NULL);
+	clk_register_clkdev(clk[TIMER1_GATE], "timer1", NULL);
+	clk_register_clkdev(clk[PCLK4096_DIV], "pclk4096_div", NULL);
+	clk_register_clkdev(clk[XIN], "xin", NULL);
+	clk_register_clkdev(clk[XIN32K], "xin32k", NULL);
+	clk_register_clkdev(clk[APLL], "apll", NULL);
+	clk_register_clkdev(clk[UPLL], "upll", NULL);
+	clk_register_clkdev(clk[SYS_MUX], "sysmux", NULL);
+	clk_register_clkdev(clk[SYS_DIV], "sysdiv", NULL);
+	clk_register_clkdev(clk[XIN128_DIV], "xin128div", NULL);
+	/* CPU */
+	clk_register_clkdev(clk[CPU_DIV], "cpudiv", NULL);
+	clk_register_clkdev(clk[CPU_GATE], "cpu", NULL);
+	/* HCLK1 */
+	clk_register_clkdev(clk[HCLK_GATE], "hclk", NULL);
+	clk_register_clkdev(clk[SRAM_GATE], "sram", NULL);
+	clk_register_clkdev(clk[HCLK1_DIV], "hclk1div", NULL);
+	clk_register_clkdev(clk[DDR_GATE], "ddr_hclk", NULL);
+	clk_register_clkdev(clk[GDMA_GATE], "gdma_hclk", NULL);
+	clk_register_clkdev(clk[EBI_GATE], "ebi_hclk", NULL);
+	clk_register_clkdev(clk[TIC_GATE], "tic_hclk", NULL);
+	/* HCLK234 */
+	clk_register_clkdev(clk[HCLKN_DIV], "hclkndiv", NULL);
+	clk_register_clkdev(clk[DRAM_GATE], "dram", NULL);
+	clk_register_clkdev(clk[HCLK234_DIV], "hclk234div", NULL);
+	/* HCLK3 */
+	clk_register_clkdev(clk[USBH_GATE], "usbh_hclk", NULL);
+	clk_register_clkdev(clk[EMAC1_GATE], "emac1_hclk", NULL);
+	clk_register_clkdev(clk[EMAC1_ECLK_DIV], "emac1_eclk_div", NULL);
+	clk_register_clkdev(clk[EMAC1_ECLK_GATE], "emac1_eclk", NULL);
+	clk_register_clkdev(clk[USBD_GATE], "usbd_hclk", NULL);
+	clk_register_clkdev(clk[FMI_GATE], "fmi_hclk", NULL);
+	clk_register_clkdev(clk[NAND_GATE], "nand_hclk", NULL);
+	clk_register_clkdev(clk[EMMC_GATE], "emmc_hclk", NULL);
+	clk_register_clkdev(clk[CRYPTO_GATE], "crypto_hclk", NULL);
+	clk_register_clkdev(clk[JPEG_GATE], "jpeg_hclk", NULL);
+	clk_register_clkdev(clk[JPEG_ECLK_DIV], "jpeg_eclk_div", NULL);
+	clk_register_clkdev(clk[JPEG_ECLK_GATE], "jpeg_eclk", NULL);
+	clk_register_clkdev(clk[GE2D_GATE], "ge2d_hclk", NULL);
+	clk_register_clkdev(clk[GE2D_ECLK_DIV], "ge2d_eclk_div", NULL);
+	clk_register_clkdev(clk[GE2D_ECLK_GATE], "ge2d_eclk", NULL);
+	/* HCLK4 */
+	clk_register_clkdev(clk[EMAC0_GATE], "emac0_hclk", NULL);
+	clk_register_clkdev(clk[EMAC0_ECLK_DIV], "emac0_eclk_div", NULL);
+	clk_register_clkdev(clk[EMAC0_ECLK_GATE], "emac0_eclk", NULL);
+	clk_register_clkdev(clk[SDH_GATE], "sdh_hclk", NULL);
+	clk_register_clkdev(clk[AUDIO_GATE], "audio_hclk", NULL);
+	clk_register_clkdev(clk[LCD_GATE], "lcd_hclk", NULL);
+	clk_register_clkdev(clk[SENSOR_GATE], "sensor_hclk", NULL);
+	clk_register_clkdev(clk[CAP_GATE], "cap_hclk", NULL);
+	/* ECLK */
+	clk_register_clkdev(clk[LCD_APLLDIV], "lcd_aplldiv", NULL);
+	clk_register_clkdev(clk[LCD_UPLLDIV], "lcd_uplldiv", NULL);
+	clk_register_clkdev(clk[LCD_ECLK_MUX], "lcd_eclk_mux", NULL);
+	clk_register_clkdev(clk[LCD_ECLK_DIV], "lcd_eclk_div", NULL);
+	clk_register_clkdev(clk[LCD_ECLK_GATE], "lcd_eclk", NULL);
+	clk_register_clkdev(clk[AUDIO_APLLDIV], "audio_aplldiv", NULL);
+	clk_register_clkdev(clk[AUDIO_UPLLDIV], "audio_uplldiv", NULL);
+	clk_register_clkdev(clk[AUDIO_ECLK_MUX], "audio_eclk_mux", NULL);
+	clk_register_clkdev(clk[AUDIO_ECLK_DIV], "audio_eclk_div", NULL);
+	clk_register_clkdev(clk[AUDIO_ECLK_GATE], "audio_eclk", NULL);
+	clk_register_clkdev(clk[USB_APLLDIV], "usb_aplldiv", NULL);
+	clk_register_clkdev(clk[USB_UPLLDIV], "usb_uplldiv", NULL);
+	clk_register_clkdev(clk[USB_ECLK_MUX], "usb_eclk_mux", NULL);
+	clk_register_clkdev(clk[USB_ECLK_DIV], "usb_eclk_div", NULL);
+	clk_register_clkdev(clk[USB_ECLK_GATE], "usb_eclk", NULL);
+	clk_register_clkdev(clk[SDH_APLLDIV], "sdh_aplldiv", NULL);
+	clk_register_clkdev(clk[SDH_UPLLDIV], "sdh_uplldiv", NULL);
+	clk_register_clkdev(clk[SDH_ECLK_MUX], "sdh_eclk_mux", NULL);
+	clk_register_clkdev(clk[SDH_ECLK_DIV], "sdh_eclk_div", NULL);
+	clk_register_clkdev(clk[SDH_ECLK_GATE], "sdh_eclk", NULL);
+	clk_register_clkdev(clk[EMMC_APLLDIV], "emmc_aplldiv", NULL);
+	clk_register_clkdev(clk[EMMC_UPLLDIV], "emmc_uplldiv", NULL);
+	clk_register_clkdev(clk[EMMC_ECLK_MUX], "emmc_eclk_mux", NULL);
+	clk_register_clkdev(clk[EMMC_ECLK_DIV], "emmc_eclk_div", NULL);
+	clk_register_clkdev(clk[EMMC_ECLK_GATE], "emmc_eclk", NULL);
+	clk_register_clkdev(clk[ADC_APLLDIV], "adc_aplldiv", NULL);
+	clk_register_clkdev(clk[ADC_UPLLDIV], "adc_uplldiv", NULL);
+	clk_register_clkdev(clk[ADC_ECLK_MUX], "adc_eclk_mux", NULL);
+	clk_register_clkdev(clk[ADC_ECLK_DIV], "adc_eclk_div", NULL);
+	clk_register_clkdev(clk[ADC_ECLK_GATE], "adc_eclk", NULL);
+	clk_register_clkdev(clk[CAP_APLLDIV], "cap_aplldiv", NULL);
+	clk_register_clkdev(clk[CAP_UPLLDIV], "cap_uplldiv", NULL);
+	clk_register_clkdev(clk[CAP_ECLK_MUX], "cap_eclk_mux", NULL);
+	clk_register_clkdev(clk[CAP_ECLK_DIV], "cap_eclk_div", NULL);
+	clk_register_clkdev(clk[CAP_ECLK_GATE], "cap_eclk", NULL);
+	clk_register_clkdev(clk[UART0_APLLDIV], "uart0_aplldiv", NULL);
+	clk_register_clkdev(clk[UART0_UPLLDIV], "uart0_uplldiv", NULL);
+	clk_register_clkdev(clk[UART0_ECLK_MUX], "uart0_eclk_mux", NULL);
+	clk_register_clkdev(clk[UART0_ECLK_DIV], "uart0_eclk_div", NULL);
+	clk_register_clkdev(clk[UART0_ECLK_GATE], "uart0_eclk", NULL);
+	clk_register_clkdev(clk[UART1_APLLDIV], "uart1_aplldiv", NULL);
+	clk_register_clkdev(clk[UART1_UPLLDIV], "uart1_uplldiv", NULL);
+	clk_register_clkdev(clk[UART1_ECLK_MUX], "uart1_eclk_mux", NULL);
+	clk_register_clkdev(clk[UART1_ECLK_DIV], "uart1_eclk_div", NULL);
+	clk_register_clkdev(clk[UART1_ECLK_GATE], "uart1_eclk", NULL);
+	clk_register_clkdev(clk[UART2_APLLDIV], "uart2_aplldiv", NULL);
+	clk_register_clkdev(clk[UART2_UPLLDIV], "uart2_uplldiv", NULL);
+	clk_register_clkdev(clk[UART2_ECLK_MUX], "uart2_eclk_mux", NULL);
+	clk_register_clkdev(clk[UART2_ECLK_DIV], "uart2_eclk_div", NULL);
+	clk_register_clkdev(clk[UART2_ECLK_GATE], "uart2_eclk", NULL);
+	clk_register_clkdev(clk[UART3_APLLDIV], "uart3_aplldiv", NULL);
+	clk_register_clkdev(clk[UART3_UPLLDIV], "uart3_uplldiv", NULL);
+	clk_register_clkdev(clk[UART3_ECLK_MUX], "uart3_eclk_mux", NULL);
+	clk_register_clkdev(clk[UART3_ECLK_DIV], "uart3_eclk_div", NULL);
+	clk_register_clkdev(clk[UART3_ECLK_GATE], "uart3_eclk", NULL);
+	clk_register_clkdev(clk[UART4_APLLDIV], "uart4_aplldiv", NULL);
+	clk_register_clkdev(clk[UART4_UPLLDIV], "uart4_uplldiv", NULL);
+	clk_register_clkdev(clk[UART4_ECLK_MUX], "uart4_eclk_mux", NULL);
+	clk_register_clkdev(clk[UART4_ECLK_DIV], "uart4_eclk_div", NULL);
+	clk_register_clkdev(clk[UART4_ECLK_GATE], "uart4_eclk", NULL);
+	clk_register_clkdev(clk[UART5_APLLDIV], "uart5_aplldiv", NULL);
+	clk_register_clkdev(clk[UART5_UPLLDIV], "uart5_uplldiv", NULL);
+	clk_register_clkdev(clk[UART5_ECLK_MUX], "uart5_eclk_mux", NULL);
+	clk_register_clkdev(clk[UART5_ECLK_DIV], "uart5_eclk_div", NULL);
+	clk_register_clkdev(clk[UART5_ECLK_GATE], "uart5_eclk", NULL);
+	clk_register_clkdev(clk[UART6_APLLDIV], "uart6_aplldiv", NULL);
+	clk_register_clkdev(clk[UART6_UPLLDIV], "uart6_uplldiv", NULL);
+	clk_register_clkdev(clk[UART6_ECLK_MUX], "uart6_eclk_mux", NULL);
+	clk_register_clkdev(clk[UART6_ECLK_DIV], "uart6_eclk_div", NULL);
+	clk_register_clkdev(clk[UART6_ECLK_GATE], "uart6_eclk", NULL);
+	clk_register_clkdev(clk[UART7_APLLDIV], "uart7_aplldiv", NULL);
+	clk_register_clkdev(clk[UART7_UPLLDIV], "uart7_uplldiv", NULL);
+	clk_register_clkdev(clk[UART7_ECLK_MUX], "uart7_eclk_mux", NULL);
+	clk_register_clkdev(clk[UART7_ECLK_DIV], "uart7_eclk_div", NULL);
+	clk_register_clkdev(clk[UART7_ECLK_GATE], "uart7_eclk", NULL);
+	clk_register_clkdev(clk[UART8_APLLDIV], "uart8_aplldiv", NULL);
+	clk_register_clkdev(clk[UART8_UPLLDIV], "uart8_uplldiv", NULL);
+	clk_register_clkdev(clk[UART8_ECLK_MUX], "uart8_eclk_mux", NULL);
+	clk_register_clkdev(clk[UART8_ECLK_DIV], "uart8_eclk_div", NULL);
+	clk_register_clkdev(clk[UART8_ECLK_GATE], "uart8_eclk", NULL);
+	clk_register_clkdev(clk[UART9_APLLDIV], "uart9_aplldiv", NULL);
+	clk_register_clkdev(clk[UART9_UPLLDIV], "uart9_uplldiv", NULL);
+	clk_register_clkdev(clk[UART9_ECLK_MUX], "uart9_eclk_mux", NULL);
+	clk_register_clkdev(clk[UART9_ECLK_DIV], "uart9_eclk_div", NULL);
+	clk_register_clkdev(clk[UART9_ECLK_GATE], "uart9_eclk", NULL);
+	clk_register_clkdev(clk[UART10_APLLDIV], "uart10_aplldiv", NULL);
+	clk_register_clkdev(clk[UART10_UPLLDIV], "uart10_uplldiv", NULL);
+	clk_register_clkdev(clk[UART10_ECLK_MUX], "uart10_eclk_mux", NULL);
+	clk_register_clkdev(clk[UART10_ECLK_DIV], "uart10_eclk_div", NULL);
+	clk_register_clkdev(clk[UART10_ECLK_GATE], "uart10_eclk", NULL);
+	clk_register_clkdev(clk[SYSTEM_APLLDIV], "system_aplldiv", NULL);
+	clk_register_clkdev(clk[SYSTEM_UPLLDIV], "system_uplldiv", NULL);
+	clk_register_clkdev(clk[SYSTEM_ECLK_MUX], "system_eclk_mux", NULL);
+	clk_register_clkdev(clk[SYSTEM_ECLK_DIV], "system_eclk_div", NULL);
+	clk_register_clkdev(clk[SYSTEM_ECLK_GATE], "system_eclk", NULL);
+	clk_register_clkdev(clk[GPIO_ECLK_MUX], "gpio_eclk_mux", NULL);
+	clk_register_clkdev(clk[GPIO_ECLK_DIV], "gpio_eclk_div", NULL);
+	clk_register_clkdev(clk[GPIO_ECLK_GATE], "gpio_eclk", NULL);
+	clk_register_clkdev(clk[KPI_ECLK_MUX], "kpi_eclk_mux", NULL);
+	clk_register_clkdev(clk[KPI_ECLK_DIV], "kpi_eclk_div", NULL);
+	clk_register_clkdev(clk[KPI_ECLK_GATE], "kpi_eclk", NULL);
+	clk_register_clkdev(clk[ETIMER0_ECLK_MUX], "etmr0_eclk_mux", NULL);
+	clk_register_clkdev(clk[ETIMER0_ECLK_GATE], "etmr0_eclk", NULL);
+	clk_register_clkdev(clk[ETIMER1_ECLK_MUX], "etmr1_eclk_mux", NULL);
+	clk_register_clkdev(clk[ETIMER1_ECLK_GATE], "etmr1_eclk", NULL);
+	clk_register_clkdev(clk[ETIMER2_ECLK_MUX], "etmr2_eclk_mux", NULL);
+	clk_register_clkdev(clk[ETIMER2_ECLK_GATE], "etmr2_eclk", NULL);
+	clk_register_clkdev(clk[ETIMER3_ECLK_MUX], "etmr3_eclk_mux", NULL);
+	clk_register_clkdev(clk[ETIMER3_ECLK_GATE], "etmr3_eclk", NULL);
+	clk_register_clkdev(clk[WWDT_ECLK_MUX], "wwdt_eclk_mux", NULL);
+	clk_register_clkdev(clk[WWDT_ECLK_GATE], "wwdt_eclk", NULL);
+	clk_register_clkdev(clk[WDT_ECLK_MUX], "wdt_eclk_mux", NULL);
+	clk_register_clkdev(clk[WDT_ECLK_GATE], "wdt_eclk", NULL);
+	clk_register_clkdev(clk[SMC0_ECLK_DIV], "smc0_eclk_div", NULL);
+	clk_register_clkdev(clk[SMC0_ECLK_GATE], "smc0_eclk", NULL);
+	clk_register_clkdev(clk[SMC1_ECLK_DIV], "smc1_eclk_div", NULL);
+	clk_register_clkdev(clk[SMC1_ECLK_GATE], "smc1_eclk", NULL);
+	/* PCLK */
+	clk_register_clkdev(clk[PCLK_DIV], "pclkdiv", NULL);
+	clk_register_clkdev(clk[RTC_GATE], "rtc", NULL);
+	clk_register_clkdev(clk[I2C0_GATE], "i2c0", NULL);
+	clk_register_clkdev(clk[I2C1_GATE], "i2c1", NULL);
+	clk_register_clkdev(clk[SPI0_GATE], "spi0", NULL);
+	clk_register_clkdev(clk[SPI1_GATE], "spi1", NULL);
+	clk_register_clkdev(clk[UART0_GATE], "uart0", NULL);
+	clk_register_clkdev(clk[UART1_GATE], "uart1", NULL);
+	clk_register_clkdev(clk[UART2_GATE], "uart2", NULL);
+	clk_register_clkdev(clk[UART3_GATE], "uart3", NULL);
+	clk_register_clkdev(clk[UART4_GATE], "uart4", NULL);
+	clk_register_clkdev(clk[UART5_GATE], "uart5", NULL);
+	clk_register_clkdev(clk[UART6_GATE], "uart6", NULL);
+	clk_register_clkdev(clk[UART7_GATE], "uart7", NULL);
+	clk_register_clkdev(clk[UART8_GATE], "uart8", NULL);
+	clk_register_clkdev(clk[UART9_GATE], "uart9", NULL);
+	clk_register_clkdev(clk[UART10_GATE], "uart10", NULL);
+	clk_register_clkdev(clk[WDT_GATE], "wdt", NULL);
+	clk_register_clkdev(clk[WWDT_GATE], "wwdt", NULL);
+	clk_register_clkdev(clk[GPIO_GATE], "gpio", NULL);
+	clk_register_clkdev(clk[SMC0_GATE], "smc0", NULL);
+	clk_register_clkdev(clk[SMC1_GATE], "smc1", NULL);
+	clk_register_clkdev(clk[ADC_GATE], "adc", NULL);
+	clk_register_clkdev(clk[KPI_GATE], "kpi", NULL);
+	clk_register_clkdev(clk[MTPC_GATE], "mtpc", NULL);
+	clk_register_clkdev(clk[PWM_GATE], "pwm", NULL);
+	clk_register_clkdev(clk[ETIMER0_GATE], "etimer0", NULL);
+	clk_register_clkdev(clk[ETIMER1_GATE], "etimer1", NULL);
+	clk_register_clkdev(clk[ETIMER2_GATE], "etimer2", NULL);
+	clk_register_clkdev(clk[ETIMER3_GATE], "etimer3", NULL);
+	clk_register_clkdev(clk[TIMER2_GATE], "timer2", NULL);
+	clk_register_clkdev(clk[TIMER3_GATE], "timer3", NULL);
+	clk_register_clkdev(clk[TIMER4_GATE], "timer4", NULL);
+	clk_register_clkdev(clk[CAN0_GATE], "can0", NULL);
+	clk_register_clkdev(clk[CAN1_GATE], "can1", NULL);
+
+	/* enable some important clocks */
+	clk_prepare_enable(clk_get(NULL, "cpu"));
+	clk_prepare_enable(clk_get(NULL, "hclk"));
+	clk_prepare_enable(clk_get(NULL, "sram"));
+	clk_prepare_enable(clk_get(NULL, "dram"));
+	clk_prepare_enable(clk_get(NULL, "ddr_hclk"));
+}
+
+CLK_OF_DECLARE(nuc970_clk, "nuvoton,clk", nuc970_clocks_init);
diff --git a/drivers/clk/nuc900/clk-upll.c b/drivers/clk/nuc900/clk-upll.c
new file mode 100644
index 0000000..d0c6fc2
--- /dev/null
+++ b/drivers/clk/nuc900/clk-upll.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2016 Wan Zongshun <mcuos.com@gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+
+#include "clk-ccf.h"
+
+struct clk_upll {
+	struct clk_hw	hw;
+	void __iomem	*base;
+};
+
+#define to_clk_upll(clk) (container_of(clk, struct clk_upll, clk))
+
+static unsigned long clk_upll_recalc_rate(struct clk_hw *hw,
+					  unsigned long parent_rate)
+{
+	struct clk_upll *pll = to_clk_upll(hw);
+	unsigned long rate;
+	unsigned long reg = readl(pll->base) & 0x0FFFFFFF;
+
+	if (parent_rate != 12000000)
+		return 0;
+
+	switch (reg) {
+	case 0x15:
+		rate = 264000000;
+		break;
+	case 0x18:
+		rate = 300000000;
+		break;
+	default:
+		rate = 264000000;
+		break;
+	}
+
+	return rate;
+}
+
+static struct clk_ops clk_upll_ops = {
+	.recalc_rate = clk_upll_recalc_rate,
+};
+
+struct clk *nuc970_clk_upll(const char *name, const char *parent,
+			    void __iomem *base)
+{
+	struct clk_upll *pll;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	pll = kmalloc(sizeof(*pll), GFP_KERNEL);
+	if (!pll)
+		return ERR_PTR(-ENOMEM);
+
+	pll->base = base;
+
+	init.name = name;
+	init.ops = &clk_upll_ops;
+	init.flags = 0;
+	init.parent_names = &parent;
+	init.num_parents = 1;
+
+	pll->hw.init = &init;
+
+	clk = clk_register(NULL, &pll->hw);
+	if (IS_ERR(clk))
+		kfree(pll);
+
+	return clk;
+}
-- 
2.7.4

Re: [PATCH 5/6] clk: add Clock driver for nuc970

[Arnd Bergmann]

On Saturday, June 25, 2016 6:37:21 PM CEST Wan Zongshun wrote:
> Signed-off-by: Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---

Please add a patch description.

	Arnd
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[PATCH 6/6] nuc900: add nuc970 platform defconfig file

[Wan Zongshun]

Add nuc970_defconfig file support.

Signed-off-by: Wan Zongshun <mcuos.com@gmail.com>
---
 arch/arm/configs/nuc970_defconfig | 1278 +++++++++++++++++++++++++++++++++++++
 1 file changed, 1278 insertions(+)
 create mode 100644 arch/arm/configs/nuc970_defconfig

diff --git a/arch/arm/configs/nuc970_defconfig b/arch/arm/configs/nuc970_defconfig
new file mode 100644
index 0000000..3ee776c
--- /dev/null
+++ b/arch/arm/configs/nuc970_defconfig
@@ -0,0 +1,1278 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm 4.7.0-rc3 Kernel Configuration
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_GENERIC_BUG=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_IRQ_WORK=y
+CONFIG_BUILDTIME_EXTABLE_SORT=y
+
+#
+# General setup
+#
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+# CONFIG_COMPILE_TEST is not set
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KERNEL_LZ4=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_XZ is not set
+# CONFIG_KERNEL_LZO is not set
+# CONFIG_KERNEL_LZ4 is not set
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_CROSS_MEMORY_ATTACH is not set
+CONFIG_FHANDLE=y
+# CONFIG_USELIB is not set
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+# CONFIG_IRQ_DOMAIN_DEBUG is not set
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+
+#
+# Timers subsystem
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ_COMMON=y
+# CONFIG_HZ_PERIODIC is not set
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+
+#
+# CPU/Task time and stats accounting
+#
+CONFIG_TICK_CPU_ACCOUNTING=y
+# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
+# CONFIG_IRQ_TIME_ACCOUNTING is not set
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+
+#
+# RCU Subsystem
+#
+CONFIG_PREEMPT_RCU=y
+# CONFIG_RCU_EXPERT is not set
+CONFIG_SRCU=y
+# CONFIG_TASKS_RCU is not set
+CONFIG_RCU_STALL_COMMON=y
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_RCU_EXPEDITE_BOOT is not set
+# CONFIG_BUILD_BIN2C is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_NMI_LOG_BUF_SHIFT=13
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_CGROUPS=y
+# CONFIG_MEMCG is not set
+# CONFIG_BLK_CGROUP is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_CFS_BANDWIDTH is not set
+CONFIG_RT_GROUP_SCHED=y
+# CONFIG_CGROUP_PIDS is not set
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_PERF=y
+# CONFIG_CGROUP_DEBUG is not set
+# CONFIG_CHECKPOINT_RESTORE is not set
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+# CONFIG_USER_NS is not set
+CONFIG_PID_NS=y
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="../rootfs"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_RD_LZ4=y
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_HAVE_UID16=y
+# CONFIG_EXPERT is not set
+CONFIG_UID16=y
+CONFIG_MULTIUSER=y
+# CONFIG_SGETMASK_SYSCALL is not set
+CONFIG_SYSFS_SYSCALL=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
+CONFIG_KALLSYMS_BASE_RELATIVE=y
+CONFIG_PRINTK=y
+CONFIG_PRINTK_NMI=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+# CONFIG_BPF_SYSCALL is not set
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_ADVISE_SYSCALLS=y
+# CONFIG_USERFAULTFD is not set
+CONFIG_MEMBARRIER=y
+# CONFIG_EMBEDDED is not set
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SYSTEM_DATA_VERIFICATION is not set
+# CONFIG_PROFILING is not set
+CONFIG_KEXEC_CORE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_JUMP_LABEL is not set
+# CONFIG_UPROBES is not set
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_NMI=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+# CONFIG_CC_STACKPROTECTOR is not set
+CONFIG_CC_STACKPROTECTOR_NONE=y
+# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
+# CONFIG_CC_STACKPROTECTOR_STRONG is not set
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
+CONFIG_HAVE_EXIT_THREAD=y
+CONFIG_ARCH_MMAP_RND_BITS_MIN=8
+CONFIG_ARCH_MMAP_RND_BITS_MAX=16
+CONFIG_ARCH_MMAP_RND_BITS=8
+# CONFIG_HAVE_ARCH_HASH is not set
+# CONFIG_ISA_BUS_API is not set
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OLD_SIGACTION=y
+# CONFIG_CPU_NO_EFFICIENT_FFS is not set
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_MODULE_SIG is not set
+# CONFIG_MODULE_COMPRESS is not set
+# CONFIG_TRIM_UNUSED_KSYMS is not set
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+# CONFIG_BLK_CMDLINE_PARSER is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_MULTIPLATFORM is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KS8695 is not set
+CONFIG_ARCH_W90X900=y
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C24XX is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP1 is not set
+CONFIG_SOC_NUC970=y
+
+#
+# W90P910 Machines
+#
+# CONFIG_MACH_W90P910EVB is not set
+
+#
+# NUC950 Machines
+#
+# CONFIG_MACH_W90P950EVB is not set
+
+#
+# NUC960 Machines
+#
+# CONFIG_MACH_W90N960EVB is not set
+
+#
+# NUC970 Machines
+#
+CONFIG_MACH_NUC970EVB=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_USE_DOMAINS=y
+
+#
+# Processor Features
+#
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_NEED_KUSER_HELPERS=y
+CONFIG_KUSER_HELPERS=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+# CONFIG_DEBUG_RODATA is not set
+CONFIG_MULTI_IRQ_HANDLER=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_DOMAINS_GENERIC is not set
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_3G_OPT is not set
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_ARCH_NR_GPIO=0
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_COUNT=y
+CONFIG_HZ_FIXED=0
+CONFIG_HZ_100=y
+# CONFIG_HZ_200 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_500 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=100
+CONFIG_SCHED_HRTICK=y
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_HAVE_ARCH_PFN_VALID=y
+# CONFIG_HIGHMEM is not set
+CONFIG_CPU_SW_DOMAIN_PAN=y
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+# CONFIG_ARM_MODULE_PLTS is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_NO_BOOTMEM=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+CONFIG_COMPACTION=y
+CONFIG_MIGRATION=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NEED_PER_CPU_KM=y
+# CONFIG_CLEANCACHE is not set
+# CONFIG_FRONTSWAP is not set
+# CONFIG_CMA is not set
+# CONFIG_ZPOOL is not set
+# CONFIG_ZBUD is not set
+# CONFIG_ZSMALLOC is not set
+CONFIG_GENERIC_EARLY_IOREMAP=y
+# CONFIG_IDLE_PAGE_TRACKING is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+# CONFIG_SECCOMP is not set
+CONFIG_SWIOTLB=y
+CONFIG_IOMMU_HELPER=y
+# CONFIG_PARAVIRT is not set
+# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
+
+#
+# Boot options
+#
+CONFIG_USE_OF=y
+CONFIG_ATAGS=y
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ARM_APPENDED_DTB=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_CMDLINE="root=/dev/ram0 console=ttyS0,115200n8 rdinit=/sbin/init mem=64M"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_CMDLINE_EXTEND is not set
+# CONFIG_CMDLINE_FORCE is not set
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_AUTO_ZRELADDR is not set
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# CPU Idle
+#
+# CONFIG_CPU_IDLE is not set
+# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_ELFCORE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_SCRIPT=y
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_COREDUMP=y
+
+#
+# Power management options
+#
+# CONFIG_SUSPEND is not set
+# CONFIG_HIBERNATION is not set
+# CONFIG_PM is not set
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_ARM_CPU_SUSPEND is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+# CONFIG_NET is not set
+CONFIG_HAVE_CBPF_JIT=y
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
+CONFIG_ALLOW_DEV_COREDUMP=y
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_GENERIC_CPU_DEVICES is not set
+CONFIG_SOC_BUS=y
+# CONFIG_DMA_SHARED_BUFFER is not set
+
+#
+# Bus devices
+#
+# CONFIG_ARM_CCN is not set
+# CONFIG_BRCMSTB_GISB_ARB is not set
+# CONFIG_VEXPRESS_CONFIG is not set
+# CONFIG_MTD is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+# CONFIG_OF_UNITTEST is not set
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+# CONFIG_OF_OVERLAY is not set
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_NULL_BLK is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+
+#
+# DRBD disabled because PROC_FS or INET not selected
+#
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_MG_DISK is not set
+
+#
+# Misc devices
+#
+# CONFIG_SENSORS_LIS3LV02D is not set
+# CONFIG_DUMMY_IRQ is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_SRAM is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+
+#
+# Altera FPGA firmware download module
+#
+
+#
+# Intel MIC Bus Driver
+#
+
+#
+# SCIF Bus Driver
+#
+
+#
+# VOP Bus Driver
+#
+
+#
+# Intel MIC Host Driver
+#
+
+#
+# Intel MIC Card Driver
+#
+
+#
+# SCIF Driver
+#
+
+#
+# Intel MIC Coprocessor State Management (COSM) Drivers
+#
+
+#
+# VOP Driver
+#
+# CONFIG_ECHO is not set
+# CONFIG_CXL_BASE is not set
+# CONFIG_CXL_KERNEL_API is not set
+# CONFIG_CXL_EEH is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_MQ_DEFAULT is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_NVM is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+# CONFIG_INPUT_MATRIXKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+# CONFIG_RMI4_CORE is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_TTY=y
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_TRACE_SINK is not set
+CONFIG_DEVMEM=y
+CONFIG_DEVKMEM=y
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_NUC970=y
+CONFIG_SERIAL_NUC970_CONSOLE=y
+# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_SCCNXP is not set
+# CONFIG_SERIAL_BCM63XX is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_SERIAL_MPS2_UART is not set
+# CONFIG_SERIAL_ARC is not set
+# CONFIG_SERIAL_FSL_LPUART is not set
+# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
+# CONFIG_SERIAL_ST_ASC is not set
+# CONFIG_SERIAL_STM32 is not set
+# CONFIG_HVC_DCC is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_XILLYBUS is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_SPMI is not set
+# CONFIG_HSI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+
+#
+# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
+#
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_OF_GPIO=y
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO drivers
+#
+# CONFIG_GPIO_74XX_MMIO is not set
+# CONFIG_GPIO_ALTERA is not set
+# CONFIG_GPIO_DWAPB is not set
+# CONFIG_GPIO_EM is not set
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_GRGPIO is not set
+# CONFIG_GPIO_MPC8XXX is not set
+# CONFIG_GPIO_XILINX is not set
+# CONFIG_GPIO_ZEVIO is not set
+# CONFIG_GPIO_ZX is not set
+
+#
+# MFD GPIO expanders
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_POWER_RESET is not set
+# CONFIG_POWER_AVS is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_ATMEL_FLEXCOM is not set
+# CONFIG_MFD_ATMEL_HLCDC is not set
+# CONFIG_MFD_CROS_EC is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_MFD_HI6421_PMIC is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_KEMPLD is not set
+# CONFIG_MFD_MT6397 is not set
+# CONFIG_MFD_PM8921_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_MFD_SYSCON is not set
+# CONFIG_MFD_TI_AM335X_TSCADC is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+
+#
+# ACP (Audio CoProcessor) Configuration
+#
+
+#
+# Frame buffer Devices
+#
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+
+#
+# HID support
+#
+# CONFIG_HID is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+# CONFIG_EDAC is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+
+#
+# DMABUF options
+#
+# CONFIG_SYNC_FILE is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_VIRT_DRIVERS is not set
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_MMIO is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+# CONFIG_STAGING is not set
+# CONFIG_GOLDFISH is not set
+# CONFIG_CHROME_PLATFORMS is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_COMMON_CLK=y
+
+#
+# Common Clock Framework
+#
+# CONFIG_CLK_QORIQ is not set
+# CONFIG_COMMON_CLK_NXP is not set
+# CONFIG_COMMON_CLK_PXA is not set
+# CONFIG_COMMON_CLK_PIC32 is not set
+# CONFIG_COMMON_CLK_OXNAS is not set
+
+#
+# Hardware Spinlock drivers
+#
+
+#
+# Clock Source drivers
+#
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_PROBE=y
+CONFIG_CLKSRC_MMIO=y
+# CONFIG_ARM_TIMER_SP804 is not set
+# CONFIG_ATMEL_PIT is not set
+# CONFIG_SH_TIMER_CMT is not set
+# CONFIG_SH_TIMER_MTU2 is not set
+# CONFIG_SH_TIMER_TMU is not set
+# CONFIG_EM_TIMER_STI is not set
+CONFIG_NUC900_TIMER=y
+# CONFIG_MAILBOX is not set
+# CONFIG_IOMMU_SUPPORT is not set
+
+#
+# Remoteproc drivers
+#
+# CONFIG_STE_MODEM_RPROC is not set
+
+#
+# Rpmsg drivers
+#
+
+#
+# SOC (System On Chip) specific Drivers
+#
+# CONFIG_SOC_BRCMSTB is not set
+# CONFIG_SUNXI_SRAM is not set
+# CONFIG_SOC_TI is not set
+# CONFIG_PM_DEVFREQ is not set
+# CONFIG_EXTCON is not set
+# CONFIG_MEMORY is not set
+# CONFIG_IIO is not set
+# CONFIG_PWM is not set
+CONFIG_IRQCHIP=y
+CONFIG_ARM_GIC_MAX_NR=1
+# CONFIG_IPACK_BUS is not set
+# CONFIG_RESET_CONTROLLER is not set
+# CONFIG_FMC is not set
+
+#
+# PHY Subsystem
+#
+# CONFIG_GENERIC_PHY is not set
+# CONFIG_PHY_PXA_28NM_HSIC is not set
+# CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_BCM_KONA_USB2_PHY is not set
+# CONFIG_POWERCAP is not set
+# CONFIG_MCB is not set
+
+#
+# Performance monitor support
+#
+CONFIG_ARM_PMU=y
+# CONFIG_RAS is not set
+
+#
+# Android
+#
+# CONFIG_ANDROID is not set
+# CONFIG_NVMEM is not set
+# CONFIG_STM is not set
+# CONFIG_INTEL_TH is not set
+
+#
+# FPGA Configuration Support
+#
+# CONFIG_FPGA is not set
+
+#
+# Firmware Drivers
+#
+# CONFIG_FIRMWARE_MEMMAP is not set
+# CONFIG_FW_CFG_SYSFS is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_F2FS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_MANDATORY_FILE_LOCKING=y
+# CONFIG_FS_ENCRYPTION is not set
+# CONFIG_FSNOTIFY is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+# CONFIG_FANOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+# CONFIG_OVERLAY_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_FAT_DEFAULT_UTF8 is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_PROC_CHILDREN is not set
+CONFIG_KERNFS=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ORANGEFS_FS is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX6FS_FS is not set
+CONFIG_ROMFS_FS=y
+CONFIG_ROMFS_BACKED_BY_BLOCK=y
+CONFIG_ROMFS_ON_BLOCK=y
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_MAC_ROMAN is not set
+# CONFIG_NLS_MAC_CELTIC is not set
+# CONFIG_NLS_MAC_CENTEURO is not set
+# CONFIG_NLS_MAC_CROATIAN is not set
+# CONFIG_NLS_MAC_CYRILLIC is not set
+# CONFIG_NLS_MAC_GAELIC is not set
+# CONFIG_NLS_MAC_GREEK is not set
+# CONFIG_NLS_MAC_ICELAND is not set
+# CONFIG_NLS_MAC_INUIT is not set
+# CONFIG_NLS_MAC_ROMANIAN is not set
+# CONFIG_NLS_MAC_TURKISH is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Kernel hacking
+#
+
+#
+# printk and dmesg options
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
+# CONFIG_DYNAMIC_DEBUG is not set
+
+#
+# Compile-time checks and compiler options
+#
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_DEBUG_KERNEL is not set
+
+#
+# Memory Debugging
+#
+# CONFIG_PAGE_EXTENSION is not set
+# CONFIG_PAGE_POISONING is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_DEBUG_MEMORY_INIT=y
+
+#
+# Debug Lockups and Hangs
+#
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+# CONFIG_SCHED_INFO is not set
+# CONFIG_DEBUG_TIMEKEEPING is not set
+
+#
+# Lock Debugging (spinlocks, mutexes, etc...)
+#
+# CONFIG_STACKTRACE is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+
+#
+# RCU Debugging
+#
+# CONFIG_PROVE_RCU is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=300
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+
+#
+# Runtime Testing
+#
+# CONFIG_LKDTM is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_TEST_HEXDUMP is not set
+# CONFIG_TEST_STRING_HELPERS is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_TEST_PRINTF is not set
+# CONFIG_TEST_BITMAP is not set
+# CONFIG_TEST_UUID is not set
+# CONFIG_TEST_RHASHTABLE is not set
+# CONFIG_TEST_HASH is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_TEST_LKM is not set
+# CONFIG_TEST_USER_COPY is not set
+# CONFIG_TEST_FIRMWARE is not set
+# CONFIG_TEST_UDELAY is not set
+# CONFIG_MEMTEST is not set
+# CONFIG_TEST_STATIC_KEYS is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_UBSAN is not set
+CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_IO_STRICT_DEVMEM is not set
+# CONFIG_ARM_UNWIND is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+# CONFIG_DEBUG_UART_8250 is not set
+CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h"
+# CONFIG_DEBUG_SET_MODULE_RONX is not set
+# CONFIG_CORESIGHT is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_HAVE_ARCH_BITREVERSE is not set
+CONFIG_RATIONAL=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_IO=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+# CONFIG_CRC8 is not set
+# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
+# CONFIG_RANDOM32_SELFTEST is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAS_DMA=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+# CONFIG_CORDIC is not set
+# CONFIG_DDR is not set
+# CONFIG_IRQ_POLL is not set
+CONFIG_LIBFDT=y
+# CONFIG_SG_SPLIT is not set
+CONFIG_SG_POOL=y
+# CONFIG_ARCH_HAS_SG_CHAIN is not set
+# CONFIG_VIRTUALIZATION is not set
-- 
2.7.4

Re: [PATCH 6/6] nuc900: add nuc970 platform defconfig file

[Arnd Bergmann]

On Saturday, June 25, 2016 6:37:22 PM CEST Wan Zongshun wrote:
> Add nuc970_defconfig file support.
> 
> Signed-off-by: Wan Zongshun <mcuos.com-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  arch/arm/configs/nuc970_defconfig | 1278 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 1278 insertions(+)
>  create mode 100644 arch/arm/configs/nuc970_defconfig
> 
> 

Please run 'make savedefconfig' to create a smaller file, then review every
line to see if it actually makes sense for you.

	Arnd

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Re: [PATCH 0/6] ARM: NUC900: Add NUC970 SoC support

[Arnd Bergmann]

On Saturday, June 25, 2016 6:37:16 PM CEST Wan Zongshun wrote:
> This patch series added Nuvoton new SoC NUC970 development board
> support, this nuc970 belongs to nuc900 series, but many features are
> not compatible with old nuc900 SoCs like nuc910, nuc920.
> 
> Those patches are basing on old w90x900 codes, and are using standard
> linux subsystem interface, such as dts, driver/clk, driver/clocksource
> , driver/irqchip drivers.
> 
> The old w90x900 plat such as nuc910,nuc960 codes will also be changed
> to new style according to nuc970 codes after those patches was accepted.

Looks good overall. I have a number of comments but they should
all be easy to address, and the general approach of adding this
first makes sense to me as well.

The three drivers should be merged through the respective subsystem
maintainer trees. There is one dependency with the clk header, but
we can resolve that if we merge the header along with the dts files
(actually before the dts files) so that it's possible to build the
.dtb without the clk driver being merged.
That driver in turn will not be selectable in Kconfig because it
depends on CONFIG_SOC_NUC970 (or whatever the symbol is called).

	Arnd