Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

[Fabio Estevam]

Hi Anson,

On Tue, Jan 2, 2018 at 3:07 PM, Anson Huang <Anson.Huang@nxp.com> wrote:

> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index d9b2c2d..cbda0cc 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -120,6 +120,10 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
>                         clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
>                 clk_set_parent(step_clk, secondary_sel_clk);
>                 clk_set_parent(pll1_sw_clk, step_clk);
> +               if (freq_hz > clk_get_rate(pll2_bus_clk)) {
> +                       clk_set_rate(pll1_sys_clk, new_freq * 1000);
> +                       clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> +               }

This change should be part of a different patch.

Thanks

Re: [PATCH 1/2] ARM: dts: imx6ul: add 696MHz operating point

[Fabio Estevam]

Hi Anson,

On Tue, Jan 2, 2018 at 3:07 PM, Anson Huang <Anson.Huang@nxp.com> wrote:
> Add 696MHz operating point according to datasheet
> (Rev. 0, 12/2015).

There is a newer version from 05/2017:
https://www.nxp.com/docs/en/data-sheet/IMX6ULAEC.pdf

>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
>  arch/arm/boot/dts/imx6ul.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
> index e0b4a46..86b3251 100644
> --- a/arch/arm/boot/dts/imx6ul.dtsi
> +++ b/arch/arm/boot/dts/imx6ul.dtsi
> @@ -68,12 +68,14 @@
>                         clock-latency = <61036>; /* two CLK32 periods */
>                         operating-points = <
>                                 /* kHz  uV */
> +                               696000  1275000
>                                 528000  1175000
>                                 396000  1025000
>                                 198000  950000
>                         >;
>                         fsl,soc-operating-points = <
>                                 /* KHz  uV */
> +                               696000  1275000

Why 1.275V?

According to the datasheet, the minimum value for VDD_SOC_CAP is 1.15V
for all frequencies.

Adding 25mV of margin leads to 1.175V.

Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

[Anson Huang]

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Hi, Fabio

在 2018年1月2日，22:37，Fabio Estevam <festevam@gmail.com<mailto:festevam@gmail.com>> 写道：

Hi Anson,

On Tue, Jan 2, 2018 at 3:07 PM, Anson Huang <Anson.Huang@nxp.com<mailto:Anson.Huang@nxp.com>> wrote:

diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
index d9b2c2d..cbda0cc 100644
--- a/drivers/cpufreq/imx6q-cpufreq.c
+++ b/drivers/cpufreq/imx6q-cpufreq.c
@@ -120,6 +120,10 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
                       clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
               clk_set_parent(step_clk, secondary_sel_clk);
               clk_set_parent(pll1_sw_clk, step_clk);
+               if (freq_hz > clk_get_rate(pll2_bus_clk)) {
+                       clk_set_rate(pll1_sys_clk, new_freq * 1000);
+                       clk_set_parent(pll1_sw_clk, pll1_sys_clk);
+               }

This change should be part of a different patch.

Thanks

This change is to support 696MHz operating point, both the speed grading check and pll rate change are necessary for 696MHz support, do you think they should be in different patch?

Anson.

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Re: [PATCH 1/2] ARM: dts: imx6ul: add 696MHz operating point

[Anson Huang]

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Hi, Fabio

From Anson's iPhone 6


在 2018年1月2日，23:03，Fabio Estevam <festevam@gmail.com<mailto:festevam@gmail.com>> 写道：

Hi Anson,

On Tue, Jan 2, 2018 at 3:07 PM, Anson Huang <Anson.Huang@nxp.com<mailto:Anson.Huang@nxp.com>> wrote:
Add 696MHz operating point according to datasheet
(Rev. 0, 12/2015).

There is a newer version from 05/2017:
https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.nxp.com%2Fdocs%2Fen%2Fdata-sheet%2FIMX6ULAEC.pdf&data=02%7C01%7CAnson.Huang%40nxp.com%7Cb4d52f7307584d46a56108d551f1edcc%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C636505021876487966&sdata=xmSGDY9GMYM7nW3R7mHjXrsCdppj2kS4TRKqWMZTdAI%3D&reserved=0

The 696M is introduced since Rev 0, so do you think I should use the latest version here?



Signed-off-by: Anson Huang <Anson.Huang@nxp.com<mailto:Anson.Huang@nxp.com>>
---
arch/arm/boot/dts/imx6ul.dtsi | 2 ++
1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index e0b4a46..86b3251 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -68,12 +68,14 @@
                       clock-latency = <61036>; /* two CLK32 periods */
                       operating-points = <
                               /* kHz  uV */
+                               696000  1275000
                               528000  1175000
                               396000  1025000
                               198000  950000
;
                       fsl,soc-operating-points = <
                               /* KHz  uV */
+                               696000  1275000

Why 1.275V?

According to the datasheet, the minimum value for VDD_SOC_CAP is 1.15V
for all frequencies.

Adding 25mV of margin leads to 1.175V.

There is a comment in VDD_ARM, VDD_SOC must NOT lower than VDD_ARM.

Output voltage must be set to the following rules:
• VDD_ARM_CAP <= VDD_SOC_CAP
• VDD_SOC_CAP - VDD_ARM_CAP < 330 mV

Anson.

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Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

[Fabio Estevam]

Hi Anson,

On Tue, Jan 2, 2018 at 1:05 PM, Anson Huang <anson.huang-3arQi8VN3Tc@public.gmane.org> wrote:

> This change is to support 696MHz operating point, both the speed grading
> check and pll rate change are necessary for 696MHz support, do you think
> they should be in different patch?

I thought  this could also change the behaviour for mx6q/dl/qp.

Are the others SoCs safe with this change?
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Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

[Anson Huang]

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在 2018年1月2日，23:13，Fabio Estevam <festevam@gmail.com<mailto:festevam@gmail.com>> 写道：

Hi Anson,

On Tue, Jan 2, 2018 at 1:05 PM, Anson Huang <anson.huang@nxp.com<mailto:anson.huang@nxp.com>> wrote:

This change is to support 696MHz operating point, both the speed grading
check and pll rate change are necessary for 696MHz support, do you think
they should be in different patch?

I thought  this could also change the behaviour for mx6q/dl/qp.

Are the others SoCs safe with this change?

This change is only valid for mx6ul and mx6ull, other SoCs like 6q/dl/qp are NOT impacted.

Anson.

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Re: [PATCH 1/2] ARM: dts: imx6ul: add 696MHz operating point

[Fabio Estevam]

On Tue, Jan 2, 2018 at 1:12 PM, Anson Huang <anson.huang@nxp.com> wrote:

> There is a comment in VDD_ARM, VDD_SOC must NOT lower than VDD_ARM.
>
> Output voltage must be set to the following rules:
> • VDD_ARM_CAP <= VDD_SOC_CAP
> • VDD_SOC_CAP - VDD_ARM_CAP < 330 mV

Thanks for the clarifcation.

Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

[Fabio Estevam]

On Tue, Jan 2, 2018 at 1:17 PM, Anson Huang <anson.huang-3arQi8VN3Tc@public.gmane.org> wrote:

> This change is only valid for mx6ul and mx6ull, other SoCs like 6q/dl/qp are
> NOT impacted.

Thanks for the clarification:

Reviewed-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
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[PATCH 1/2] ARM: dts: imx6ul: add 696MHz operating point

[Anson Huang]

Add 696MHz operating point according to datasheet
(Rev. 0, 12/2015).

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
 arch/arm/boot/dts/imx6ul.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index e0b4a46..86b3251 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -68,12 +68,14 @@
 			clock-latency = <61036>; /* two CLK32 periods */
 			operating-points = <
 				/* kHz	uV */
+				696000	1275000
 				528000	1175000
 				396000	1025000
 				198000	950000
 			>;
 			fsl,soc-operating-points = <
 				/* KHz	uV */
+				696000	1275000
 				528000	1175000
 				396000	1175000
 				198000	1175000
-- 
1.9.1

[PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

[Anson Huang]

Add 696MHz operating point for i.MX6UL, only for those
parts with speed grading fuse set to 2b'10 supports
696MHz operating point, so, speed grading check is also
added for i.MX6UL in this patch, the clock tree for each
operating point are as below:

696MHz:
    pll1                       696000000
       pll1_bypass             696000000
          pll1_sys             696000000
             pll1_sw           696000000
                arm            696000000
528MHz:
    pll2                       528000000
       pll2_bypass             528000000
          pll2_bus             528000000
             ca7_secondary_sel 528000000
                step           528000000
                   pll1_sw     528000000
                      arm      528000000
396MHz:
    pll2_pfd2_396m             396000000
       ca7_secondary_sel       396000000
          step                 396000000
             pll1_sw           396000000
                arm            396000000
198MHz:
    pll2_pfd2_396m             396000000
       ca7_secondary_sel       396000000
          step                 396000000
             pll1_sw           396000000
                arm            198000000

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
 drivers/cpufreq/imx6q-cpufreq.c | 46 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 45 insertions(+), 1 deletion(-)

diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
index d9b2c2d..cbda0cc 100644
--- a/drivers/cpufreq/imx6q-cpufreq.c
+++ b/drivers/cpufreq/imx6q-cpufreq.c
@@ -120,6 +120,10 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
 			clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
 		clk_set_parent(step_clk, secondary_sel_clk);
 		clk_set_parent(pll1_sw_clk, step_clk);
+		if (freq_hz > clk_get_rate(pll2_bus_clk)) {
+			clk_set_rate(pll1_sys_clk, new_freq * 1000);
+			clk_set_parent(pll1_sw_clk, pll1_sys_clk);
+		}
 	} else {
 		clk_set_parent(step_clk, pll2_pfd2_396m_clk);
 		clk_set_parent(pll1_sw_clk, step_clk);
@@ -244,6 +248,43 @@ static void imx6q_opp_check_speed_grading(struct device *dev)
 	of_node_put(np);
 }
 
+#define OCOTP_CFG3_6UL_SPEED_696MHZ	0x2
+
+static void imx6ul_opp_check_speed_grading(struct device *dev)
+{
+	struct device_node *np;
+	void __iomem *base;
+	u32 val;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
+	if (!np)
+		return;
+
+	base = of_iomap(np, 0);
+	if (!base) {
+		dev_err(dev, "failed to map ocotp\n");
+		goto put_node;
+	}
+
+	/*
+	 * Speed GRADING[1:0] defines the max speed of ARM:
+	 * 2b'00: Reserved;
+	 * 2b'01: 528000000Hz;
+	 * 2b'10: 696000000Hz;
+	 * 2b'11: Reserved;
+	 * We need to set the max speed of ARM according to fuse map.
+	 */
+	val = readl_relaxed(base + OCOTP_CFG3);
+	val >>= OCOTP_CFG3_SPEED_SHIFT;
+	val &= 0x3;
+	if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
+		if (dev_pm_opp_disable(dev, 696000000))
+			dev_warn(dev, "failed to disable 696MHz OPP\n");
+	iounmap(base);
+put_node:
+	of_node_put(np);
+}
+
 static int imx6q_cpufreq_probe(struct platform_device *pdev)
 {
 	struct device_node *np;
@@ -311,7 +352,10 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
 		goto put_reg;
 	}
 
-	imx6q_opp_check_speed_grading(cpu_dev);
+	if (of_machine_is_compatible("fsl,imx6ul"))
+		imx6ul_opp_check_speed_grading(cpu_dev);
+	else
+		imx6q_opp_check_speed_grading(cpu_dev);
 
 	/* Because we have added the OPPs here, we must free them */
 	free_opp = true;
-- 
1.9.1

RE: [PATCH 1/2] ARM: dts: imx6ul: add 696MHz operating point

[Anson Huang]

Post this discussion mail to kernel mail list, since last mail is rejected due to incorrect format, sorry for confusion. 

Best Regards!
Anson Huang


> -----Original Message-----
> From: Fabio Estevam [mailto:festevam@gmail.com]
> Sent: 2018-01-02 11:32 PM
> To: Anson Huang <anson.huang@nxp.com>
> Cc: moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE <linux-
> arm-kernel@lists.infradead.org>; open list:OPEN FIRMWARE AND FLATTENED
> DEVICE TREE BINDINGS <devicetree@vger.kernel.org>; linux-
> pm@vger.kernel.org; linux-kernel <linux-kernel@vger.kernel.org>; Mark
> Rutland <mark.rutland@arm.com>; A.s. Dong <aisheng.dong@nxp.com>; Jacky
> Bai <ping.bai@nxp.com>; viresh kumar <viresh.kumar@linaro.org>;
> rjw@rjwysocki.net; Russell King - ARM Linux <linux@armlinux.org.uk>; Rob
> Herring <robh+dt@kernel.org>; Sascha Hauer <kernel@pengutronix.de>;
> Fabio Estevam <fabio.estevam@nxp.com>; Shawn Guo
> <shawnguo@kernel.org>
> Subject: Re: [PATCH 1/2] ARM: dts: imx6ul: add 696MHz operating point
> 
> On Tue, Jan 2, 2018 at 1:12 PM, Anson Huang <anson.huang@nxp.com> wrote:
> 
> > There is a comment in VDD_ARM, VDD_SOC must NOT lower than VDD_ARM.
> >
> > Output voltage must be set to the following rules:
> > • VDD_ARM_CAP <= VDD_SOC_CAP
> > • VDD_SOC_CAP - VDD_ARM_CAP < 330 mV
> 
> Thanks for the clarifcation.
> 
> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

RE: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

[Anson Huang]

Post the discussion mail to arm kernel mail list, since last mail is rejected due to incorrect format, sorry for the confusion.

Best Regards!
Anson Huang


> -----Original Message-----
> From: Fabio Estevam [mailto:festevam@gmail.com]
> Sent: 2018-01-02 11:33 PM
> To: Anson Huang <anson.huang@nxp.com>
> Cc: moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE <linux-
> arm-kernel@lists.infradead.org>; open list:OPEN FIRMWARE AND FLATTENED
> DEVICE TREE BINDINGS <devicetree@vger.kernel.org>; linux-
> pm@vger.kernel.org; linux-kernel <linux-kernel@vger.kernel.org>; Mark
> Rutland <mark.rutland@arm.com>; A.s. Dong <aisheng.dong@nxp.com>; Jacky
> Bai <ping.bai@nxp.com>; viresh kumar <viresh.kumar@linaro.org>;
> rjw@rjwysocki.net; Russell King - ARM Linux <linux@armlinux.org.uk>; Rob
> Herring <robh+dt@kernel.org>; Sascha Hauer <kernel@pengutronix.de>;
> Fabio Estevam <fabio.estevam@nxp.com>; Shawn Guo
> <shawnguo@kernel.org>
> Subject: Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for
> i.mx6ul
> 
> On Tue, Jan 2, 2018 at 1:17 PM, Anson Huang <anson.huang@nxp.com> wrote:
> 
> > This change is only valid for mx6ul and mx6ull, other SoCs like
> > 6q/dl/qp are NOT impacted.
> 
> Thanks for the clarification:
> 
> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

[Rafael J. Wysocki]

On Tue, Jan 2, 2018 at 6:07 PM, Anson Huang <Anson.Huang-3arQi8VN3Tc@public.gmane.org> wrote:
> Add 696MHz operating point for i.MX6UL, only for those
> parts with speed grading fuse set to 2b'10 supports
> 696MHz operating point, so, speed grading check is also
> added for i.MX6UL in this patch, the clock tree for each
> operating point are as below:
>
> 696MHz:
>     pll1                       696000000
>        pll1_bypass             696000000
>           pll1_sys             696000000
>              pll1_sw           696000000
>                 arm            696000000
> 528MHz:
>     pll2                       528000000
>        pll2_bypass             528000000
>           pll2_bus             528000000
>              ca7_secondary_sel 528000000
>                 step           528000000
>                    pll1_sw     528000000
>                       arm      528000000
> 396MHz:
>     pll2_pfd2_396m             396000000
>        ca7_secondary_sel       396000000
>           step                 396000000
>              pll1_sw           396000000
>                 arm            396000000
> 198MHz:
>     pll2_pfd2_396m             396000000
>        ca7_secondary_sel       396000000
>           step                 396000000
>              pll1_sw           396000000
>                 arm            198000000
>
> Signed-off-by: Anson Huang <Anson.Huang-3arQi8VN3Tc@public.gmane.org>

This doesn't apply for me and in a nontrivial way.

What kernel is it against?

> ---
>  drivers/cpufreq/imx6q-cpufreq.c | 46 ++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 45 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index d9b2c2d..cbda0cc 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -120,6 +120,10 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
>                         clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
>                 clk_set_parent(step_clk, secondary_sel_clk);
>                 clk_set_parent(pll1_sw_clk, step_clk);
> +               if (freq_hz > clk_get_rate(pll2_bus_clk)) {
> +                       clk_set_rate(pll1_sys_clk, new_freq * 1000);
> +                       clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> +               }
>         } else {
>                 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>                 clk_set_parent(pll1_sw_clk, step_clk);
> @@ -244,6 +248,43 @@ static void imx6q_opp_check_speed_grading(struct device *dev)
>         of_node_put(np);
>  }
>
> +#define OCOTP_CFG3_6UL_SPEED_696MHZ    0x2
> +
> +static void imx6ul_opp_check_speed_grading(struct device *dev)
> +{
> +       struct device_node *np;
> +       void __iomem *base;
> +       u32 val;
> +
> +       np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
> +       if (!np)
> +               return;
> +
> +       base = of_iomap(np, 0);
> +       if (!base) {
> +               dev_err(dev, "failed to map ocotp\n");
> +               goto put_node;
> +       }
> +
> +       /*
> +        * Speed GRADING[1:0] defines the max speed of ARM:
> +        * 2b'00: Reserved;
> +        * 2b'01: 528000000Hz;
> +        * 2b'10: 696000000Hz;
> +        * 2b'11: Reserved;
> +        * We need to set the max speed of ARM according to fuse map.
> +        */
> +       val = readl_relaxed(base + OCOTP_CFG3);
> +       val >>= OCOTP_CFG3_SPEED_SHIFT;
> +       val &= 0x3;
> +       if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
> +               if (dev_pm_opp_disable(dev, 696000000))
> +                       dev_warn(dev, "failed to disable 696MHz OPP\n");
> +       iounmap(base);
> +put_node:
> +       of_node_put(np);
> +}
> +
>  static int imx6q_cpufreq_probe(struct platform_device *pdev)
>  {
>         struct device_node *np;
> @@ -311,7 +352,10 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
>                 goto put_reg;
>         }
>
> -       imx6q_opp_check_speed_grading(cpu_dev);
> +       if (of_machine_is_compatible("fsl,imx6ul"))
> +               imx6ul_opp_check_speed_grading(cpu_dev);
> +       else
> +               imx6q_opp_check_speed_grading(cpu_dev);
>
>         /* Because we have added the OPPs here, we must free them */
>         free_opp = true;
> --
> 1.9.1
>
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RE: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

[Anson Huang]

Hi, Rafael

Best Regards!
Anson Huang


> -----Original Message-----
> From: rjwysocki@gmail.com [mailto:rjwysocki@gmail.com] On Behalf Of Rafael
> J. Wysocki
> Sent: 2018-01-05 8:21 PM
> To: Anson Huang <anson.huang@nxp.com>
> Cc: linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org; Linux
> PM <linux-pm@vger.kernel.org>; Linux Kernel Mailing List <linux-
> kernel@vger.kernel.org>; Shawn Guo <shawnguo@kernel.org>; Sascha Hauer
> <kernel@pengutronix.de>; Fabio Estevam <fabio.estevam@nxp.com>; Rob
> Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>;
> Russell King - ARM Linux <linux@armlinux.org.uk>; Rafael J. Wysocki
> <rjw@rjwysocki.net>; Viresh Kumar <viresh.kumar@linaro.org>; Jacky Bai
> <ping.bai@nxp.com>; A.s. Dong <aisheng.dong@nxp.com>
> Subject: Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for
> i.mx6ul
> 
> On Tue, Jan 2, 2018 at 6:07 PM, Anson Huang <Anson.Huang@nxp.com> wrote:
> > Add 696MHz operating point for i.MX6UL, only for those parts with
> > speed grading fuse set to 2b'10 supports 696MHz operating point, so,
> > speed grading check is also added for i.MX6UL in this patch, the clock
> > tree for each operating point are as below:
> >
> > 696MHz:
> >     pll1                       696000000
> >        pll1_bypass             696000000
> >           pll1_sys             696000000
> >              pll1_sw           696000000
> >                 arm            696000000
> > 528MHz:
> >     pll2                       528000000
> >        pll2_bypass             528000000
> >           pll2_bus             528000000
> >              ca7_secondary_sel 528000000
> >                 step           528000000
> >                    pll1_sw     528000000
> >                       arm      528000000
> > 396MHz:
> >     pll2_pfd2_396m             396000000
> >        ca7_secondary_sel       396000000
> >           step                 396000000
> >              pll1_sw           396000000
> >                 arm            396000000
> > 198MHz:
> >     pll2_pfd2_396m             396000000
> >        ca7_secondary_sel       396000000
> >           step                 396000000
> >              pll1_sw           396000000
> >                 arm            198000000
> >
> > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> 
> This doesn't apply for me and in a nontrivial way.
> 
> What kernel is it against?

I did it based on linux-next, it should be on linux-next-pm branch, I redo
the patch set V2 based on linux-next-pm, also redo the test,
sorry for the inconvenience.

Anson.

> 
> > ---
> >  drivers/cpufreq/imx6q-cpufreq.c | 46
> > ++++++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 45 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/cpufreq/imx6q-cpufreq.c
> > b/drivers/cpufreq/imx6q-cpufreq.c index d9b2c2d..cbda0cc 100644
> > --- a/drivers/cpufreq/imx6q-cpufreq.c
> > +++ b/drivers/cpufreq/imx6q-cpufreq.c
> > @@ -120,6 +120,10 @@ static int imx6q_set_target(struct cpufreq_policy
> *policy, unsigned int index)
> >                         clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> >                 clk_set_parent(step_clk, secondary_sel_clk);
> >                 clk_set_parent(pll1_sw_clk, step_clk);
> > +               if (freq_hz > clk_get_rate(pll2_bus_clk)) {
> > +                       clk_set_rate(pll1_sys_clk, new_freq * 1000);
> > +                       clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> > +               }
> >         } else {
> >                 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> >                 clk_set_parent(pll1_sw_clk, step_clk); @@ -244,6
> > +248,43 @@ static void imx6q_opp_check_speed_grading(struct device *dev)
> >         of_node_put(np);
> >  }
> >
> > +#define OCOTP_CFG3_6UL_SPEED_696MHZ    0x2
> > +
> > +static void imx6ul_opp_check_speed_grading(struct device *dev) {
> > +       struct device_node *np;
> > +       void __iomem *base;
> > +       u32 val;
> > +
> > +       np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
> > +       if (!np)
> > +               return;
> > +
> > +       base = of_iomap(np, 0);
> > +       if (!base) {
> > +               dev_err(dev, "failed to map ocotp\n");
> > +               goto put_node;
> > +       }
> > +
> > +       /*
> > +        * Speed GRADING[1:0] defines the max speed of ARM:
> > +        * 2b'00: Reserved;
> > +        * 2b'01: 528000000Hz;
> > +        * 2b'10: 696000000Hz;
> > +        * 2b'11: Reserved;
> > +        * We need to set the max speed of ARM according to fuse map.
> > +        */
> > +       val = readl_relaxed(base + OCOTP_CFG3);
> > +       val >>= OCOTP_CFG3_SPEED_SHIFT;
> > +       val &= 0x3;
> > +       if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
> > +               if (dev_pm_opp_disable(dev, 696000000))
> > +                       dev_warn(dev, "failed to disable 696MHz OPP\n");
> > +       iounmap(base);
> > +put_node:
> > +       of_node_put(np);
> > +}
> > +
> >  static int imx6q_cpufreq_probe(struct platform_device *pdev)  {
> >         struct device_node *np;
> > @@ -311,7 +352,10 @@ static int imx6q_cpufreq_probe(struct
> platform_device *pdev)
> >                 goto put_reg;
> >         }
> >
> > -       imx6q_opp_check_speed_grading(cpu_dev);
> > +       if (of_machine_is_compatible("fsl,imx6ul"))
> > +               imx6ul_opp_check_speed_grading(cpu_dev);
> > +       else
> > +               imx6q_opp_check_speed_grading(cpu_dev);
> >
> >         /* Because we have added the OPPs here, we must free them */
> >         free_opp = true;
> > --
> > 1.9.1
> >

Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

[Rafael J. Wysocki]

On Saturday, January 6, 2018 4:05:41 AM CET Anson Huang wrote:
> Hi, Rafael
> 
> Best Regards!
> Anson Huang
> 
> 
> > -----Original Message-----
> > From: rjwysocki@gmail.com [mailto:rjwysocki@gmail.com] On Behalf Of Rafael
> > J. Wysocki
> > Sent: 2018-01-05 8:21 PM
> > To: Anson Huang <anson.huang@nxp.com>
> > Cc: linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org; Linux
> > PM <linux-pm@vger.kernel.org>; Linux Kernel Mailing List <linux-
> > kernel@vger.kernel.org>; Shawn Guo <shawnguo@kernel.org>; Sascha Hauer
> > <kernel@pengutronix.de>; Fabio Estevam <fabio.estevam@nxp.com>; Rob
> > Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>;
> > Russell King - ARM Linux <linux@armlinux.org.uk>; Rafael J. Wysocki
> > <rjw@rjwysocki.net>; Viresh Kumar <viresh.kumar@linaro.org>; Jacky Bai
> > <ping.bai@nxp.com>; A.s. Dong <aisheng.dong@nxp.com>
> > Subject: Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for
> > i.mx6ul
> > 
> > On Tue, Jan 2, 2018 at 6:07 PM, Anson Huang <Anson.Huang@nxp.com> wrote:
> > > Add 696MHz operating point for i.MX6UL, only for those parts with
> > > speed grading fuse set to 2b'10 supports 696MHz operating point, so,
> > > speed grading check is also added for i.MX6UL in this patch, the clock
> > > tree for each operating point are as below:
> > >
> > > 696MHz:
> > >     pll1                       696000000
> > >        pll1_bypass             696000000
> > >           pll1_sys             696000000
> > >              pll1_sw           696000000
> > >                 arm            696000000
> > > 528MHz:
> > >     pll2                       528000000
> > >        pll2_bypass             528000000
> > >           pll2_bus             528000000
> > >              ca7_secondary_sel 528000000
> > >                 step           528000000
> > >                    pll1_sw     528000000
> > >                       arm      528000000
> > > 396MHz:
> > >     pll2_pfd2_396m             396000000
> > >        ca7_secondary_sel       396000000
> > >           step                 396000000
> > >              pll1_sw           396000000
> > >                 arm            396000000
> > > 198MHz:
> > >     pll2_pfd2_396m             396000000
> > >        ca7_secondary_sel       396000000
> > >           step                 396000000
> > >              pll1_sw           396000000
> > >                 arm            198000000
> > >
> > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> > 
> > This doesn't apply for me and in a nontrivial way.
> > 
> > What kernel is it against?
> 
> I did it based on linux-next, it should be on linux-next-pm branch, I redo
> the patch set V2 based on linux-next-pm, also redo the test,
> sorry for the inconvenience.

But you didn't add the Reviewed-by: tags from Fabio to them.

Was that on purpose or by mistake?

Thanks,
Rafael

RE: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

[Anson Huang]

Best Regards!
Anson Huang


> -----Original Message-----
> From: Rafael J. Wysocki [mailto:rjw-LthD3rsA81gm4RdzfppkhA@public.gmane.org]
> Sent: 2018-01-08 7:34 AM
> To: Anson Huang <anson.huang-3arQi8VN3Tc@public.gmane.org>
> Cc: Rafael J. Wysocki <rafael-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>; linux-arm-
> kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Linux PM <linux-
> pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>; Linux Kernel Mailing List <linux-
> kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>; Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>; Sascha Hauer
> <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>; Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>; Rob
> Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>; Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>;
> Russell King - ARM Linux <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>; Viresh Kumar
> <viresh.kumar-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>; Jacky Bai <ping.bai-3arQi8VN3Tc@public.gmane.org>; A.s. Dong
> <aisheng.dong-3arQi8VN3Tc@public.gmane.org>
> Subject: Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for
> i.mx6ul
> 
> On Saturday, January 6, 2018 4:05:41 AM CET Anson Huang wrote:
> > Hi, Rafael
> >
> > Best Regards!
> > Anson Huang
> >
> >
> > > -----Original Message-----
> > > From: rjwysocki-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org [mailto:rjwysocki-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org] On Behalf Of
> > > Rafael J. Wysocki
> > > Sent: 2018-01-05 8:21 PM
> > > To: Anson Huang <anson.huang-3arQi8VN3Tc@public.gmane.org>
> > > Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org;
> > > devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Linux PM <linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>;
> > > Linux Kernel Mailing List <linux- kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>; Shawn Guo
> > > <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>; Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>; Fabio
> > > Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>; Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>;
> > > Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>; Russell King - ARM Linux
> > > <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>; Rafael J. Wysocki <rjw-LthD3rsA81gm4RdzfppkhA@public.gmane.org>;
> > > Viresh Kumar <viresh.kumar-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>; Jacky Bai
> > > <ping.bai-3arQi8VN3Tc@public.gmane.org>; A.s. Dong <aisheng.dong-3arQi8VN3Tc@public.gmane.org>
> > > Subject: Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point
> > > for i.mx6ul
> > >
> > > On Tue, Jan 2, 2018 at 6:07 PM, Anson Huang <Anson.Huang-3arQi8VN3Tc@public.gmane.org>
> wrote:
> > > > Add 696MHz operating point for i.MX6UL, only for those parts with
> > > > speed grading fuse set to 2b'10 supports 696MHz operating point,
> > > > so, speed grading check is also added for i.MX6UL in this patch,
> > > > the clock tree for each operating point are as below:
> > > >
> > > > 696MHz:
> > > >     pll1                       696000000
> > > >        pll1_bypass             696000000
> > > >           pll1_sys             696000000
> > > >              pll1_sw           696000000
> > > >                 arm            696000000
> > > > 528MHz:
> > > >     pll2                       528000000
> > > >        pll2_bypass             528000000
> > > >           pll2_bus             528000000
> > > >              ca7_secondary_sel 528000000
> > > >                 step           528000000
> > > >                    pll1_sw     528000000
> > > >                       arm      528000000
> > > > 396MHz:
> > > >     pll2_pfd2_396m             396000000
> > > >        ca7_secondary_sel       396000000
> > > >           step                 396000000
> > > >              pll1_sw           396000000
> > > >                 arm            396000000
> > > > 198MHz:
> > > >     pll2_pfd2_396m             396000000
> > > >        ca7_secondary_sel       396000000
> > > >           step                 396000000
> > > >              pll1_sw           396000000
> > > >                 arm            198000000
> > > >
> > > > Signed-off-by: Anson Huang <Anson.Huang-3arQi8VN3Tc@public.gmane.org>
> > >
> > > This doesn't apply for me and in a nontrivial way.
> > >
> > > What kernel is it against?
> >
> > I did it based on linux-next, it should be on linux-next-pm branch, I
> > redo the patch set V2 based on linux-next-pm, also redo the test,
> > sorry for the inconvenience.
> 
> But you didn't add the Reviewed-by: tags from Fabio to them.
> 
> Was that on purpose or by mistake?
> 
> Thanks,
> Rafael

It was my mistake, I thought it will be added by maintainer, I will add them and set a V3
patch set. Thanks.

Anson.
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