RE: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'

["Datta, Shubhrajyoti" <shubhrajyoti.datta@amd.com>]

[AMD Official Use Only - General]



> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Thursday, July 14, 2022 5:29 PM
> To: Michal Simek <michal.simek@xilinx.com>; Shubhrajyoti Datta
> <shubhrajyoti.datta@gmail.com>; Rob Herring <robh@kernel.org>; Krzysztof
> Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Shubhrajyoti Datta <shubhraj@xilinx.com>; linux-serial@vger.kernel.org;
> devicetree@vger.kernel.org; gregkh@linuxfoundation.org; Srinivas Goud
> <sgoud@xilinx.com>
> Subject: Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'
> 
> CAUTION: This message has originated from an External Source. Please use
> proper judgment and caution when opening attachments, clicking links, or
> responding to this email.
> 
> 
> On 14/07/2022 12:55, Michal Simek wrote:
> > Hi Rob and Krzysztof,
> >
> > On 6/14/22 14:21, Shubhrajyoti Datta wrote:
> >>>>
> >>   <snip>
> >>
> >>>
> >>> No, I don't know what the differences are in your h/w. You have ID
> >>> registers, but changed the IP and didn't change the ID registers?
> >>> How has the IP changed?
> >>>
> >>
> >> The IP is not changed and the ID registers are not updated.
> >> The limitation is coming from the AXI  port that the IP is connected to.
> >> The axi port is allowing only the 32 bit access.
> >> The same information will be updated in the Versal TRM.
> >
> > Can you please give us your recommendation how to process with this?
> 
> Unfortunately I don't think that anyone remembers context from last year,
> especially me who was not Cced. Rob responded at end of March and it took
> two months to get back any answer. Such slow response time from submitter
> does not help to stay in the context. :(

I had to contact the hardware team and get the details on the issue it took me sometime to get a response.

I will summarize 

We are using the ip from ARM but the AXI port that we hooked has a limitation that it allows only 32 bit accesses.

So to tide over the and differentiate  I am adding a new compatible arm,xlnx-uart.

> 
> 
> Best regards,
> Krzysztof