RE: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'

[Shubhrajyoti Datta <shubhraj@xilinx.com>]

> -----Original Message-----
> From: Shubhrajyoti Datta
> Sent: Friday, December 10, 2021 7:12 PM
> To: Rob Herring <robh@kernel.org>
> Cc: linux-serial@vger.kernel.org; devicetree@vger.kernel.org;
> gregkh@linuxfoundation.org; Raviteja Narayanam <rna@xlnx.xilinx.com>
> Subject: RE: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'
> 
> 
> 
> > -----Original Message-----
> > From: Rob Herring <robh@kernel.org>
> > Sent: Tuesday, November 30, 2021 3:39 AM
> > To: Shubhrajyoti Datta <shubhraj@xilinx.com>
> > Cc: linux-serial@vger.kernel.org; devicetree@vger.kernel.org;
> > gregkh@linuxfoundation.org; Raviteja Narayanam <rna@xlnx.xilinx.com>
> > Subject: Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'
> >
> > On Tue, Nov 16, 2021 at 04:47:45PM +0530, Shubhrajyoti Datta wrote:
> > > Add support for Uart used in Xilinx Versal SOCs as a platform device.
> >
> > No. Why would we want to do that?
> Apologies did not understand that.
> 
> >
> > >
> > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> > > Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
> > > ---
> > >  Documentation/devicetree/bindings/serial/pl011.yaml | 10 +++++++---
> > >  1 file changed, 7 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml
> > > b/Documentation/devicetree/bindings/serial/pl011.yaml
> > > index 5ea00f8a283d..6c73923dd15e 100644
> > > --- a/Documentation/devicetree/bindings/serial/pl011.yaml
> > > +++ b/Documentation/devicetree/bindings/serial/pl011.yaml
> > > @@ -24,9 +24,13 @@ select:
> > >
> > >  properties:
> > >    compatible:
> > > -    items:
> > > -      - const: arm,pl011
> > > -      - const: arm,primecell
> > > +    oneOf:
> > > +      - items:
> > > +          - const: arm,pl011
> > > +          - const: arm,primecell
> > > +      - items:
> > > +          - const: arm,pl011
> > > +          - const: arm,xlnx-uart # xilinx uart as platform device
> >
> > 'arm,primecell' means the block has ID registers. Are you saying this
> > implementation doesn't?
> 
> The ID registers do not have any Xilinx specific identifiers.
> However there are differences  like 32-bit access.

Hope that the current approach is fine with you.

Thanks 
> >
> > >
> > >    reg:
> > >      maxItems: 1
> > > --
> > > 2.25.1
> > >
> > >