From: Daniel Baluta <daniel.baluta@gmail.com>
To: Nicolin Chen <nicoleotsuka@gmail.com>
Cc: Daniel Baluta <daniel.baluta@nxp.com>,
Mark Brown <broonie@kernel.org>,
Lucas Stach <l.stach@pengutronix.de>,
Mihai Serban <mihai.serban@gmail.com>,
Linux-ALSA <alsa-devel@alsa-project.org>,
Viorel Suman <viorel.suman@nxp.com>,
Timur Tabi <timur@kernel.org>,
"S.j. Wang" <shengjiu.wang@nxp.com>,
"Angus Ainslie (Purism)" <angus@akkea.ca>,
Takashi Iwai <tiwai@suse.com>, dl-linux-imx <linux-imx@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Devicetree List <devicetree@vger.kernel.org>,
Rob Herring <robh@kernel.org>
Subject: Re: [PATCH v2 3/7] ASoC: fsl_sai: Add support to enable multiple data lines
Date: Tue, 6 Aug 2019 18:23:27 +0300 [thread overview]
Message-ID: <CAEnQRZBN5Y+75cpgS2h3LwDj5BkF5cesqu6=V3GuPU4=5pgn6A@mail.gmail.com> (raw)
In-Reply-To: <20190729202154.GC20594@Asurada-Nvidia.nvidia.com>
On Mon, Jul 29, 2019 at 11:22 PM Nicolin Chen <nicoleotsuka@gmail.com> wrote:
>
> On Sun, Jul 28, 2019 at 10:24:25PM +0300, Daniel Baluta wrote:
> > SAI supports up to 8 Rx/Tx data lines which can be enabled
> > using TCE/RCE bits of TCR3/RCR3 registers.
> >
> > Data lines to be enabled are read from DT fsl,dl-mask property.
> > By default (if no DT entry is provided) only data line 0 is enabled.
> >
> > Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
> > ---
> > sound/soc/fsl/fsl_sai.c | 11 ++++++++++-
> > sound/soc/fsl/fsl_sai.h | 4 +++-
> > 2 files changed, 13 insertions(+), 2 deletions(-)
> >
> > diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
> > index 637b1d12a575..5e7cb7fd29f5 100644
> > --- a/sound/soc/fsl/fsl_sai.c
> > +++ b/sound/soc/fsl/fsl_sai.c
> > @@ -601,7 +601,7 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
> >
> > regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx),
> > FSL_SAI_CR3_TRCE_MASK,
> > - FSL_SAI_CR3_TRCE);
> > + FSL_SAI_CR3_TRCE(sai->soc_data->dl_mask[tx]);
> >
> > ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
> > SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
> > @@ -888,6 +888,15 @@ static int fsl_sai_probe(struct platform_device *pdev)
> > }
> > }
> >
> > + /*
> > + * active data lines mask for TX/RX, defaults to 1 (only the first
> > + * data line is enabled
> > + */
> > + sai->dl_mask[RX] = 1;
> > + sai->dl_mask[TX] = 1;
> > + of_property_read_u32_index(np, "fsl,dl-mask", RX, &sai->dl_mask[RX]);
> > + of_property_read_u32_index(np, "fsl,dl-mask", TX, &sai->dl_mask[TX]);
>
> Just curious what if we enable 8 data lines through DT bindings
> while an audio file only has 1 or 2 channels. Will TRCE bits be
> okay to stay with 8 data channels configurations? Btw, how does
> DMA work for the data registers? ESAI has one entry at a fixed
> address for all data channels while SAI seems to have different
> data registers.
Hi Nicolin,
I have sent v3 and removed this patch from the series because we
need to find a better solution.
I think we should enable TCE based on the number of available datalines
and the number of active channels. Will come with a RFC patch later.
Pasting here the reply of SAI Audio IP owner regarding to your question above,
just for anyone to have more info of our private discussion:
If all 8 datalines are enabled using TCE then the transmit FIFO for
all 8 datalines need to be serviced, otherwise a FIFO underrun will be
generated.
Each dataline has a separate transmit FIFO with a separate register to
service the FIFO, so each dataline can be serviced separately. Note
that configuring FCOMB=2 would make it look like ESAI with a common
address for all FIFOs.
When performing DMA transfers to multiple datalines, there are a
couple of options:
* Use 1 DMA channel to copy first slot for each dataline to each
FIFO and then update the destination address back to the first
register.
* Configure separate DMA channel for each dataline and trigger the
first one by the DMA request and the subsequent channels by DMA
linking or scatter/gather.
* Configure FCOMB=2 and treat it the same as the ESAI. This is
almost the same as 1, but don’t need to update the destination
address.
Thanks,
Daniel.
next prev parent reply other threads:[~2019-08-06 15:23 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-28 19:24 [PATCH v2 0/7] Add support for new SAI IP version Daniel Baluta
2019-07-28 19:24 ` [PATCH v2 1/7] ASoC: fsl_sai: Add registers definition for multiple datalines Daniel Baluta
2019-07-29 19:42 ` Nicolin Chen
2019-07-29 19:57 ` [alsa-devel] " Daniel Baluta
2019-07-29 20:20 ` Mark Brown
2019-07-30 7:59 ` Nicolin Chen
2019-08-06 11:15 ` Daniel Baluta
2019-08-07 1:12 ` Nicolin Chen
2019-07-28 19:24 ` [PATCH v2 2/7] ASoC: fsl_sai: Update Tx/Rx channel enable mask Daniel Baluta
2019-07-28 19:24 ` [PATCH v2 3/7] ASoC: fsl_sai: Add support to enable multiple data lines Daniel Baluta
2019-07-29 20:21 ` Nicolin Chen
2019-08-06 15:23 ` Daniel Baluta [this message]
2019-08-07 1:14 ` Nicolin Chen
2019-07-28 19:24 ` [PATCH v2 4/7] ASoC: dt-bindings: Document dl-mask property Daniel Baluta
2019-07-29 20:15 ` Nicolin Chen
2019-07-29 20:27 ` Daniel Baluta
2019-07-28 19:24 ` [PATCH v2 5/7] ASoC: fsl_sai: Add support for SAI new version Daniel Baluta
2019-07-28 19:24 ` [PATCH v2 6/7] ASoC: fsl_sai: Add support for imx7ulp/imx8mq Daniel Baluta
2019-07-30 8:05 ` Nicolin Chen
2019-07-28 19:24 ` [PATCH v2 7/7] ASoC: dt-bindings: Introduce compatible strings for 7ULP and 8MQ Daniel Baluta
2019-07-30 8:01 ` Nicolin Chen
2019-07-30 12:02 ` [alsa-devel] " Daniel Baluta
2019-07-30 12:04 ` Mark Brown
2019-07-30 12:10 ` Daniel Baluta
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAEnQRZBN5Y+75cpgS2h3LwDj5BkF5cesqu6=V3GuPU4=5pgn6A@mail.gmail.com' \
--to=daniel.baluta@gmail.com \
--cc=alsa-devel@alsa-project.org \
--cc=angus@akkea.ca \
--cc=broonie@kernel.org \
--cc=daniel.baluta@nxp.com \
--cc=devicetree@vger.kernel.org \
--cc=festevam@gmail.com \
--cc=kernel@pengutronix.de \
--cc=l.stach@pengutronix.de \
--cc=linux-imx@nxp.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mihai.serban@gmail.com \
--cc=nicoleotsuka@gmail.com \
--cc=robh@kernel.org \
--cc=shengjiu.wang@nxp.com \
--cc=timur@kernel.org \
--cc=tiwai@suse.com \
--cc=viorel.suman@nxp.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).