* [PATCH v2] eeprom: at25: Add DT support for EEPROMs with odd address bits
@ 2017-12-08 13:46 Geert Uytterhoeven
[not found] ` <1512740801-21142-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
0 siblings, 1 reply; 3+ messages in thread
From: Geert Uytterhoeven @ 2017-12-08 13:46 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Arnd Bergmann, Greg Kroah-Hartman, Ivo Sieben
Cc: Wolfram Sang, devicetree, linux-kernel, Geert Uytterhoeven
Certain EEPROMS have a size that is larger than the number of address
bytes would allow, and store the MSB of the address in bit 3 of the
instruction byte.
This can be described in platform data using EE_INSTR_BIT3_IS_ADDR, or
in DT using the obsolete legacy "at25,addr-mode" property.
But currently there exists no non-deprecated way to describe this in DT.
Hence extend the existing "address-width" DT property to allow
specifying 9 address bits, and enable support for that in the driver.
This has been tested with a Microchip 25LC040A.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2:
- Do not consider odd address widths of 17 or 25 bits,
- Move handling inside the switch() statement.
---
Documentation/devicetree/bindings/eeprom/at25.txt | 4 +++-
drivers/misc/eeprom/at25.c | 3 +++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/eeprom/at25.txt b/Documentation/devicetree/bindings/eeprom/at25.txt
index e823d90b802f7f8f..b3bde97dc19913ea 100644
--- a/Documentation/devicetree/bindings/eeprom/at25.txt
+++ b/Documentation/devicetree/bindings/eeprom/at25.txt
@@ -11,7 +11,9 @@ Required properties:
- spi-max-frequency : max spi frequency to use
- pagesize : size of the eeprom page
- size : total eeprom size in bytes
-- address-width : number of address bits (one of 8, 16, or 24)
+- address-width : number of address bits (one of 8, 9, 16, or 24).
+ For 9 bits, the MSB of the address is sent as bit 3 of the instruction
+ byte, before the address byte.
Optional properties:
- spi-cpha : SPI shifted clock phase, as per spi-bus bindings.
diff --git a/drivers/misc/eeprom/at25.c b/drivers/misc/eeprom/at25.c
index 5afe4cd165699060..9282ffd607ff2799 100644
--- a/drivers/misc/eeprom/at25.c
+++ b/drivers/misc/eeprom/at25.c
@@ -276,6 +276,9 @@ static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip)
return -ENODEV;
}
switch (val) {
+ case 9:
+ chip->flags |= EE_INSTR_BIT3_IS_ADDR;
+ /* fall through */
case 8:
chip->flags |= EE_ADDR1;
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2] eeprom: at25: Add DT support for EEPROMs with odd address bits
[not found] ` <1512740801-21142-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
@ 2017-12-12 20:54 ` Rob Herring
2017-12-13 10:37 ` Ivo Sieben
0 siblings, 1 reply; 3+ messages in thread
From: Rob Herring @ 2017-12-12 20:54 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Mark Rutland, Arnd Bergmann, Greg Kroah-Hartman, Ivo Sieben,
Wolfram Sang, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On Fri, Dec 08, 2017 at 02:46:41PM +0100, Geert Uytterhoeven wrote:
> Certain EEPROMS have a size that is larger than the number of address
> bytes would allow, and store the MSB of the address in bit 3 of the
> instruction byte.
>
> This can be described in platform data using EE_INSTR_BIT3_IS_ADDR, or
> in DT using the obsolete legacy "at25,addr-mode" property.
> But currently there exists no non-deprecated way to describe this in DT.
>
> Hence extend the existing "address-width" DT property to allow
> specifying 9 address bits, and enable support for that in the driver.
>
> This has been tested with a Microchip 25LC040A.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
> ---
> v2:
> - Do not consider odd address widths of 17 or 25 bits,
> - Move handling inside the switch() statement.
> ---
> Documentation/devicetree/bindings/eeprom/at25.txt | 4 +++-
> drivers/misc/eeprom/at25.c | 3 +++
> 2 files changed, 6 insertions(+), 1 deletion(-)
Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] eeprom: at25: Add DT support for EEPROMs with odd address bits
2017-12-12 20:54 ` Rob Herring
@ 2017-12-13 10:37 ` Ivo Sieben
0 siblings, 0 replies; 3+ messages in thread
From: Ivo Sieben @ 2017-12-13 10:37 UTC (permalink / raw)
To: Rob Herring
Cc: Geert Uytterhoeven, Mark Rutland, Arnd Bergmann,
Greg Kroah-Hartman, Wolfram Sang, devicetree, LKML
2017-12-12 21:54 GMT+01:00 Rob Herring <robh@kernel.org>:
> On Fri, Dec 08, 2017 at 02:46:41PM +0100, Geert Uytterhoeven wrote:
>> Certain EEPROMS have a size that is larger than the number of address
>> bytes would allow, and store the MSB of the address in bit 3 of the
>> instruction byte.
>>
>> This can be described in platform data using EE_INSTR_BIT3_IS_ADDR, or
>> in DT using the obsolete legacy "at25,addr-mode" property.
>> But currently there exists no non-deprecated way to describe this in DT.
>>
>> Hence extend the existing "address-width" DT property to allow
>> specifying 9 address bits, and enable support for that in the driver.
>>
>> This has been tested with a Microchip 25LC040A.
>>
>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>> ---
>> v2:
>> - Do not consider odd address widths of 17 or 25 bits,
>> - Move handling inside the switch() statement.
>> ---
>> Documentation/devicetree/bindings/eeprom/at25.txt | 4 +++-
>> drivers/misc/eeprom/at25.c | 3 +++
>> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Ivo Sieben <meltedpianoman@gmail.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2017-12-08 13:46 [PATCH v2] eeprom: at25: Add DT support for EEPROMs with odd address bits Geert Uytterhoeven
[not found] ` <1512740801-21142-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
2017-12-12 20:54 ` Rob Herring
2017-12-13 10:37 ` Ivo Sieben
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