* [PATCH v12 0/5] clk: clocking-wizard: Driver updates @ 2021-08-10 7:25 Shubhrajyoti Datta 2021-08-10 7:25 ` [PATCH v12 1/5] dt-bindings: add documentation of xilinx clocking wizard Shubhrajyoti Datta ` (5 more replies) 0 siblings, 6 replies; 10+ messages in thread From: Shubhrajyoti Datta @ 2021-08-10 7:25 UTC (permalink / raw) To: linux-clk, git; +Cc: devicetree, shubhrajyoti.datta, Shubhrajyoti Datta The patch does the following Update the versions of the clocking wizard ip. Move from staging to clk directory. Update the bindings. v12: No change. Rebased Shubhrajyoti Datta (5): dt-bindings: add documentation of xilinx clocking wizard clk: clocking-wizard: Add the clockwizard to clk directory clk: clocking-wizard: Rename nr-outputs to xlnx,nr-outputs clk: clocking-wizard: Fix the reconfig for 5.2 clk: clocking-wizard: Update the compatible .../bindings/clock/xlnx,clocking-wizard.yaml | 77 +++ drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-xlnx-clock-wizard.c | 643 ++++++++++++++++++ 4 files changed, 730 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml create mode 100644 drivers/clk/clk-xlnx-clock-wizard.c -- 2.17.1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v12 1/5] dt-bindings: add documentation of xilinx clocking wizard 2021-08-10 7:25 [PATCH v12 0/5] clk: clocking-wizard: Driver updates Shubhrajyoti Datta @ 2021-08-10 7:25 ` Shubhrajyoti Datta 2021-08-17 19:52 ` Rob Herring 2021-08-10 7:25 ` [PATCH v12 2/5] clk: clocking-wizard: Add the clockwizard to clk directory Shubhrajyoti Datta ` (4 subsequent siblings) 5 siblings, 1 reply; 10+ messages in thread From: Shubhrajyoti Datta @ 2021-08-10 7:25 UTC (permalink / raw) To: linux-clk, git; +Cc: devicetree, shubhrajyoti.datta, Shubhrajyoti Datta Add the devicetree binding for the xilinx clocking wizard. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> --- v6: Fix a yaml warning v7: Add vendor prefix speed-grade v8: Fix the warnings v10: Add nr-outputs v11: add the compatibles for various versions rename nr-outputs to xlnx,nr-outputs v12: No change .../bindings/clock/xlnx,clocking-wizard.yaml | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml new file mode 100644 index 000000000000..74a121988e92 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Xilinx clocking wizard + +maintainers: + - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> + +description: + The clocking wizard is a soft ip clocking block of Xilinx versal. It + reads required input clock frequencies from the devicetree and acts as clock + clock output. + +properties: + compatible: + enum: + - xlnx,clocking-wizard + - xlnx,clocking-wizard-v5-2 # version 5.2 + - xlnx,clocking-wizard-v6-0 # version 6.0 + + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + items: + - description: clock input + - description: axi clock + + clock-names: + items: + - const: clk_in1 + - const: s_axi_aclk + + + xlnx,speed-grade: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + description: + Speed grade of the device. Higher the speed grade faster is the FPGA device. + + xlnx,nr-outputs: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 8 + description: + Number of outputs. + +required: + - compatible + - reg + - "#clock-cells" + - clocks + - clock-names + - xlnx,speed-grade + - xlnx,nr-outputs + +additionalProperties: false + +examples: + - | + clock-controller@b0000000 { + compatible = "xlnx,clocking-wizard"; + reg = <0xb0000000 0x10000>; + #clock-cells = <1>; + xlnx,speed-grade = <1>; + xlnx,nr-outputs = <6>; + clock-names = "clk_in1", "s_axi_aclk"; + clocks = <&clkc 15>, <&clkc 15>; + }; +... -- 2.17.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v12 1/5] dt-bindings: add documentation of xilinx clocking wizard 2021-08-10 7:25 ` [PATCH v12 1/5] dt-bindings: add documentation of xilinx clocking wizard Shubhrajyoti Datta @ 2021-08-17 19:52 ` Rob Herring 2021-08-19 10:27 ` Shubhrajyoti Datta 0 siblings, 1 reply; 10+ messages in thread From: Rob Herring @ 2021-08-17 19:52 UTC (permalink / raw) To: Shubhrajyoti Datta; +Cc: linux-clk, git, devicetree, shubhrajyoti.datta On Tue, Aug 10, 2021 at 12:55:29PM +0530, Shubhrajyoti Datta wrote: > Add the devicetree binding for the xilinx clocking wizard. > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > --- > v6: > Fix a yaml warning > v7: > Add vendor prefix speed-grade > v8: > Fix the warnings > v10: > Add nr-outputs > v11: > add the compatibles for various versions > rename nr-outputs to xlnx,nr-outputs > v12: > No change > > .../bindings/clock/xlnx,clocking-wizard.yaml | 77 +++++++++++++++++++ > 1 file changed, 77 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > > diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > new file mode 100644 > index 000000000000..74a121988e92 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > @@ -0,0 +1,77 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Xilinx clocking wizard > + > +maintainers: > + - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > + > +description: > + The clocking wizard is a soft ip clocking block of Xilinx versal. It > + reads required input clock frequencies from the devicetree and acts as clock > + clock output. > + > +properties: > + compatible: > + enum: > + - xlnx,clocking-wizard What version is this one? > + - xlnx,clocking-wizard-v5-2 # version 5.2 > + - xlnx,clocking-wizard-v6-0 # version 6.0 The comment is pretty pointless. And periods are allowed in compatible strings, so just do '-v5.2'. > + > + > + reg: > + maxItems: 1 > + > + "#clock-cells": > + const: 1 > + > + clocks: > + items: > + - description: clock input > + - description: axi clock > + > + clock-names: > + items: > + - const: clk_in1 > + - const: s_axi_aclk > + > + > + xlnx,speed-grade: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [1, 2, 3] > + description: > + Speed grade of the device. Higher the speed grade faster is the FPGA device. > + > + xlnx,nr-outputs: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 1 > + maximum: 8 > + description: > + Number of outputs. > + > +required: > + - compatible > + - reg > + - "#clock-cells" > + - clocks > + - clock-names > + - xlnx,speed-grade > + - xlnx,nr-outputs > + > +additionalProperties: false > + > +examples: > + - | > + clock-controller@b0000000 { > + compatible = "xlnx,clocking-wizard"; > + reg = <0xb0000000 0x10000>; > + #clock-cells = <1>; > + xlnx,speed-grade = <1>; > + xlnx,nr-outputs = <6>; > + clock-names = "clk_in1", "s_axi_aclk"; > + clocks = <&clkc 15>, <&clkc 15>; > + }; > +... > -- > 2.17.1 > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v12 1/5] dt-bindings: add documentation of xilinx clocking wizard 2021-08-17 19:52 ` Rob Herring @ 2021-08-19 10:27 ` Shubhrajyoti Datta 0 siblings, 0 replies; 10+ messages in thread From: Shubhrajyoti Datta @ 2021-08-19 10:27 UTC (permalink / raw) To: Rob Herring Cc: Shubhrajyoti Datta, linux-clk, git, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS On Wed, Aug 18, 2021 at 1:22 AM Rob Herring <robh@kernel.org> wrote: > > On Tue, Aug 10, 2021 at 12:55:29PM +0530, Shubhrajyoti Datta wrote: > > Add the devicetree binding for the xilinx clocking wizard. > > > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > > --- > > v6: > > Fix a yaml warning > > v7: > > Add vendor prefix speed-grade > > v8: > > Fix the warnings > > v10: > > Add nr-outputs > > v11: > > add the compatibles for various versions > > rename nr-outputs to xlnx,nr-outputs > > v12: > > No change > > > > .../bindings/clock/xlnx,clocking-wizard.yaml | 77 +++++++++++++++++++ > > 1 file changed, 77 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > > > > diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > > new file mode 100644 > > index 000000000000..74a121988e92 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > > @@ -0,0 +1,77 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#" > > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > > + > > +title: Xilinx clocking wizard > > + > > +maintainers: > > + - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > > + > > +description: > > + The clocking wizard is a soft ip clocking block of Xilinx versal. It > > + reads required input clock frequencies from the devicetree and acts as clock > > + clock output. > > + > > +properties: > > + compatible: > > + enum: > > + - xlnx,clocking-wizard > > What version is this one? This is kept for backward compatibility the current driver expects this string > > > + - xlnx,clocking-wizard-v5-2 # version 5.2 > > + - xlnx,clocking-wizard-v6-0 # version 6.0 > > The comment is pretty pointless. And periods are allowed in compatible > strings, so just do '-v5.2'. sure will do. > > > + > > + > > + reg: > > + maxItems: 1 > > + ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v12 2/5] clk: clocking-wizard: Add the clockwizard to clk directory 2021-08-10 7:25 [PATCH v12 0/5] clk: clocking-wizard: Driver updates Shubhrajyoti Datta 2021-08-10 7:25 ` [PATCH v12 1/5] dt-bindings: add documentation of xilinx clocking wizard Shubhrajyoti Datta @ 2021-08-10 7:25 ` Shubhrajyoti Datta 2021-08-24 9:51 ` Geert Uytterhoeven 2021-08-10 7:25 ` [PATCH v12 3/5] clk: clocking-wizard: Rename nr-outputs to xlnx,nr-outputs Shubhrajyoti Datta ` (3 subsequent siblings) 5 siblings, 1 reply; 10+ messages in thread From: Shubhrajyoti Datta @ 2021-08-10 7:25 UTC (permalink / raw) To: linux-clk, git; +Cc: devicetree, shubhrajyoti.datta, Shubhrajyoti Datta Add clocking wizard driver to clk. And delete the driver from the staging as it is in drivers/clk. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> --- drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-xlnx-clock-wizard.c | 635 ++++++++++++++++++++++++++++ 3 files changed, 645 insertions(+) create mode 100644 drivers/clk/clk-xlnx-clock-wizard.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index e873f9ea2e65..22817be89bd8 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -390,6 +390,15 @@ config COMMON_CLK_K210 help Support for the Canaan Kendryte K210 RISC-V SoC clocks. +config COMMON_CLK_XLNX_CLKWZRD + tristate "Xilinx Clocking Wizard" + depends on COMMON_CLK && OF + help + Support for the Xilinx Clocking Wizard IP core clock generator. + Adds support for clocking wizard and compatible. + This driver supports the Xilinx clocking wizard programmable clock + synthesizer. The number of output is configurable in the design. + source "drivers/clk/actions/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/baikal-t1/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 2b91d34c582b..15a75aa3f351 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -68,6 +68,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o +obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o # please keep this section sorted lexicographically by directory path name obj-y += actions/ diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c new file mode 100644 index 000000000000..ec377f0d569b --- /dev/null +++ b/drivers/clk/clk-xlnx-clock-wizard.c @@ -0,0 +1,635 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx 'Clocking Wizard' driver + * + * Copyright (C) 2013 - 2021 Xilinx + * + * Sören Brinkmann <soren.brinkmann@xilinx.com> + * + */ + +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/module.h> +#include <linux/err.h> +#include <linux/iopoll.h> + +#define WZRD_NUM_OUTPUTS 7 +#define WZRD_ACLK_MAX_FREQ 250000000UL + +#define WZRD_CLK_CFG_REG(n) (0x200 + 4 * (n)) + +#define WZRD_CLKOUT0_FRAC_EN BIT(18) +#define WZRD_CLKFBOUT_FRAC_EN BIT(26) + +#define WZRD_CLKFBOUT_MULT_SHIFT 8 +#define WZRD_CLKFBOUT_MULT_MASK (0xff << WZRD_CLKFBOUT_MULT_SHIFT) +#define WZRD_CLKFBOUT_FRAC_SHIFT 16 +#define WZRD_CLKFBOUT_FRAC_MASK (0x3ff << WZRD_CLKFBOUT_FRAC_SHIFT) +#define WZRD_DIVCLK_DIVIDE_SHIFT 0 +#define WZRD_DIVCLK_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT) +#define WZRD_CLKOUT_DIVIDE_SHIFT 0 +#define WZRD_CLKOUT_DIVIDE_WIDTH 8 +#define WZRD_CLKOUT_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT) +#define WZRD_CLKOUT_FRAC_SHIFT 8 +#define WZRD_CLKOUT_FRAC_MASK 0x3ff + +#define WZRD_DR_MAX_INT_DIV_VALUE 255 +#define WZRD_DR_STATUS_REG_OFFSET 0x04 +#define WZRD_DR_LOCK_BIT_MASK 0x00000001 +#define WZRD_DR_INIT_REG_OFFSET 0x25C +#define WZRD_DR_DIV_TO_PHASE_OFFSET 4 +#define WZRD_DR_BEGIN_DYNA_RECONF 0x03 + +#define WZRD_USEC_POLL 10 +#define WZRD_TIMEOUT_POLL 1000 +/* Get the mask from width */ +#define div_mask(width) ((1 << (width)) - 1) + +/* Extract divider instance from clock hardware instance */ +#define to_clk_wzrd_divider(_hw) container_of(_hw, struct clk_wzrd_divider, hw) + +enum clk_wzrd_int_clks { + wzrd_clk_mul, + wzrd_clk_mul_div, + wzrd_clk_mul_frac, + wzrd_clk_int_max +}; + +/** + * struct clk_wzrd - Clock wizard private data structure + * + * @clk_data: Clock data + * @nb: Notifier block + * @base: Memory base + * @clk_in1: Handle to input clock 'clk_in1' + * @axi_clk: Handle to input clock 's_axi_aclk' + * @clks_internal: Internal clocks + * @clkout: Output clocks + * @speed_grade: Speed grade of the device + * @suspended: Flag indicating power state of the device + */ +struct clk_wzrd { + struct clk_onecell_data clk_data; + struct notifier_block nb; + void __iomem *base; + struct clk *clk_in1; + struct clk *axi_clk; + struct clk *clks_internal[wzrd_clk_int_max]; + struct clk *clkout[WZRD_NUM_OUTPUTS]; + unsigned int speed_grade; + bool suspended; +}; + +/** + * struct clk_wzrd_divider - clock divider specific to clk_wzrd + * + * @hw: handle between common and hardware-specific interfaces + * @base: base address of register containing the divider + * @offset: offset address of register containing the divider + * @shift: shift to the divider bit field + * @width: width of the divider bit field + * @flags: clk_wzrd divider flags + * @table: array of value/divider pairs, last entry should have div = 0 + * @lock: register lock + */ +struct clk_wzrd_divider { + struct clk_hw hw; + void __iomem *base; + u16 offset; + u8 shift; + u8 width; + u8 flags; + const struct clk_div_table *table; + spinlock_t *lock; /* divider lock */ +}; + +#define to_clk_wzrd(_nb) container_of(_nb, struct clk_wzrd, nb) + +/* maximum frequencies for input/output clocks per speed grade */ +static const unsigned long clk_wzrd_max_freq[] = { + 800000000UL, + 933000000UL, + 1066000000UL +}; + +/* spin lock variable for clk_wzrd */ +static DEFINE_SPINLOCK(clkwzrd_lock); + +static unsigned long clk_wzrd_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); + void __iomem *div_addr = divider->base + divider->offset; + unsigned int val; + + val = readl(div_addr) >> divider->shift; + val &= div_mask(divider->width); + + return divider_recalc_rate(hw, parent_rate, val, divider->table, + divider->flags, divider->width); +} + +static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + int err; + u32 value; + unsigned long flags = 0; + struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); + void __iomem *div_addr = divider->base + divider->offset; + + if (divider->lock) + spin_lock_irqsave(divider->lock, flags); + else + __acquire(divider->lock); + + value = DIV_ROUND_CLOSEST(parent_rate, rate); + + /* Cap the value to max */ + min_t(u32, value, WZRD_DR_MAX_INT_DIV_VALUE); + + /* Set divisor and clear phase offset */ + writel(value, div_addr); + writel(0x00, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET); + + /* Check status register */ + err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, + value, value & WZRD_DR_LOCK_BIT_MASK, + WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); + if (err) + goto err_reconfig; + + /* Initiate reconfiguration */ + writel(WZRD_DR_BEGIN_DYNA_RECONF, + divider->base + WZRD_DR_INIT_REG_OFFSET); + + /* Check status register */ + err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, + value, value & WZRD_DR_LOCK_BIT_MASK, + WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); +err_reconfig: + if (divider->lock) + spin_unlock_irqrestore(divider->lock, flags); + else + __release(divider->lock); + return err; +} + +static long clk_wzrd_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + u8 div; + + /* + * since we don't change parent rate we just round rate to closest + * achievable + */ + div = DIV_ROUND_CLOSEST(*prate, rate); + + return *prate / div; +} + +static const struct clk_ops clk_wzrd_clk_divider_ops = { + .round_rate = clk_wzrd_round_rate, + .set_rate = clk_wzrd_dynamic_reconfig, + .recalc_rate = clk_wzrd_recalc_rate, +}; + +static unsigned long clk_wzrd_recalc_ratef(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned int val; + u32 div, frac; + struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); + void __iomem *div_addr = divider->base + divider->offset; + + val = readl(div_addr); + div = val & div_mask(divider->width); + frac = (val >> WZRD_CLKOUT_FRAC_SHIFT) & WZRD_CLKOUT_FRAC_MASK; + + return mult_frac(parent_rate, 1000, (div * 1000) + frac); +} + +static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + int err; + u32 value, pre; + unsigned long rate_div, f, clockout0_div; + struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); + void __iomem *div_addr = divider->base + divider->offset; + + rate_div = ((parent_rate * 1000) / rate); + clockout0_div = rate_div / 1000; + + pre = DIV_ROUND_CLOSEST((parent_rate * 1000), rate); + f = (u32)(pre - (clockout0_div * 1000)); + f = f & WZRD_CLKOUT_FRAC_MASK; + f = f << WZRD_CLKOUT_DIVIDE_WIDTH; + + value = (f | (clockout0_div & WZRD_CLKOUT_DIVIDE_MASK)); + + /* Set divisor and clear phase offset */ + writel(value, div_addr); + writel(0x0, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET); + + /* Check status register */ + err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value, + value & WZRD_DR_LOCK_BIT_MASK, + WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); + if (err) + return err; + + /* Initiate reconfiguration */ + writel(WZRD_DR_BEGIN_DYNA_RECONF, + divider->base + WZRD_DR_INIT_REG_OFFSET); + + /* Check status register */ + return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value, + value & WZRD_DR_LOCK_BIT_MASK, + WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); +} + +static long clk_wzrd_round_rate_f(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + return rate; +} + +static const struct clk_ops clk_wzrd_clk_divider_ops_f = { + .round_rate = clk_wzrd_round_rate_f, + .set_rate = clk_wzrd_dynamic_reconfig_f, + .recalc_rate = clk_wzrd_recalc_ratef, +}; + +static struct clk *clk_wzrd_register_divf(struct device *dev, + const char *name, + const char *parent_name, + unsigned long flags, + void __iomem *base, u16 offset, + u8 shift, u8 width, + u8 clk_divider_flags, + const struct clk_div_table *table, + spinlock_t *lock) +{ + struct clk_wzrd_divider *div; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); + if (!div) + return ERR_PTR(-ENOMEM); + + init.name = name; + + init.ops = &clk_wzrd_clk_divider_ops_f; + + init.flags = flags; + init.parent_names = &parent_name; + init.num_parents = 1; + + div->base = base; + div->offset = offset; + div->shift = shift; + div->width = width; + div->flags = clk_divider_flags; + div->lock = lock; + div->hw.init = &init; + div->table = table; + + hw = &div->hw; + ret = devm_clk_hw_register(dev, hw); + if (ret) + return ERR_PTR(ret); + + return hw->clk; +} + +static struct clk *clk_wzrd_register_divider(struct device *dev, + const char *name, + const char *parent_name, + unsigned long flags, + void __iomem *base, u16 offset, + u8 shift, u8 width, + u8 clk_divider_flags, + const struct clk_div_table *table, + spinlock_t *lock) +{ + struct clk_wzrd_divider *div; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); + if (!div) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &clk_wzrd_clk_divider_ops; + init.flags = flags; + init.parent_names = &parent_name; + init.num_parents = 1; + + div->base = base; + div->offset = offset; + div->shift = shift; + div->width = width; + div->flags = clk_divider_flags; + div->lock = lock; + div->hw.init = &init; + div->table = table; + + hw = &div->hw; + ret = devm_clk_hw_register(dev, hw); + if (ret) + hw = ERR_PTR(ret); + + return hw->clk; +} + +static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long event, + void *data) +{ + unsigned long max; + struct clk_notifier_data *ndata = data; + struct clk_wzrd *clk_wzrd = to_clk_wzrd(nb); + + if (clk_wzrd->suspended) + return NOTIFY_OK; + + if (ndata->clk == clk_wzrd->clk_in1) + max = clk_wzrd_max_freq[clk_wzrd->speed_grade - 1]; + else if (ndata->clk == clk_wzrd->axi_clk) + max = WZRD_ACLK_MAX_FREQ; + else + return NOTIFY_DONE; /* should never happen */ + + switch (event) { + case PRE_RATE_CHANGE: + if (ndata->new_rate > max) + return NOTIFY_BAD; + return NOTIFY_OK; + case POST_RATE_CHANGE: + case ABORT_RATE_CHANGE: + default: + return NOTIFY_DONE; + } +} + +static int __maybe_unused clk_wzrd_suspend(struct device *dev) +{ + struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev); + + clk_disable_unprepare(clk_wzrd->axi_clk); + clk_wzrd->suspended = true; + + return 0; +} + +static int __maybe_unused clk_wzrd_resume(struct device *dev) +{ + int ret; + struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev); + + ret = clk_prepare_enable(clk_wzrd->axi_clk); + if (ret) { + dev_err(dev, "unable to enable s_axi_aclk\n"); + return ret; + } + + clk_wzrd->suspended = false; + + return 0; +} + +static SIMPLE_DEV_PM_OPS(clk_wzrd_dev_pm_ops, clk_wzrd_suspend, + clk_wzrd_resume); + +static int clk_wzrd_probe(struct platform_device *pdev) +{ + int i, ret; + u32 reg, reg_f, mult; + unsigned long rate; + const char *clk_name; + void __iomem *ctrl_reg; + struct clk_wzrd *clk_wzrd; + struct device_node *np = pdev->dev.of_node; + int nr_outputs; + unsigned long flags = 0; + + clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL); + if (!clk_wzrd) + return -ENOMEM; + platform_set_drvdata(pdev, clk_wzrd); + + clk_wzrd->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(clk_wzrd->base)) + return PTR_ERR(clk_wzrd->base); + + ret = of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_grade); + if (!ret) { + if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) { + dev_warn(&pdev->dev, "invalid speed grade '%d'\n", + clk_wzrd->speed_grade); + clk_wzrd->speed_grade = 0; + } + } + + clk_wzrd->clk_in1 = devm_clk_get(&pdev->dev, "clk_in1"); + if (IS_ERR(clk_wzrd->clk_in1)) { + if (clk_wzrd->clk_in1 != ERR_PTR(-EPROBE_DEFER)) + dev_err(&pdev->dev, "clk_in1 not found\n"); + return PTR_ERR(clk_wzrd->clk_in1); + } + + clk_wzrd->axi_clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); + if (IS_ERR(clk_wzrd->axi_clk)) { + if (clk_wzrd->axi_clk != ERR_PTR(-EPROBE_DEFER)) + dev_err(&pdev->dev, "s_axi_aclk not found\n"); + return PTR_ERR(clk_wzrd->axi_clk); + } + ret = clk_prepare_enable(clk_wzrd->axi_clk); + if (ret) { + dev_err(&pdev->dev, "enabling s_axi_aclk failed\n"); + return ret; + } + rate = clk_get_rate(clk_wzrd->axi_clk); + if (rate > WZRD_ACLK_MAX_FREQ) { + dev_err(&pdev->dev, "s_axi_aclk frequency (%lu) too high\n", + rate); + ret = -EINVAL; + goto err_disable_clk; + } + + reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)); + reg_f = reg & WZRD_CLKFBOUT_FRAC_MASK; + reg_f = reg_f >> WZRD_CLKFBOUT_FRAC_SHIFT; + + reg = reg & WZRD_CLKFBOUT_MULT_MASK; + reg = reg >> WZRD_CLKFBOUT_MULT_SHIFT; + mult = (reg * 1000) + reg_f; + clk_name = kasprintf(GFP_KERNEL, "%s_mul", dev_name(&pdev->dev)); + if (!clk_name) { + ret = -ENOMEM; + goto err_disable_clk; + } + + ret = of_property_read_u32(np, "nr-outputs", &nr_outputs); + if (ret || nr_outputs > WZRD_NUM_OUTPUTS) { + ret = -EINVAL; + goto err_disable_clk; + } + if (nr_outputs == 1) + flags = CLK_SET_RATE_PARENT; + + clk_wzrd->clks_internal[wzrd_clk_mul] = clk_register_fixed_factor + (&pdev->dev, clk_name, + __clk_get_name(clk_wzrd->clk_in1), + 0, mult, 1000); + if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul])) { + dev_err(&pdev->dev, "unable to register fixed-factor clock\n"); + ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul]); + goto err_disable_clk; + } + + clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev)); + if (!clk_name) { + ret = -ENOMEM; + goto err_rm_int_clk; + } + + ctrl_reg = clk_wzrd->base + WZRD_CLK_CFG_REG(0); + /* register div */ + clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_divider + (&pdev->dev, clk_name, + __clk_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]), + flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &clkwzrd_lock); + if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div])) { + dev_err(&pdev->dev, "unable to register divider clock\n"); + ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div]); + goto err_rm_int_clk; + } + + /* register div per output */ + for (i = nr_outputs - 1; i >= 0 ; i--) { + const char *clkout_name; + + clkout_name = kasprintf(GFP_KERNEL, "%s_out%d", dev_name(&pdev->dev), i); + if (!clkout_name) { + ret = -ENOMEM; + goto err_rm_int_clk; + } + + if (!i) + clk_wzrd->clkout[i] = clk_wzrd_register_divf + (&pdev->dev, clkout_name, + clk_name, flags, + clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12), + WZRD_CLKOUT_DIVIDE_SHIFT, + WZRD_CLKOUT_DIVIDE_WIDTH, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + NULL, &clkwzrd_lock); + else + clk_wzrd->clkout[i] = clk_wzrd_register_divider + (&pdev->dev, clkout_name, + clk_name, 0, + clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12), + WZRD_CLKOUT_DIVIDE_SHIFT, + WZRD_CLKOUT_DIVIDE_WIDTH, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + NULL, &clkwzrd_lock); + if (IS_ERR(clk_wzrd->clkout[i])) { + int j; + + for (j = i + 1; j < nr_outputs; j++) + clk_unregister(clk_wzrd->clkout[j]); + dev_err(&pdev->dev, + "unable to register divider clock\n"); + ret = PTR_ERR(clk_wzrd->clkout[i]); + goto err_rm_int_clks; + } + } + + kfree(clk_name); + + clk_wzrd->clk_data.clks = clk_wzrd->clkout; + clk_wzrd->clk_data.clk_num = ARRAY_SIZE(clk_wzrd->clkout); + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_wzrd->clk_data); + + if (clk_wzrd->speed_grade) { + clk_wzrd->nb.notifier_call = clk_wzrd_clk_notifier; + + ret = clk_notifier_register(clk_wzrd->clk_in1, + &clk_wzrd->nb); + if (ret) + dev_warn(&pdev->dev, + "unable to register clock notifier\n"); + + ret = clk_notifier_register(clk_wzrd->axi_clk, &clk_wzrd->nb); + if (ret) + dev_warn(&pdev->dev, + "unable to register clock notifier\n"); + } + + return 0; + +err_rm_int_clks: + clk_unregister(clk_wzrd->clks_internal[1]); +err_rm_int_clk: + kfree(clk_name); + clk_unregister(clk_wzrd->clks_internal[0]); +err_disable_clk: + clk_disable_unprepare(clk_wzrd->axi_clk); + + return ret; +} + +static int clk_wzrd_remove(struct platform_device *pdev) +{ + int i; + struct clk_wzrd *clk_wzrd = platform_get_drvdata(pdev); + + of_clk_del_provider(pdev->dev.of_node); + + for (i = 0; i < WZRD_NUM_OUTPUTS; i++) + clk_unregister(clk_wzrd->clkout[i]); + for (i = 0; i < wzrd_clk_int_max; i++) + clk_unregister(clk_wzrd->clks_internal[i]); + + if (clk_wzrd->speed_grade) { + clk_notifier_unregister(clk_wzrd->axi_clk, &clk_wzrd->nb); + clk_notifier_unregister(clk_wzrd->clk_in1, &clk_wzrd->nb); + } + + clk_disable_unprepare(clk_wzrd->axi_clk); + + return 0; +} + +static const struct of_device_id clk_wzrd_ids[] = { + { .compatible = "xlnx,clocking-wizard" }, + { }, +}; +MODULE_DEVICE_TABLE(of, clk_wzrd_ids); + +static struct platform_driver clk_wzrd_driver = { + .driver = { + .name = "clk-wizard", + .of_match_table = clk_wzrd_ids, + .pm = &clk_wzrd_dev_pm_ops, + }, + .probe = clk_wzrd_probe, + .remove = clk_wzrd_remove, +}; +module_platform_driver(clk_wzrd_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com"); +MODULE_DESCRIPTION("Driver for the Xilinx Clocking Wizard IP core"); -- 2.17.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v12 2/5] clk: clocking-wizard: Add the clockwizard to clk directory 2021-08-10 7:25 ` [PATCH v12 2/5] clk: clocking-wizard: Add the clockwizard to clk directory Shubhrajyoti Datta @ 2021-08-24 9:51 ` Geert Uytterhoeven 0 siblings, 0 replies; 10+ messages in thread From: Geert Uytterhoeven @ 2021-08-24 9:51 UTC (permalink / raw) To: Shubhrajyoti Datta Cc: linux-clk, git, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, shubhrajyoti.datta Hi Shubhrajyoti, Thanks for your patch! On Tue, Aug 10, 2021 at 10:37 AM Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> wrote: > Add clocking wizard driver to clk. > And delete the driver from the staging as it is in drivers/clk. The old driver is not deleted from staging? > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > --- > > drivers/clk/Kconfig | 9 + > drivers/clk/Makefile | 1 + > drivers/clk/clk-xlnx-clock-wizard.c | 635 ++++++++++++++++++++++++++++ > 3 files changed, 645 insertions(+) > create mode 100644 drivers/clk/clk-xlnx-clock-wizard.c > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig > index e873f9ea2e65..22817be89bd8 100644 > --- a/drivers/clk/Kconfig > +++ b/drivers/clk/Kconfig > @@ -390,6 +390,15 @@ config COMMON_CLK_K210 > help > Support for the Canaan Kendryte K210 RISC-V SoC clocks. > > +config COMMON_CLK_XLNX_CLKWZRD > + tristate "Xilinx Clocking Wizard" > + depends on COMMON_CLK && OF Should there be a platform dependency ("depends on <FOO> || COMPILE_TEST"), to avoid asking the user about this driver when configuring a kernel for a platform that does not have this device, or can this device be present on any platform? Despite the original driver having been added 7 years ago, there are no upstream users of "xlnx,clocking-wizard" yet... > + help > + Support for the Xilinx Clocking Wizard IP core clock generator. > + Adds support for clocking wizard and compatible. > + This driver supports the Xilinx clocking wizard programmable clock > + synthesizer. The number of output is configurable in the design. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v12 3/5] clk: clocking-wizard: Rename nr-outputs to xlnx,nr-outputs 2021-08-10 7:25 [PATCH v12 0/5] clk: clocking-wizard: Driver updates Shubhrajyoti Datta 2021-08-10 7:25 ` [PATCH v12 1/5] dt-bindings: add documentation of xilinx clocking wizard Shubhrajyoti Datta 2021-08-10 7:25 ` [PATCH v12 2/5] clk: clocking-wizard: Add the clockwizard to clk directory Shubhrajyoti Datta @ 2021-08-10 7:25 ` Shubhrajyoti Datta 2021-08-10 7:25 ` [PATCH v12 4/5] clk: clocking-wizard: Fix the reconfig for 5.2 Shubhrajyoti Datta ` (2 subsequent siblings) 5 siblings, 0 replies; 10+ messages in thread From: Shubhrajyoti Datta @ 2021-08-10 7:25 UTC (permalink / raw) To: linux-clk, git; +Cc: devicetree, shubhrajyoti.datta, Shubhrajyoti Datta Rename nr-outputs to xlnx,output. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> --- v11: new patch v12: No change drivers/clk/clk-xlnx-clock-wizard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c index ec377f0d569b..1e0818eb0435 100644 --- a/drivers/clk/clk-xlnx-clock-wizard.c +++ b/drivers/clk/clk-xlnx-clock-wizard.c @@ -480,7 +480,7 @@ static int clk_wzrd_probe(struct platform_device *pdev) goto err_disable_clk; } - ret = of_property_read_u32(np, "nr-outputs", &nr_outputs); + ret = of_property_read_u32(np, "xlnx,nr-outputs", &nr_outputs); if (ret || nr_outputs > WZRD_NUM_OUTPUTS) { ret = -EINVAL; goto err_disable_clk; -- 2.17.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v12 4/5] clk: clocking-wizard: Fix the reconfig for 5.2 2021-08-10 7:25 [PATCH v12 0/5] clk: clocking-wizard: Driver updates Shubhrajyoti Datta ` (2 preceding siblings ...) 2021-08-10 7:25 ` [PATCH v12 3/5] clk: clocking-wizard: Rename nr-outputs to xlnx,nr-outputs Shubhrajyoti Datta @ 2021-08-10 7:25 ` Shubhrajyoti Datta 2021-08-10 7:25 ` [PATCH v12 5/5] clk: clocking-wizard: Update the compatible Shubhrajyoti Datta 2021-08-24 9:46 ` [PATCH v12 0/5] clk: clocking-wizard: Driver updates Geert Uytterhoeven 5 siblings, 0 replies; 10+ messages in thread From: Shubhrajyoti Datta @ 2021-08-10 7:25 UTC (permalink / raw) To: linux-clk, git; +Cc: devicetree, shubhrajyoti.datta, Shubhrajyoti Datta The 5.2 the reconfig is triggered by writing 7 followed by 2 to the reconfig reg. Add the same. Also 6.0 is backward compatible so it should be fine. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> --- v11: new patch v12: No change drivers/clk/clk-xlnx-clock-wizard.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c index 1e0818eb0435..61c40e06e381 100644 --- a/drivers/clk/clk-xlnx-clock-wizard.c +++ b/drivers/clk/clk-xlnx-clock-wizard.c @@ -44,6 +44,8 @@ #define WZRD_DR_INIT_REG_OFFSET 0x25C #define WZRD_DR_DIV_TO_PHASE_OFFSET 4 #define WZRD_DR_BEGIN_DYNA_RECONF 0x03 +#define WZRD_DR_BEGIN_DYNA_RECONF_5_2 0x07 +#define WZRD_DR_BEGIN_DYNA_RECONF1_5_2 0x02 #define WZRD_USEC_POLL 10 #define WZRD_TIMEOUT_POLL 1000 @@ -165,7 +167,9 @@ static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate, goto err_reconfig; /* Initiate reconfiguration */ - writel(WZRD_DR_BEGIN_DYNA_RECONF, + writel(WZRD_DR_BEGIN_DYNA_RECONF_5_2, + divider->base + WZRD_DR_INIT_REG_OFFSET); + writel(WZRD_DR_BEGIN_DYNA_RECONF1_5_2, divider->base + WZRD_DR_INIT_REG_OFFSET); /* Check status register */ @@ -224,7 +228,7 @@ static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate, struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); void __iomem *div_addr = divider->base + divider->offset; - rate_div = ((parent_rate * 1000) / rate); + rate_div = DIV_ROUND_DOWN_ULL(parent_rate * 1000, rate); clockout0_div = rate_div / 1000; pre = DIV_ROUND_CLOSEST((parent_rate * 1000), rate); @@ -246,7 +250,9 @@ static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate, return err; /* Initiate reconfiguration */ - writel(WZRD_DR_BEGIN_DYNA_RECONF, + writel(WZRD_DR_BEGIN_DYNA_RECONF_5_2, + divider->base + WZRD_DR_INIT_REG_OFFSET); + writel(WZRD_DR_BEGIN_DYNA_RECONF1_5_2, divider->base + WZRD_DR_INIT_REG_OFFSET); /* Check status register */ -- 2.17.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v12 5/5] clk: clocking-wizard: Update the compatible 2021-08-10 7:25 [PATCH v12 0/5] clk: clocking-wizard: Driver updates Shubhrajyoti Datta ` (3 preceding siblings ...) 2021-08-10 7:25 ` [PATCH v12 4/5] clk: clocking-wizard: Fix the reconfig for 5.2 Shubhrajyoti Datta @ 2021-08-10 7:25 ` Shubhrajyoti Datta 2021-08-24 9:46 ` [PATCH v12 0/5] clk: clocking-wizard: Driver updates Geert Uytterhoeven 5 siblings, 0 replies; 10+ messages in thread From: Shubhrajyoti Datta @ 2021-08-10 7:25 UTC (permalink / raw) To: linux-clk, git; +Cc: devicetree, shubhrajyoti.datta, Shubhrajyoti Datta Update the compatible to indicate support for both 5.2 and 6.0 Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> --- v11: new patch v12: No change drivers/clk/clk-xlnx-clock-wizard.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c index 61c40e06e381..716fea83341a 100644 --- a/drivers/clk/clk-xlnx-clock-wizard.c +++ b/drivers/clk/clk-xlnx-clock-wizard.c @@ -621,6 +621,8 @@ static int clk_wzrd_remove(struct platform_device *pdev) static const struct of_device_id clk_wzrd_ids[] = { { .compatible = "xlnx,clocking-wizard" }, + { .compatible = "xlnx,clocking-wizard-v5-2" }, + { .compatible = "xlnx,clocking-wizard-v6-0" }, { }, }; MODULE_DEVICE_TABLE(of, clk_wzrd_ids); -- 2.17.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v12 0/5] clk: clocking-wizard: Driver updates 2021-08-10 7:25 [PATCH v12 0/5] clk: clocking-wizard: Driver updates Shubhrajyoti Datta ` (4 preceding siblings ...) 2021-08-10 7:25 ` [PATCH v12 5/5] clk: clocking-wizard: Update the compatible Shubhrajyoti Datta @ 2021-08-24 9:46 ` Geert Uytterhoeven 5 siblings, 0 replies; 10+ messages in thread From: Geert Uytterhoeven @ 2021-08-24 9:46 UTC (permalink / raw) To: Shubhrajyoti Datta Cc: linux-clk, git, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, shubhrajyoti.datta Hi Shubhrajyoti, On Tue, Aug 10, 2021 at 10:37 AM Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> wrote: > The patch does the following > Update the versions of the clocking wizard ip. > Move from staging to clk directory. > Update the bindings. Thanks for your series! > v12: > No change. > Rebased There is a change: you lost the move from staging to clk. > > Shubhrajyoti Datta (5): > dt-bindings: add documentation of xilinx clocking wizard > clk: clocking-wizard: Add the clockwizard to clk directory > clk: clocking-wizard: Rename nr-outputs to xlnx,nr-outputs > clk: clocking-wizard: Fix the reconfig for 5.2 > clk: clocking-wizard: Update the compatible > > .../bindings/clock/xlnx,clocking-wizard.yaml | 77 +++ > drivers/clk/Kconfig | 9 + > drivers/clk/Makefile | 1 + > drivers/clk/clk-xlnx-clock-wizard.c | 643 ++++++++++++++++++ > 4 files changed, 730 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > create mode 100644 drivers/clk/clk-xlnx-clock-wizard.c Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-08-24 9:52 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-08-10 7:25 [PATCH v12 0/5] clk: clocking-wizard: Driver updates Shubhrajyoti Datta 2021-08-10 7:25 ` [PATCH v12 1/5] dt-bindings: add documentation of xilinx clocking wizard Shubhrajyoti Datta 2021-08-17 19:52 ` Rob Herring 2021-08-19 10:27 ` Shubhrajyoti Datta 2021-08-10 7:25 ` [PATCH v12 2/5] clk: clocking-wizard: Add the clockwizard to clk directory Shubhrajyoti Datta 2021-08-24 9:51 ` Geert Uytterhoeven 2021-08-10 7:25 ` [PATCH v12 3/5] clk: clocking-wizard: Rename nr-outputs to xlnx,nr-outputs Shubhrajyoti Datta 2021-08-10 7:25 ` [PATCH v12 4/5] clk: clocking-wizard: Fix the reconfig for 5.2 Shubhrajyoti Datta 2021-08-10 7:25 ` [PATCH v12 5/5] clk: clocking-wizard: Update the compatible Shubhrajyoti Datta 2021-08-24 9:46 ` [PATCH v12 0/5] clk: clocking-wizard: Driver updates Geert Uytterhoeven
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