* [PATCH 1/3] arm64: dts: juno: add coresight support
[not found] ` <1465228765-14038-1-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
@ 2016-06-06 15:59 ` Sudeep Holla
2016-06-17 15:29 ` Mathieu Poirier
[not found] ` <1465228765-14038-2-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
2016-06-06 15:59 ` [PATCH 2/3] arm64: dts: juno: add arm,primecell-periphid override Sudeep Holla
` (2 subsequent siblings)
3 siblings, 2 replies; 23+ messages in thread
From: Sudeep Holla @ 2016-06-06 15:59 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Sudeep Holla, Jon Medhurst, Mathieu Poirier, Suzuki K Poulose,
Liviu Dudau, Lorenzo Pieralisi,
devicetree-u79uwXL29TY76Z2rM5mHXA
Most of the debug-related components on Juno are located in the coreSight
subsystem while others are located in the Cortex-Axx clusters, the SCP
subsystem, and in the main system.
Each core in the two processor clusters contain an Embedded Trace
Macrocell(ETM) which generates real-time trace information that trace
tools can use and an ATB trace output that is sent to a funnel before
going to the CoreSight subsystem.
The trace output signals combine with two trace expansions using another
funnel and fed into the Embedded Trace FIFO(ETF0).
The output trace data stream of the funnel is then replicated before it
is sent to either the:
- Trace Port Interface Unit(TPIU), that sends it out using the trace port.
- ETR that can write the trace data to memory located in the application
memory space
Cc: Liviu Dudau <liviu.dudau-5wv7dgnIgG8@public.gmane.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 296 +++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/arm/juno-r1.dts | 24 +++
arch/arm64/boot/dts/arm/juno-r2.dts | 24 +++
arch/arm64/boot/dts/arm/juno.dts | 24 +++
4 files changed, 368 insertions(+)
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index dee2386d3b9b..90a8710f7032 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -56,6 +56,302 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
};
+ /*
+ * Juno TRMs specify the size for these coresight components as 64K.
+ * The actual size is just 4K though 64K is reserved. Access to the
+ * unmapped reserved region results in a DECERR response.
+ */
+ etf@20010000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x20010000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* input port */
+ port@0 {
+ reg = <0>;
+ etf_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&main_funnel_out_port>;
+ };
+ };
+
+ /* output port */
+ port@1 {
+ reg = <0>;
+ etf_out_port: endpoint {
+ remote-endpoint = <&replicator_in_port0>;
+ };
+ };
+ };
+ };
+
+ tpiu@20030000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0 0x20030000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ port {
+ tpiu_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&replicator_out_port0>;
+ };
+ };
+ };
+
+ main_funnel@20040000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x20040000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ main_funnel_out_port: endpoint {
+ remote-endpoint = <&etf_in_port>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ main_funnel_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&cluster0_funnel_out_port>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ main_funnel_in_port1: endpoint {
+ slave-mode;
+ remote-endpoint = <&cluster1_funnel_out_port>;
+ };
+ };
+
+ };
+ };
+
+ etr@20070000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x20070000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ port {
+ etr_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&replicator_out_port1>;
+ };
+ };
+ };
+
+ coresight-replicator {
+ /* non-configurable replicators don't show up on the
+ * AMBA bus. As such no need to add "arm,primecell".
+ */
+ compatible = "arm,coresight-replicator";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* replicator output ports */
+ port@0 {
+ reg = <0>;
+ replicator_out_port0: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ replicator_out_port1: endpoint {
+ remote-endpoint = <&etr_in_port>;
+ };
+ };
+
+ /* replicator input port */
+ port@2 {
+ reg = <0>;
+ replicator_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&etf_out_port>;
+ };
+ };
+ };
+ };
+
+ cluster0_funnel@220c0000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x220c0000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ cluster0_funnel_out_port: endpoint {
+ remote-endpoint = <&main_funnel_in_port0>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ cluster0_funnel_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&cluster0_etm0_out_port>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ cluster0_funnel_in_port1: endpoint {
+ slave-mode;
+ remote-endpoint = <&cluster0_etm1_out_port>;
+ };
+ };
+ };
+ };
+
+ cluster1_funnel@230c0000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x230c0000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ cluster1_funnel_out_port: endpoint {
+ remote-endpoint = <&main_funnel_in_port1>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ cluster1_funnel_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&cluster1_etm0_out_port>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ cluster1_funnel_in_port1: endpoint {
+ slave-mode;
+ remote-endpoint = <&cluster1_etm1_out_port>;
+ };
+ };
+ port@3 {
+ reg = <2>;
+ cluster1_funnel_in_port2: endpoint {
+ slave-mode;
+ remote-endpoint = <&cluster1_etm2_out_port>;
+ };
+ };
+ port@4 {
+ reg = <3>;
+ cluster1_funnel_in_port3: endpoint {
+ slave-mode;
+ remote-endpoint = <&cluster1_etm3_out_port>;
+ };
+ };
+ };
+ };
+
+ etm0: etm@22040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x22040000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ port {
+ cluster0_etm0_out_port: endpoint {
+ remote-endpoint = <&cluster0_funnel_in_port0>;
+ };
+ };
+ };
+
+ etm1: etm@22140000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x22140000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ port {
+ cluster0_etm1_out_port: endpoint {
+ remote-endpoint = <&cluster0_funnel_in_port1>;
+ };
+ };
+ };
+
+ etm2: etm@23040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x23040000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ port {
+ cluster1_etm0_out_port: endpoint {
+ remote-endpoint = <&cluster1_funnel_in_port0>;
+ };
+ };
+ };
+
+ etm3: etm@23140000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x23140000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ port {
+ cluster1_etm1_out_port: endpoint {
+ remote-endpoint = <&cluster1_funnel_in_port1>;
+ };
+ };
+ };
+
+ etm4: etm@23240000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x23240000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ port {
+ cluster1_etm2_out_port: endpoint {
+ remote-endpoint = <&cluster1_funnel_in_port2>;
+ };
+ };
+ };
+
+ etm5: etm@23340000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x23340000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ port {
+ cluster1_etm3_out_port: endpoint {
+ remote-endpoint = <&cluster1_funnel_in_port3>;
+ };
+ };
+ };
+
sram: sram@2e000000 {
compatible = "arm,juno-sram-ns", "mmio-sram";
reg = <0x0 0x2e000000 0x0 0x8000>;
diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
index d95d9e7e2dc0..f4f8f54f8b85 100644
--- a/arch/arm64/boot/dts/arm/juno-r1.dts
+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
@@ -181,3 +181,27 @@
&pcie_ctlr {
status = "okay";
};
+
+&etm0 {
+ cpu = <&A57_0>;
+};
+
+&etm1 {
+ cpu = <&A57_1>;
+};
+
+&etm2 {
+ cpu = <&A53_0>;
+};
+
+&etm3 {
+ cpu = <&A53_1>;
+};
+
+&etm4 {
+ cpu = <&A53_2>;
+};
+
+&etm5 {
+ cpu = <&A53_3>;
+};
diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
index 88ecd6182b67..d903e545b64c 100644
--- a/arch/arm64/boot/dts/arm/juno-r2.dts
+++ b/arch/arm64/boot/dts/arm/juno-r2.dts
@@ -181,3 +181,27 @@
&pcie_ctlr {
status = "okay";
};
+
+&etm0 {
+ cpu = <&A72_0>;
+};
+
+&etm1 {
+ cpu = <&A72_1>;
+};
+
+&etm2 {
+ cpu = <&A53_0>;
+};
+
+&etm3 {
+ cpu = <&A53_1>;
+};
+
+&etm4 {
+ cpu = <&A53_2>;
+};
+
+&etm5 {
+ cpu = <&A53_3>;
+};
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index dcfcf15a17f5..a7270eff6939 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -173,3 +173,27 @@
#include "juno-base.dtsi"
};
+
+&etm0 {
+ cpu = <&A57_0>;
+};
+
+&etm1 {
+ cpu = <&A57_1>;
+};
+
+&etm2 {
+ cpu = <&A53_0>;
+};
+
+&etm3 {
+ cpu = <&A53_1>;
+};
+
+&etm4 {
+ cpu = <&A53_2>;
+};
+
+&etm5 {
+ cpu = <&A53_3>;
+};
--
2.7.4
--
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^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 2/3] arm64: dts: juno: add arm,primecell-periphid override
[not found] ` <1465228765-14038-1-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
2016-06-06 15:59 ` [PATCH 1/3] arm64: dts: juno: add coresight support Sudeep Holla
@ 2016-06-06 15:59 ` Sudeep Holla
[not found] ` <1465228765-14038-3-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
2016-06-06 15:59 ` [PATCH 3/3] arm64: dts: juno: add SCPI power domains for device power management Sudeep Holla
2016-07-06 10:15 ` [PATCH v2 0/2] arm64: dts: juno: add coresight support Sudeep Holla
3 siblings, 1 reply; 23+ messages in thread
From: Sudeep Holla @ 2016-06-06 15:59 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Sudeep Holla, Jon Medhurst, Mathieu Poirier, Suzuki K Poulose,
Liviu Dudau, Lorenzo Pieralisi,
devicetree-u79uwXL29TY76Z2rM5mHXA
The Linux AMBA framework probes the peripheral ids when adding the amba
devices very early on the boot. Generally they are on APB bus and just
require APB clocks to be on even when most of the core logic of the IP
is powered down.
However on Juno, the entire debugsys domain needs to be ON to access
those CID/PID registers and hence broken by design. Accessing those
while debugsys power domain is off will lead to the bridge stalling the
transactions instead of returning the slave error.
Since keeping the power domain on by default affects the core power(by
preventing cores entering deeper idle states), it's not feasible
solution. Instead we can provide arm,primecell-periphid override in the
device tree that prevents accessing the device early in the boot.
However the power domains can be enabled whenever required using runtime
PM and associated power domains.
Cc: Liviu Dudau <liviu.dudau-5wv7dgnIgG8@public.gmane.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 13 +++++++++++++
arch/arm64/boot/dts/arm/juno-r1.dts | 6 ++++++
arch/arm64/boot/dts/arm/juno-r2.dts | 6 ++++++
arch/arm64/boot/dts/arm/juno.dts | 6 ++++++
4 files changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 90a8710f7032..49fa55cdc977 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -63,6 +63,14 @@
*/
etf@20010000 {
compatible = "arm,coresight-tmc", "arm,primecell";
+ /*
+ * The primecell peripheral id is explicitly specified here with
+ * the actual hardware value. It's not any override. It's
+ * required to workaround an errata to avoid bus stalls early
+ * in the boot when AMBA primecell ids are probed before the
+ * actual power domain can be enabled using SCPI.
+ */
+ arm,primecell-periphid = <0x001bb961>;
reg = <0 0x20010000 0 0x1000>;
clocks = <&soc_smc50mhz>;
@@ -92,6 +100,7 @@
tpiu@20030000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
+ arm,primecell-periphid = <0x004bb912>;
reg = <0 0x20030000 0 0x1000>;
clocks = <&soc_smc50mhz>;
@@ -106,6 +115,7 @@
main_funnel@20040000 {
compatible = "arm,coresight-funnel", "arm,primecell";
+ arm,primecell-periphid = <0x002bb908>;
reg = <0 0x20040000 0 0x1000>;
clocks = <&soc_smc50mhz>;
@@ -142,6 +152,7 @@
etr@20070000 {
compatible = "arm,coresight-tmc", "arm,primecell";
+ arm,primecell-periphid = <0x001bb961>;
reg = <0 0x20070000 0 0x1000>;
clocks = <&soc_smc50mhz>;
@@ -192,6 +203,7 @@
cluster0_funnel@220c0000 {
compatible = "arm,coresight-funnel", "arm,primecell";
+ arm,primecell-periphid = <0x002bb908>;
reg = <0 0x220c0000 0 0x1000>;
clocks = <&soc_smc50mhz>;
@@ -227,6 +239,7 @@
cluster1_funnel@230c0000 {
compatible = "arm,coresight-funnel", "arm,primecell";
+ arm,primecell-periphid = <0x002bb908>;
reg = <0 0x230c0000 0 0x1000>;
clocks = <&soc_smc50mhz>;
diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
index f4f8f54f8b85..c3c9fdff49bf 100644
--- a/arch/arm64/boot/dts/arm/juno-r1.dts
+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
@@ -184,24 +184,30 @@
&etm0 {
cpu = <&A57_0>;
+ arm,primecell-periphid = <0x002bb95e>;
};
&etm1 {
cpu = <&A57_1>;
+ arm,primecell-periphid = <0x002bb95e>;
};
&etm2 {
cpu = <&A53_0>;
+ arm,primecell-periphid = <0x003bb95d>;
};
&etm3 {
cpu = <&A53_1>;
+ arm,primecell-periphid = <0x003bb95d>;
};
&etm4 {
cpu = <&A53_2>;
+ arm,primecell-periphid = <0x003bb95d>;
};
&etm5 {
cpu = <&A53_3>;
+ arm,primecell-periphid = <0x003bb95d>;
};
diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
index d903e545b64c..c672c978f89d 100644
--- a/arch/arm64/boot/dts/arm/juno-r2.dts
+++ b/arch/arm64/boot/dts/arm/juno-r2.dts
@@ -184,24 +184,30 @@
&etm0 {
cpu = <&A72_0>;
+ arm,primecell-periphid = <0x000bb95a>;
};
&etm1 {
cpu = <&A72_1>;
+ arm,primecell-periphid = <0x000bb95a>;
};
&etm2 {
cpu = <&A53_0>;
+ arm,primecell-periphid = <0x003bb95d>;
};
&etm3 {
cpu = <&A53_1>;
+ arm,primecell-periphid = <0x003bb95d>;
};
&etm4 {
cpu = <&A53_2>;
+ arm,primecell-periphid = <0x003bb95d>;
};
&etm5 {
cpu = <&A53_3>;
+ arm,primecell-periphid = <0x003bb95d>;
};
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index a7270eff6939..0528e47e66d1 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -176,24 +176,30 @@
&etm0 {
cpu = <&A57_0>;
+ arm,primecell-periphid = <0x000bb95e>;
};
&etm1 {
cpu = <&A57_1>;
+ arm,primecell-periphid = <0x000bb95e>;
};
&etm2 {
cpu = <&A53_0>;
+ arm,primecell-periphid = <0x000bb95d>;
};
&etm3 {
cpu = <&A53_1>;
+ arm,primecell-periphid = <0x000bb95d>;
};
&etm4 {
cpu = <&A53_2>;
+ arm,primecell-periphid = <0x000bb95d>;
};
&etm5 {
cpu = <&A53_3>;
+ arm,primecell-periphid = <0x000bb95d>;
};
--
2.7.4
--
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the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 3/3] arm64: dts: juno: add SCPI power domains for device power management
[not found] ` <1465228765-14038-1-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
2016-06-06 15:59 ` [PATCH 1/3] arm64: dts: juno: add coresight support Sudeep Holla
2016-06-06 15:59 ` [PATCH 2/3] arm64: dts: juno: add arm,primecell-periphid override Sudeep Holla
@ 2016-06-06 15:59 ` Sudeep Holla
[not found] ` <1465228765-14038-4-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
2016-07-06 10:15 ` [PATCH v2 0/2] arm64: dts: juno: add coresight support Sudeep Holla
3 siblings, 1 reply; 23+ messages in thread
From: Sudeep Holla @ 2016-06-06 15:59 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Sudeep Holla, Jon Medhurst, Mathieu Poirier, Suzuki K Poulose,
Liviu Dudau, Lorenzo Pieralisi,
devicetree-u79uwXL29TY76Z2rM5mHXA
This patch adds power domain information to coresight devices using
SCPI power domains.
Cc: Liviu Dudau <liviu.dudau-5wv7dgnIgG8@public.gmane.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 49fa55cdc977..ef054094d5a8 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -75,6 +75,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -105,6 +106,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
port {
tpiu_in_port: endpoint {
slave-mode;
@@ -120,6 +122,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -157,6 +160,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
port {
etr_in_port: endpoint {
slave-mode;
@@ -208,6 +212,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -244,6 +249,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -293,6 +299,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
port {
cluster0_etm0_out_port: endpoint {
remote-endpoint = <&cluster0_funnel_in_port0>;
@@ -306,6 +313,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
port {
cluster0_etm1_out_port: endpoint {
remote-endpoint = <&cluster0_funnel_in_port1>;
@@ -319,6 +327,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
port {
cluster1_etm0_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port0>;
@@ -332,6 +341,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
port {
cluster1_etm1_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port1>;
@@ -345,6 +355,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
port {
cluster1_etm2_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port2>;
@@ -358,6 +369,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
port {
cluster1_etm3_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port3>;
@@ -428,6 +440,12 @@
};
};
+ scpi_devpd: scpi-power-domains {
+ compatible = "arm,scpi-power-domains";
+ num-domains = <2>;
+ #power-domain-cells = <1>;
+ };
+
scpi_sensors0: sensors {
compatible = "arm,scpi-sensors";
#thermal-sensor-cells = <1>;
--
2.7.4
--
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^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] arm64: dts: juno: add coresight support
[not found] ` <1465228765-14038-2-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
@ 2016-06-08 16:04 ` Liviu Dudau
2016-06-12 21:57 ` Mathieu Poirier
2016-06-21 5:41 ` Olof Johansson
2 siblings, 0 replies; 23+ messages in thread
From: Liviu Dudau @ 2016-06-08 16:04 UTC (permalink / raw)
To: Sudeep Holla
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Jon Medhurst,
Mathieu Poirier, Suzuki K Poulose, Lorenzo Pieralisi,
devicetree-u79uwXL29TY76Z2rM5mHXA
On Mon, Jun 06, 2016 at 04:59:23PM +0100, Sudeep Holla wrote:
> Most of the debug-related components on Juno are located in the coreSight
> subsystem while others are located in the Cortex-Axx clusters, the SCP
> subsystem, and in the main system.
>
> Each core in the two processor clusters contain an Embedded Trace
> Macrocell(ETM) which generates real-time trace information that trace
> tools can use and an ATB trace output that is sent to a funnel before
> going to the CoreSight subsystem.
>
> The trace output signals combine with two trace expansions using another
> funnel and fed into the Embedded Trace FIFO(ETF0).
>
> The output trace data stream of the funnel is then replicated before it
> is sent to either the:
> - Trace Port Interface Unit(TPIU), that sends it out using the trace port.
> - ETR that can write the trace data to memory located in the application
> memory space
>
> Cc: Liviu Dudau <liviu.dudau-5wv7dgnIgG8@public.gmane.org>
Acked-by: Liviu Dudau <Liviu.Dudau-5wv7dgnIgG8@public.gmane.org>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
> ---
> arch/arm64/boot/dts/arm/juno-base.dtsi | 296 +++++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/arm/juno-r1.dts | 24 +++
> arch/arm64/boot/dts/arm/juno-r2.dts | 24 +++
> arch/arm64/boot/dts/arm/juno.dts | 24 +++
> 4 files changed, 368 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
> index dee2386d3b9b..90a8710f7032 100644
> --- a/arch/arm64/boot/dts/arm/juno-base.dtsi
> +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
> @@ -56,6 +56,302 @@
> <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
> };
>
> + /*
> + * Juno TRMs specify the size for these coresight components as 64K.
> + * The actual size is just 4K though 64K is reserved. Access to the
> + * unmapped reserved region results in a DECERR response.
> + */
> + etf@20010000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x20010000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* input port */
> + port@0 {
> + reg = <0>;
> + etf_in_port: endpoint {
> + slave-mode;
> + remote-endpoint = <&main_funnel_out_port>;
> + };
> + };
> +
> + /* output port */
> + port@1 {
> + reg = <0>;
> + etf_out_port: endpoint {
> + remote-endpoint = <&replicator_in_port0>;
> + };
> + };
> + };
> + };
> +
> + tpiu@20030000 {
> + compatible = "arm,coresight-tpiu", "arm,primecell";
> + reg = <0 0x20030000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + tpiu_in_port: endpoint {
> + slave-mode;
> + remote-endpoint = <&replicator_out_port0>;
> + };
> + };
> + };
> +
> + main_funnel@20040000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x20040000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + main_funnel_out_port: endpoint {
> + remote-endpoint = <&etf_in_port>;
> + };
> + };
> +
> + port@1 {
> + reg = <0>;
> + main_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster0_funnel_out_port>;
> + };
> + };
> +
> + port@2 {
> + reg = <1>;
> + main_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_funnel_out_port>;
> + };
> + };
> +
> + };
> + };
> +
> + etr@20070000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x20070000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + etr_in_port: endpoint {
> + slave-mode;
> + remote-endpoint = <&replicator_out_port1>;
> + };
> + };
> + };
> +
> + coresight-replicator {
> + /* non-configurable replicators don't show up on the
> + * AMBA bus. As such no need to add "arm,primecell".
> + */
> + compatible = "arm,coresight-replicator";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* replicator output ports */
> + port@0 {
> + reg = <0>;
> + replicator_out_port0: endpoint {
> + remote-endpoint = <&tpiu_in_port>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + replicator_out_port1: endpoint {
> + remote-endpoint = <&etr_in_port>;
> + };
> + };
> +
> + /* replicator input port */
> + port@2 {
> + reg = <0>;
> + replicator_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&etf_out_port>;
> + };
> + };
> + };
> + };
> +
> + cluster0_funnel@220c0000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x220c0000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + cluster0_funnel_out_port: endpoint {
> + remote-endpoint = <&main_funnel_in_port0>;
> + };
> + };
> +
> + port@1 {
> + reg = <0>;
> + cluster0_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster0_etm0_out_port>;
> + };
> + };
> +
> + port@2 {
> + reg = <1>;
> + cluster0_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster0_etm1_out_port>;
> + };
> + };
> + };
> + };
> +
> + cluster1_funnel@230c0000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x230c0000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + cluster1_funnel_out_port: endpoint {
> + remote-endpoint = <&main_funnel_in_port1>;
> + };
> + };
> +
> + port@1 {
> + reg = <0>;
> + cluster1_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_etm0_out_port>;
> + };
> + };
> +
> + port@2 {
> + reg = <1>;
> + cluster1_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_etm1_out_port>;
> + };
> + };
> + port@3 {
> + reg = <2>;
> + cluster1_funnel_in_port2: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_etm2_out_port>;
> + };
> + };
> + port@4 {
> + reg = <3>;
> + cluster1_funnel_in_port3: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_etm3_out_port>;
> + };
> + };
> + };
> + };
> +
> + etm0: etm@22040000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x22040000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster0_etm0_out_port: endpoint {
> + remote-endpoint = <&cluster0_funnel_in_port0>;
> + };
> + };
> + };
> +
> + etm1: etm@22140000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x22140000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster0_etm1_out_port: endpoint {
> + remote-endpoint = <&cluster0_funnel_in_port1>;
> + };
> + };
> + };
> +
> + etm2: etm@23040000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x23040000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster1_etm0_out_port: endpoint {
> + remote-endpoint = <&cluster1_funnel_in_port0>;
> + };
> + };
> + };
> +
> + etm3: etm@23140000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x23140000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster1_etm1_out_port: endpoint {
> + remote-endpoint = <&cluster1_funnel_in_port1>;
> + };
> + };
> + };
> +
> + etm4: etm@23240000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x23240000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster1_etm2_out_port: endpoint {
> + remote-endpoint = <&cluster1_funnel_in_port2>;
> + };
> + };
> + };
> +
> + etm5: etm@23340000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x23340000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster1_etm3_out_port: endpoint {
> + remote-endpoint = <&cluster1_funnel_in_port3>;
> + };
> + };
> + };
> +
> sram: sram@2e000000 {
> compatible = "arm,juno-sram-ns", "mmio-sram";
> reg = <0x0 0x2e000000 0x0 0x8000>;
> diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
> index d95d9e7e2dc0..f4f8f54f8b85 100644
> --- a/arch/arm64/boot/dts/arm/juno-r1.dts
> +++ b/arch/arm64/boot/dts/arm/juno-r1.dts
> @@ -181,3 +181,27 @@
> &pcie_ctlr {
> status = "okay";
> };
> +
> +&etm0 {
> + cpu = <&A57_0>;
> +};
> +
> +&etm1 {
> + cpu = <&A57_1>;
> +};
> +
> +&etm2 {
> + cpu = <&A53_0>;
> +};
> +
> +&etm3 {
> + cpu = <&A53_1>;
> +};
> +
> +&etm4 {
> + cpu = <&A53_2>;
> +};
> +
> +&etm5 {
> + cpu = <&A53_3>;
> +};
> diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
> index 88ecd6182b67..d903e545b64c 100644
> --- a/arch/arm64/boot/dts/arm/juno-r2.dts
> +++ b/arch/arm64/boot/dts/arm/juno-r2.dts
> @@ -181,3 +181,27 @@
> &pcie_ctlr {
> status = "okay";
> };
> +
> +&etm0 {
> + cpu = <&A72_0>;
> +};
> +
> +&etm1 {
> + cpu = <&A72_1>;
> +};
> +
> +&etm2 {
> + cpu = <&A53_0>;
> +};
> +
> +&etm3 {
> + cpu = <&A53_1>;
> +};
> +
> +&etm4 {
> + cpu = <&A53_2>;
> +};
> +
> +&etm5 {
> + cpu = <&A53_3>;
> +};
> diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
> index dcfcf15a17f5..a7270eff6939 100644
> --- a/arch/arm64/boot/dts/arm/juno.dts
> +++ b/arch/arm64/boot/dts/arm/juno.dts
> @@ -173,3 +173,27 @@
>
> #include "juno-base.dtsi"
> };
> +
> +&etm0 {
> + cpu = <&A57_0>;
> +};
> +
> +&etm1 {
> + cpu = <&A57_1>;
> +};
> +
> +&etm2 {
> + cpu = <&A53_0>;
> +};
> +
> +&etm3 {
> + cpu = <&A53_1>;
> +};
> +
> +&etm4 {
> + cpu = <&A53_2>;
> +};
> +
> +&etm5 {
> + cpu = <&A53_3>;
> +};
> --
> 2.7.4
>
--
====================
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
¯\_(ツ)_/¯
--
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/3] arm64: dts: juno: add arm,primecell-periphid override
[not found] ` <1465228765-14038-3-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
@ 2016-06-08 16:05 ` Liviu Dudau
2016-06-16 14:42 ` Sudeep Holla
1 sibling, 0 replies; 23+ messages in thread
From: Liviu Dudau @ 2016-06-08 16:05 UTC (permalink / raw)
To: Sudeep Holla
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Jon Medhurst,
Mathieu Poirier, Suzuki K Poulose, Lorenzo Pieralisi,
devicetree-u79uwXL29TY76Z2rM5mHXA
On Mon, Jun 06, 2016 at 04:59:24PM +0100, Sudeep Holla wrote:
> The Linux AMBA framework probes the peripheral ids when adding the amba
> devices very early on the boot. Generally they are on APB bus and just
> require APB clocks to be on even when most of the core logic of the IP
> is powered down.
>
> However on Juno, the entire debugsys domain needs to be ON to access
> those CID/PID registers and hence broken by design. Accessing those
> while debugsys power domain is off will lead to the bridge stalling the
> transactions instead of returning the slave error.
>
> Since keeping the power domain on by default affects the core power(by
> preventing cores entering deeper idle states), it's not feasible
> solution. Instead we can provide arm,primecell-periphid override in the
> device tree that prevents accessing the device early in the boot.
>
> However the power domains can be enabled whenever required using runtime
> PM and associated power domains.
>
> Cc: Liviu Dudau <liviu.dudau-5wv7dgnIgG8@public.gmane.org>
Acked-by: Liviu Dudau <Liviu.Dudau-5wv7dgnIgG8@public.gmane.org>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
> ---
> arch/arm64/boot/dts/arm/juno-base.dtsi | 13 +++++++++++++
> arch/arm64/boot/dts/arm/juno-r1.dts | 6 ++++++
> arch/arm64/boot/dts/arm/juno-r2.dts | 6 ++++++
> arch/arm64/boot/dts/arm/juno.dts | 6 ++++++
> 4 files changed, 31 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
> index 90a8710f7032..49fa55cdc977 100644
> --- a/arch/arm64/boot/dts/arm/juno-base.dtsi
> +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
> @@ -63,6 +63,14 @@
> */
> etf@20010000 {
> compatible = "arm,coresight-tmc", "arm,primecell";
> + /*
> + * The primecell peripheral id is explicitly specified here with
> + * the actual hardware value. It's not any override. It's
> + * required to workaround an errata to avoid bus stalls early
> + * in the boot when AMBA primecell ids are probed before the
> + * actual power domain can be enabled using SCPI.
> + */
> + arm,primecell-periphid = <0x001bb961>;
> reg = <0 0x20010000 0 0x1000>;
>
> clocks = <&soc_smc50mhz>;
> @@ -92,6 +100,7 @@
>
> tpiu@20030000 {
> compatible = "arm,coresight-tpiu", "arm,primecell";
> + arm,primecell-periphid = <0x004bb912>;
> reg = <0 0x20030000 0 0x1000>;
>
> clocks = <&soc_smc50mhz>;
> @@ -106,6 +115,7 @@
>
> main_funnel@20040000 {
> compatible = "arm,coresight-funnel", "arm,primecell";
> + arm,primecell-periphid = <0x002bb908>;
> reg = <0 0x20040000 0 0x1000>;
>
> clocks = <&soc_smc50mhz>;
> @@ -142,6 +152,7 @@
>
> etr@20070000 {
> compatible = "arm,coresight-tmc", "arm,primecell";
> + arm,primecell-periphid = <0x001bb961>;
> reg = <0 0x20070000 0 0x1000>;
>
> clocks = <&soc_smc50mhz>;
> @@ -192,6 +203,7 @@
>
> cluster0_funnel@220c0000 {
> compatible = "arm,coresight-funnel", "arm,primecell";
> + arm,primecell-periphid = <0x002bb908>;
> reg = <0 0x220c0000 0 0x1000>;
>
> clocks = <&soc_smc50mhz>;
> @@ -227,6 +239,7 @@
>
> cluster1_funnel@230c0000 {
> compatible = "arm,coresight-funnel", "arm,primecell";
> + arm,primecell-periphid = <0x002bb908>;
> reg = <0 0x230c0000 0 0x1000>;
>
> clocks = <&soc_smc50mhz>;
> diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
> index f4f8f54f8b85..c3c9fdff49bf 100644
> --- a/arch/arm64/boot/dts/arm/juno-r1.dts
> +++ b/arch/arm64/boot/dts/arm/juno-r1.dts
> @@ -184,24 +184,30 @@
>
> &etm0 {
> cpu = <&A57_0>;
> + arm,primecell-periphid = <0x002bb95e>;
> };
>
> &etm1 {
> cpu = <&A57_1>;
> + arm,primecell-periphid = <0x002bb95e>;
> };
>
> &etm2 {
> cpu = <&A53_0>;
> + arm,primecell-periphid = <0x003bb95d>;
> };
>
> &etm3 {
> cpu = <&A53_1>;
> + arm,primecell-periphid = <0x003bb95d>;
> };
>
> &etm4 {
> cpu = <&A53_2>;
> + arm,primecell-periphid = <0x003bb95d>;
> };
>
> &etm5 {
> cpu = <&A53_3>;
> + arm,primecell-periphid = <0x003bb95d>;
> };
> diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
> index d903e545b64c..c672c978f89d 100644
> --- a/arch/arm64/boot/dts/arm/juno-r2.dts
> +++ b/arch/arm64/boot/dts/arm/juno-r2.dts
> @@ -184,24 +184,30 @@
>
> &etm0 {
> cpu = <&A72_0>;
> + arm,primecell-periphid = <0x000bb95a>;
> };
>
> &etm1 {
> cpu = <&A72_1>;
> + arm,primecell-periphid = <0x000bb95a>;
> };
>
> &etm2 {
> cpu = <&A53_0>;
> + arm,primecell-periphid = <0x003bb95d>;
> };
>
> &etm3 {
> cpu = <&A53_1>;
> + arm,primecell-periphid = <0x003bb95d>;
> };
>
> &etm4 {
> cpu = <&A53_2>;
> + arm,primecell-periphid = <0x003bb95d>;
> };
>
> &etm5 {
> cpu = <&A53_3>;
> + arm,primecell-periphid = <0x003bb95d>;
> };
> diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
> index a7270eff6939..0528e47e66d1 100644
> --- a/arch/arm64/boot/dts/arm/juno.dts
> +++ b/arch/arm64/boot/dts/arm/juno.dts
> @@ -176,24 +176,30 @@
>
> &etm0 {
> cpu = <&A57_0>;
> + arm,primecell-periphid = <0x000bb95e>;
> };
>
> &etm1 {
> cpu = <&A57_1>;
> + arm,primecell-periphid = <0x000bb95e>;
> };
>
> &etm2 {
> cpu = <&A53_0>;
> + arm,primecell-periphid = <0x000bb95d>;
> };
>
> &etm3 {
> cpu = <&A53_1>;
> + arm,primecell-periphid = <0x000bb95d>;
> };
>
> &etm4 {
> cpu = <&A53_2>;
> + arm,primecell-periphid = <0x000bb95d>;
> };
>
> &etm5 {
> cpu = <&A53_3>;
> + arm,primecell-periphid = <0x000bb95d>;
> };
> --
> 2.7.4
>
--
====================
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
¯\_(ツ)_/¯
--
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/3] arm64: dts: juno: add SCPI power domains for device power management
[not found] ` <1465228765-14038-4-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
@ 2016-06-08 16:05 ` Liviu Dudau
2016-06-17 15:30 ` Mathieu Poirier
1 sibling, 0 replies; 23+ messages in thread
From: Liviu Dudau @ 2016-06-08 16:05 UTC (permalink / raw)
To: Sudeep Holla
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Jon Medhurst,
Mathieu Poirier, Suzuki K Poulose, Lorenzo Pieralisi,
devicetree-u79uwXL29TY76Z2rM5mHXA
On Mon, Jun 06, 2016 at 04:59:25PM +0100, Sudeep Holla wrote:
> This patch adds power domain information to coresight devices using
> SCPI power domains.
>
> Cc: Liviu Dudau <liviu.dudau-5wv7dgnIgG8@public.gmane.org>
Acked-by: Liviu Dudau <Liviu.Dudau-5wv7dgnIgG8@public.gmane.org>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
> ---
> arch/arm64/boot/dts/arm/juno-base.dtsi | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
> index 49fa55cdc977..ef054094d5a8 100644
> --- a/arch/arm64/boot/dts/arm/juno-base.dtsi
> +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
> @@ -75,6 +75,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -105,6 +106,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> port {
> tpiu_in_port: endpoint {
> slave-mode;
> @@ -120,6 +122,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -157,6 +160,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> port {
> etr_in_port: endpoint {
> slave-mode;
> @@ -208,6 +212,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -244,6 +249,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -293,6 +299,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> port {
> cluster0_etm0_out_port: endpoint {
> remote-endpoint = <&cluster0_funnel_in_port0>;
> @@ -306,6 +313,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> port {
> cluster0_etm1_out_port: endpoint {
> remote-endpoint = <&cluster0_funnel_in_port1>;
> @@ -319,6 +327,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> port {
> cluster1_etm0_out_port: endpoint {
> remote-endpoint = <&cluster1_funnel_in_port0>;
> @@ -332,6 +341,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> port {
> cluster1_etm1_out_port: endpoint {
> remote-endpoint = <&cluster1_funnel_in_port1>;
> @@ -345,6 +355,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> port {
> cluster1_etm2_out_port: endpoint {
> remote-endpoint = <&cluster1_funnel_in_port2>;
> @@ -358,6 +369,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> port {
> cluster1_etm3_out_port: endpoint {
> remote-endpoint = <&cluster1_funnel_in_port3>;
> @@ -428,6 +440,12 @@
> };
> };
>
> + scpi_devpd: scpi-power-domains {
> + compatible = "arm,scpi-power-domains";
> + num-domains = <2>;
> + #power-domain-cells = <1>;
> + };
> +
> scpi_sensors0: sensors {
> compatible = "arm,scpi-sensors";
> #thermal-sensor-cells = <1>;
> --
> 2.7.4
>
--
====================
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
¯\_(ツ)_/¯
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] arm64: dts: juno: add coresight support
[not found] ` <1465228765-14038-2-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
2016-06-08 16:04 ` Liviu Dudau
@ 2016-06-12 21:57 ` Mathieu Poirier
[not found] ` <CANLsYkzbtW2nFsntQ8vLafu=JS+qcjXm+6HQpi3F_P2a5CsHaw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-06-21 5:41 ` Olof Johansson
2 siblings, 1 reply; 23+ messages in thread
From: Mathieu Poirier @ 2016-06-12 21:57 UTC (permalink / raw)
To: Sudeep Holla
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Jon Medhurst,
Suzuki K Poulose, Liviu Dudau, Lorenzo Pieralisi,
devicetree-u79uwXL29TY76Z2rM5mHXA
On 6 June 2016 at 09:59, Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> wrote:
> Most of the debug-related components on Juno are located in the coreSight
> subsystem while others are located in the Cortex-Axx clusters, the SCP
> subsystem, and in the main system.
>
> Each core in the two processor clusters contain an Embedded Trace
> Macrocell(ETM) which generates real-time trace information that trace
> tools can use and an ATB trace output that is sent to a funnel before
> going to the CoreSight subsystem.
>
> The trace output signals combine with two trace expansions using another
> funnel and fed into the Embedded Trace FIFO(ETF0).
>
> The output trace data stream of the funnel is then replicated before it
> is sent to either the:
> - Trace Port Interface Unit(TPIU), that sends it out using the trace port.
> - ETR that can write the trace data to memory located in the application
> memory space
Hi Sudeep,
Did you try booting this on juno-r0? On my side the system won't boot
unless I enable the debug power domain by externally connecting to the
system using DS-5.
The branch I used is here [1].
Thanks,
Mathieu
[1]. https://git.linaro.org/kernel/coresight.git (branch next)
>
> Cc: Liviu Dudau <liviu.dudau-5wv7dgnIgG8@public.gmane.org>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
> ---
> arch/arm64/boot/dts/arm/juno-base.dtsi | 296 +++++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/arm/juno-r1.dts | 24 +++
> arch/arm64/boot/dts/arm/juno-r2.dts | 24 +++
> arch/arm64/boot/dts/arm/juno.dts | 24 +++
> 4 files changed, 368 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
> index dee2386d3b9b..90a8710f7032 100644
> --- a/arch/arm64/boot/dts/arm/juno-base.dtsi
> +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
> @@ -56,6 +56,302 @@
> <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
> };
>
> + /*
> + * Juno TRMs specify the size for these coresight components as 64K.
> + * The actual size is just 4K though 64K is reserved. Access to the
> + * unmapped reserved region results in a DECERR response.
> + */
> + etf@20010000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x20010000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* input port */
> + port@0 {
> + reg = <0>;
> + etf_in_port: endpoint {
> + slave-mode;
> + remote-endpoint = <&main_funnel_out_port>;
> + };
> + };
> +
> + /* output port */
> + port@1 {
> + reg = <0>;
> + etf_out_port: endpoint {
> + remote-endpoint = <&replicator_in_port0>;
> + };
> + };
> + };
> + };
> +
> + tpiu@20030000 {
> + compatible = "arm,coresight-tpiu", "arm,primecell";
> + reg = <0 0x20030000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + tpiu_in_port: endpoint {
> + slave-mode;
> + remote-endpoint = <&replicator_out_port0>;
> + };
> + };
> + };
> +
> + main_funnel@20040000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x20040000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + main_funnel_out_port: endpoint {
> + remote-endpoint = <&etf_in_port>;
> + };
> + };
> +
> + port@1 {
> + reg = <0>;
> + main_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster0_funnel_out_port>;
> + };
> + };
> +
> + port@2 {
> + reg = <1>;
> + main_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_funnel_out_port>;
> + };
> + };
> +
> + };
> + };
> +
> + etr@20070000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x20070000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + etr_in_port: endpoint {
> + slave-mode;
> + remote-endpoint = <&replicator_out_port1>;
> + };
> + };
> + };
> +
> + coresight-replicator {
> + /* non-configurable replicators don't show up on the
> + * AMBA bus. As such no need to add "arm,primecell".
> + */
> + compatible = "arm,coresight-replicator";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* replicator output ports */
> + port@0 {
> + reg = <0>;
> + replicator_out_port0: endpoint {
> + remote-endpoint = <&tpiu_in_port>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + replicator_out_port1: endpoint {
> + remote-endpoint = <&etr_in_port>;
> + };
> + };
> +
> + /* replicator input port */
> + port@2 {
> + reg = <0>;
> + replicator_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&etf_out_port>;
> + };
> + };
> + };
> + };
> +
> + cluster0_funnel@220c0000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x220c0000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + cluster0_funnel_out_port: endpoint {
> + remote-endpoint = <&main_funnel_in_port0>;
> + };
> + };
> +
> + port@1 {
> + reg = <0>;
> + cluster0_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster0_etm0_out_port>;
> + };
> + };
> +
> + port@2 {
> + reg = <1>;
> + cluster0_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster0_etm1_out_port>;
> + };
> + };
> + };
> + };
> +
> + cluster1_funnel@230c0000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x230c0000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + cluster1_funnel_out_port: endpoint {
> + remote-endpoint = <&main_funnel_in_port1>;
> + };
> + };
> +
> + port@1 {
> + reg = <0>;
> + cluster1_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_etm0_out_port>;
> + };
> + };
> +
> + port@2 {
> + reg = <1>;
> + cluster1_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_etm1_out_port>;
> + };
> + };
> + port@3 {
> + reg = <2>;
> + cluster1_funnel_in_port2: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_etm2_out_port>;
> + };
> + };
> + port@4 {
> + reg = <3>;
> + cluster1_funnel_in_port3: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_etm3_out_port>;
> + };
> + };
> + };
> + };
> +
> + etm0: etm@22040000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x22040000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster0_etm0_out_port: endpoint {
> + remote-endpoint = <&cluster0_funnel_in_port0>;
> + };
> + };
> + };
> +
> + etm1: etm@22140000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x22140000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster0_etm1_out_port: endpoint {
> + remote-endpoint = <&cluster0_funnel_in_port1>;
> + };
> + };
> + };
> +
> + etm2: etm@23040000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x23040000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster1_etm0_out_port: endpoint {
> + remote-endpoint = <&cluster1_funnel_in_port0>;
> + };
> + };
> + };
> +
> + etm3: etm@23140000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x23140000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster1_etm1_out_port: endpoint {
> + remote-endpoint = <&cluster1_funnel_in_port1>;
> + };
> + };
> + };
> +
> + etm4: etm@23240000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x23240000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster1_etm2_out_port: endpoint {
> + remote-endpoint = <&cluster1_funnel_in_port2>;
> + };
> + };
> + };
> +
> + etm5: etm@23340000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x23340000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster1_etm3_out_port: endpoint {
> + remote-endpoint = <&cluster1_funnel_in_port3>;
> + };
> + };
> + };
> +
> sram: sram@2e000000 {
> compatible = "arm,juno-sram-ns", "mmio-sram";
> reg = <0x0 0x2e000000 0x0 0x8000>;
> diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
> index d95d9e7e2dc0..f4f8f54f8b85 100644
> --- a/arch/arm64/boot/dts/arm/juno-r1.dts
> +++ b/arch/arm64/boot/dts/arm/juno-r1.dts
> @@ -181,3 +181,27 @@
> &pcie_ctlr {
> status = "okay";
> };
> +
> +&etm0 {
> + cpu = <&A57_0>;
> +};
> +
> +&etm1 {
> + cpu = <&A57_1>;
> +};
> +
> +&etm2 {
> + cpu = <&A53_0>;
> +};
> +
> +&etm3 {
> + cpu = <&A53_1>;
> +};
> +
> +&etm4 {
> + cpu = <&A53_2>;
> +};
> +
> +&etm5 {
> + cpu = <&A53_3>;
> +};
> diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
> index 88ecd6182b67..d903e545b64c 100644
> --- a/arch/arm64/boot/dts/arm/juno-r2.dts
> +++ b/arch/arm64/boot/dts/arm/juno-r2.dts
> @@ -181,3 +181,27 @@
> &pcie_ctlr {
> status = "okay";
> };
> +
> +&etm0 {
> + cpu = <&A72_0>;
> +};
> +
> +&etm1 {
> + cpu = <&A72_1>;
> +};
> +
> +&etm2 {
> + cpu = <&A53_0>;
> +};
> +
> +&etm3 {
> + cpu = <&A53_1>;
> +};
> +
> +&etm4 {
> + cpu = <&A53_2>;
> +};
> +
> +&etm5 {
> + cpu = <&A53_3>;
> +};
> diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
> index dcfcf15a17f5..a7270eff6939 100644
> --- a/arch/arm64/boot/dts/arm/juno.dts
> +++ b/arch/arm64/boot/dts/arm/juno.dts
> @@ -173,3 +173,27 @@
>
> #include "juno-base.dtsi"
> };
> +
> +&etm0 {
> + cpu = <&A57_0>;
> +};
> +
> +&etm1 {
> + cpu = <&A57_1>;
> +};
> +
> +&etm2 {
> + cpu = <&A53_0>;
> +};
> +
> +&etm3 {
> + cpu = <&A53_1>;
> +};
> +
> +&etm4 {
> + cpu = <&A53_2>;
> +};
> +
> +&etm5 {
> + cpu = <&A53_3>;
> +};
> --
> 2.7.4
>
--
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] arm64: dts: juno: add coresight support
[not found] ` <CANLsYkzbtW2nFsntQ8vLafu=JS+qcjXm+6HQpi3F_P2a5CsHaw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2016-06-13 3:05 ` Mathieu Poirier
2016-06-13 9:18 ` Sudeep Holla
1 sibling, 0 replies; 23+ messages in thread
From: Mathieu Poirier @ 2016-06-13 3:05 UTC (permalink / raw)
To: Sudeep Holla
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Jon Medhurst,
Suzuki K Poulose, Liviu Dudau, Lorenzo Pieralisi,
devicetree-u79uwXL29TY76Z2rM5mHXA
On 12 June 2016 at 15:57, Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> On 6 June 2016 at 09:59, Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> wrote:
>> Most of the debug-related components on Juno are located in the coreSight
>> subsystem while others are located in the Cortex-Axx clusters, the SCP
>> subsystem, and in the main system.
>>
>> Each core in the two processor clusters contain an Embedded Trace
>> Macrocell(ETM) which generates real-time trace information that trace
>> tools can use and an ATB trace output that is sent to a funnel before
>> going to the CoreSight subsystem.
>>
>> The trace output signals combine with two trace expansions using another
>> funnel and fed into the Embedded Trace FIFO(ETF0).
>>
>> The output trace data stream of the funnel is then replicated before it
>> is sent to either the:
>> - Trace Port Interface Unit(TPIU), that sends it out using the trace port.
>> - ETR that can write the trace data to memory located in the application
>> memory space
>
> Hi Sudeep,
>
> Did you try booting this on juno-r0?
Forget this comment - I just noticed the dependency on the SCPI
patches in the cover letter. I'll test again tomorrow.
> On my side the system won't boot
> unless I enable the debug power domain by externally connecting to the
> system using DS-5.
>
> The branch I used is here [1].
>
> Thanks,
> Mathieu
>
> [1]. https://git.linaro.org/kernel/coresight.git (branch next)
>
>
>>
>> Cc: Liviu Dudau <liviu.dudau-5wv7dgnIgG8@public.gmane.org>
>> Cc: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
>> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
>> ---
>> arch/arm64/boot/dts/arm/juno-base.dtsi | 296 +++++++++++++++++++++++++++++++++
>> arch/arm64/boot/dts/arm/juno-r1.dts | 24 +++
>> arch/arm64/boot/dts/arm/juno-r2.dts | 24 +++
>> arch/arm64/boot/dts/arm/juno.dts | 24 +++
>> 4 files changed, 368 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
>> index dee2386d3b9b..90a8710f7032 100644
>> --- a/arch/arm64/boot/dts/arm/juno-base.dtsi
>> +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
>> @@ -56,6 +56,302 @@
>> <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
>> };
>>
>> + /*
>> + * Juno TRMs specify the size for these coresight components as 64K.
>> + * The actual size is just 4K though 64K is reserved. Access to the
>> + * unmapped reserved region results in a DECERR response.
>> + */
>> + etf@20010000 {
>> + compatible = "arm,coresight-tmc", "arm,primecell";
>> + reg = <0 0x20010000 0 0x1000>;
>> +
>> + clocks = <&soc_smc50mhz>;
>> + clock-names = "apb_pclk";
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + /* input port */
>> + port@0 {
>> + reg = <0>;
>> + etf_in_port: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&main_funnel_out_port>;
>> + };
>> + };
>> +
>> + /* output port */
>> + port@1 {
>> + reg = <0>;
>> + etf_out_port: endpoint {
>> + remote-endpoint = <&replicator_in_port0>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + tpiu@20030000 {
>> + compatible = "arm,coresight-tpiu", "arm,primecell";
>> + reg = <0 0x20030000 0 0x1000>;
>> +
>> + clocks = <&soc_smc50mhz>;
>> + clock-names = "apb_pclk";
>> + port {
>> + tpiu_in_port: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&replicator_out_port0>;
>> + };
>> + };
>> + };
>> +
>> + main_funnel@20040000 {
>> + compatible = "arm,coresight-funnel", "arm,primecell";
>> + reg = <0 0x20040000 0 0x1000>;
>> +
>> + clocks = <&soc_smc50mhz>;
>> + clock-names = "apb_pclk";
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + main_funnel_out_port: endpoint {
>> + remote-endpoint = <&etf_in_port>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <0>;
>> + main_funnel_in_port0: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&cluster0_funnel_out_port>;
>> + };
>> + };
>> +
>> + port@2 {
>> + reg = <1>;
>> + main_funnel_in_port1: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&cluster1_funnel_out_port>;
>> + };
>> + };
>> +
>> + };
>> + };
>> +
>> + etr@20070000 {
>> + compatible = "arm,coresight-tmc", "arm,primecell";
>> + reg = <0 0x20070000 0 0x1000>;
>> +
>> + clocks = <&soc_smc50mhz>;
>> + clock-names = "apb_pclk";
>> + port {
>> + etr_in_port: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&replicator_out_port1>;
>> + };
>> + };
>> + };
>> +
>> + coresight-replicator {
>> + /* non-configurable replicators don't show up on the
>> + * AMBA bus. As such no need to add "arm,primecell".
>> + */
>> + compatible = "arm,coresight-replicator";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + /* replicator output ports */
>> + port@0 {
>> + reg = <0>;
>> + replicator_out_port0: endpoint {
>> + remote-endpoint = <&tpiu_in_port>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + replicator_out_port1: endpoint {
>> + remote-endpoint = <&etr_in_port>;
>> + };
>> + };
>> +
>> + /* replicator input port */
>> + port@2 {
>> + reg = <0>;
>> + replicator_in_port0: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&etf_out_port>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + cluster0_funnel@220c0000 {
>> + compatible = "arm,coresight-funnel", "arm,primecell";
>> + reg = <0 0x220c0000 0 0x1000>;
>> +
>> + clocks = <&soc_smc50mhz>;
>> + clock-names = "apb_pclk";
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + cluster0_funnel_out_port: endpoint {
>> + remote-endpoint = <&main_funnel_in_port0>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <0>;
>> + cluster0_funnel_in_port0: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&cluster0_etm0_out_port>;
>> + };
>> + };
>> +
>> + port@2 {
>> + reg = <1>;
>> + cluster0_funnel_in_port1: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&cluster0_etm1_out_port>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + cluster1_funnel@230c0000 {
>> + compatible = "arm,coresight-funnel", "arm,primecell";
>> + reg = <0 0x230c0000 0 0x1000>;
>> +
>> + clocks = <&soc_smc50mhz>;
>> + clock-names = "apb_pclk";
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + cluster1_funnel_out_port: endpoint {
>> + remote-endpoint = <&main_funnel_in_port1>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <0>;
>> + cluster1_funnel_in_port0: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&cluster1_etm0_out_port>;
>> + };
>> + };
>> +
>> + port@2 {
>> + reg = <1>;
>> + cluster1_funnel_in_port1: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&cluster1_etm1_out_port>;
>> + };
>> + };
>> + port@3 {
>> + reg = <2>;
>> + cluster1_funnel_in_port2: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&cluster1_etm2_out_port>;
>> + };
>> + };
>> + port@4 {
>> + reg = <3>;
>> + cluster1_funnel_in_port3: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&cluster1_etm3_out_port>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + etm0: etm@22040000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x22040000 0 0x1000>;
>> +
>> + clocks = <&soc_smc50mhz>;
>> + clock-names = "apb_pclk";
>> + port {
>> + cluster0_etm0_out_port: endpoint {
>> + remote-endpoint = <&cluster0_funnel_in_port0>;
>> + };
>> + };
>> + };
>> +
>> + etm1: etm@22140000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x22140000 0 0x1000>;
>> +
>> + clocks = <&soc_smc50mhz>;
>> + clock-names = "apb_pclk";
>> + port {
>> + cluster0_etm1_out_port: endpoint {
>> + remote-endpoint = <&cluster0_funnel_in_port1>;
>> + };
>> + };
>> + };
>> +
>> + etm2: etm@23040000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x23040000 0 0x1000>;
>> +
>> + clocks = <&soc_smc50mhz>;
>> + clock-names = "apb_pclk";
>> + port {
>> + cluster1_etm0_out_port: endpoint {
>> + remote-endpoint = <&cluster1_funnel_in_port0>;
>> + };
>> + };
>> + };
>> +
>> + etm3: etm@23140000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x23140000 0 0x1000>;
>> +
>> + clocks = <&soc_smc50mhz>;
>> + clock-names = "apb_pclk";
>> + port {
>> + cluster1_etm1_out_port: endpoint {
>> + remote-endpoint = <&cluster1_funnel_in_port1>;
>> + };
>> + };
>> + };
>> +
>> + etm4: etm@23240000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x23240000 0 0x1000>;
>> +
>> + clocks = <&soc_smc50mhz>;
>> + clock-names = "apb_pclk";
>> + port {
>> + cluster1_etm2_out_port: endpoint {
>> + remote-endpoint = <&cluster1_funnel_in_port2>;
>> + };
>> + };
>> + };
>> +
>> + etm5: etm@23340000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x23340000 0 0x1000>;
>> +
>> + clocks = <&soc_smc50mhz>;
>> + clock-names = "apb_pclk";
>> + port {
>> + cluster1_etm3_out_port: endpoint {
>> + remote-endpoint = <&cluster1_funnel_in_port3>;
>> + };
>> + };
>> + };
>> +
>> sram: sram@2e000000 {
>> compatible = "arm,juno-sram-ns", "mmio-sram";
>> reg = <0x0 0x2e000000 0x0 0x8000>;
>> diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
>> index d95d9e7e2dc0..f4f8f54f8b85 100644
>> --- a/arch/arm64/boot/dts/arm/juno-r1.dts
>> +++ b/arch/arm64/boot/dts/arm/juno-r1.dts
>> @@ -181,3 +181,27 @@
>> &pcie_ctlr {
>> status = "okay";
>> };
>> +
>> +&etm0 {
>> + cpu = <&A57_0>;
>> +};
>> +
>> +&etm1 {
>> + cpu = <&A57_1>;
>> +};
>> +
>> +&etm2 {
>> + cpu = <&A53_0>;
>> +};
>> +
>> +&etm3 {
>> + cpu = <&A53_1>;
>> +};
>> +
>> +&etm4 {
>> + cpu = <&A53_2>;
>> +};
>> +
>> +&etm5 {
>> + cpu = <&A53_3>;
>> +};
>> diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
>> index 88ecd6182b67..d903e545b64c 100644
>> --- a/arch/arm64/boot/dts/arm/juno-r2.dts
>> +++ b/arch/arm64/boot/dts/arm/juno-r2.dts
>> @@ -181,3 +181,27 @@
>> &pcie_ctlr {
>> status = "okay";
>> };
>> +
>> +&etm0 {
>> + cpu = <&A72_0>;
>> +};
>> +
>> +&etm1 {
>> + cpu = <&A72_1>;
>> +};
>> +
>> +&etm2 {
>> + cpu = <&A53_0>;
>> +};
>> +
>> +&etm3 {
>> + cpu = <&A53_1>;
>> +};
>> +
>> +&etm4 {
>> + cpu = <&A53_2>;
>> +};
>> +
>> +&etm5 {
>> + cpu = <&A53_3>;
>> +};
>> diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
>> index dcfcf15a17f5..a7270eff6939 100644
>> --- a/arch/arm64/boot/dts/arm/juno.dts
>> +++ b/arch/arm64/boot/dts/arm/juno.dts
>> @@ -173,3 +173,27 @@
>>
>> #include "juno-base.dtsi"
>> };
>> +
>> +&etm0 {
>> + cpu = <&A57_0>;
>> +};
>> +
>> +&etm1 {
>> + cpu = <&A57_1>;
>> +};
>> +
>> +&etm2 {
>> + cpu = <&A53_0>;
>> +};
>> +
>> +&etm3 {
>> + cpu = <&A53_1>;
>> +};
>> +
>> +&etm4 {
>> + cpu = <&A53_2>;
>> +};
>> +
>> +&etm5 {
>> + cpu = <&A53_3>;
>> +};
>> --
>> 2.7.4
>>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] arm64: dts: juno: add coresight support
[not found] ` <CANLsYkzbtW2nFsntQ8vLafu=JS+qcjXm+6HQpi3F_P2a5CsHaw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-06-13 3:05 ` Mathieu Poirier
@ 2016-06-13 9:18 ` Sudeep Holla
[not found] ` <575E7A56.6070005-5wv7dgnIgG8@public.gmane.org>
1 sibling, 1 reply; 23+ messages in thread
From: Sudeep Holla @ 2016-06-13 9:18 UTC (permalink / raw)
To: Mathieu Poirier
Cc: Sudeep Holla, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Jon Medhurst, Suzuki K Poulose, Liviu Dudau, Lorenzo Pieralisi,
devicetree-u79uwXL29TY76Z2rM5mHXA
On 12/06/16 22:57, Mathieu Poirier wrote:
> On 6 June 2016 at 09:59, Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> wrote:
>> Most of the debug-related components on Juno are located in the coreSight
>> subsystem while others are located in the Cortex-Axx clusters, the SCP
>> subsystem, and in the main system.
>>
>> Each core in the two processor clusters contain an Embedded Trace
>> Macrocell(ETM) which generates real-time trace information that trace
>> tools can use and an ATB trace output that is sent to a funnel before
>> going to the CoreSight subsystem.
>>
>> The trace output signals combine with two trace expansions using another
>> funnel and fed into the Embedded Trace FIFO(ETF0).
>>
>> The output trace data stream of the funnel is then replicated before it
>> is sent to either the:
>> - Trace Port Interface Unit(TPIU), that sends it out using the trace port.
>> - ETR that can write the trace data to memory located in the application
>> memory space
>
> Hi Sudeep,
>
> Did you try booting this on juno-r0? On my side the system won't boot
> unless I enable the debug power domain by externally connecting to the
> system using DS-5.
>
As you have already realized that you need SCPI power domain patches for
the functionality. However, in absence of those patches or when it's
disabled, it shouldn't cause any boot or runtime issues. Only ETM or
coresight won't work. If it's causing any crash or hang, please do let
me know, that needs to be fixed. I have only tested with latest
firmware. Let me know the details of hang/crash and firmware version you
are using.
--
Regards,
Sudeep
--
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] arm64: dts: juno: add coresight support
[not found] ` <575E7A56.6070005-5wv7dgnIgG8@public.gmane.org>
@ 2016-06-13 14:47 ` Mathieu Poirier
[not found] ` <CANLsYkzSOrypAZaDYAvvaFBB50ugkOpGFKCh-Sd=EyCE8bG0gg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 23+ messages in thread
From: Mathieu Poirier @ 2016-06-13 14:47 UTC (permalink / raw)
To: Sudeep Holla
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Jon Medhurst,
Suzuki K Poulose, Liviu Dudau, Lorenzo Pieralisi,
devicetree-u79uwXL29TY76Z2rM5mHXA
On 13 June 2016 at 03:18, Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> wrote:
>
>
> On 12/06/16 22:57, Mathieu Poirier wrote:
>>
>> On 6 June 2016 at 09:59, Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> wrote:
>>>
>>> Most of the debug-related components on Juno are located in the coreSight
>>> subsystem while others are located in the Cortex-Axx clusters, the SCP
>>> subsystem, and in the main system.
>>>
>>> Each core in the two processor clusters contain an Embedded Trace
>>> Macrocell(ETM) which generates real-time trace information that trace
>>> tools can use and an ATB trace output that is sent to a funnel before
>>> going to the CoreSight subsystem.
>>>
>>> The trace output signals combine with two trace expansions using another
>>> funnel and fed into the Embedded Trace FIFO(ETF0).
>>>
>>> The output trace data stream of the funnel is then replicated before it
>>> is sent to either the:
>>> - Trace Port Interface Unit(TPIU), that sends it out using the trace
>>> port.
>>> - ETR that can write the trace data to memory located in the application
>>> memory space
>>
>>
>> Hi Sudeep,
>>
>> Did you try booting this on juno-r0? On my side the system won't boot
>> unless I enable the debug power domain by externally connecting to the
>> system using DS-5.
>>
>
> As you have already realized that you need SCPI power domain patches for
> the functionality. However, in absence of those patches or when it's
> disabled, it shouldn't cause any boot or runtime issues. Only ETM or
> coresight won't work. If it's causing any crash or hang, please do let
> me know, that needs to be fixed. I have only tested with latest
> firmware. Let me know the details of hang/crash and firmware version you
> are using.
We have a problem then. Booting with this branch[1] and the 3 DT
patches from this set the system hangs. But before going any further
I'd bet the FW on my board is too old. This is what I get on my side:
RM V2M-Juno Boot loader v1.0.0
HBI0262 build 1684
ARM V2M_Juno Firmware v1.3.4
Build Date: Aug 27 2015
Time : 14:44:50
Date : 13:06:2016
Press Enter to stop auto boot...
What version are you using?
In the mean time I'm digging up your SCPI patches...
Thanks,
Mathieu
[1]. https://git.linaro.org/kernel/coresight.git/ (branch next)
>
> --
> Regards,
> Sudeep
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] arm64: dts: juno: add coresight support
[not found] ` <CANLsYkzSOrypAZaDYAvvaFBB50ugkOpGFKCh-Sd=EyCE8bG0gg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2016-06-13 14:53 ` Sudeep Holla
0 siblings, 0 replies; 23+ messages in thread
From: Sudeep Holla @ 2016-06-13 14:53 UTC (permalink / raw)
To: Mathieu Poirier
Cc: Sudeep Holla, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Jon Medhurst, Suzuki K Poulose, Liviu Dudau, Lorenzo Pieralisi,
devicetree-u79uwXL29TY76Z2rM5mHXA
On 13/06/16 15:47, Mathieu Poirier wrote:
> On 13 June 2016 at 03:18, Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> wrote:
>>
>>
>> On 12/06/16 22:57, Mathieu Poirier wrote:
>>>
>>> On 6 June 2016 at 09:59, Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> wrote:
>>>>
>>>> Most of the debug-related components on Juno are located in the coreSight
>>>> subsystem while others are located in the Cortex-Axx clusters, the SCP
>>>> subsystem, and in the main system.
>>>>
>>>> Each core in the two processor clusters contain an Embedded Trace
>>>> Macrocell(ETM) which generates real-time trace information that trace
>>>> tools can use and an ATB trace output that is sent to a funnel before
>>>> going to the CoreSight subsystem.
>>>>
>>>> The trace output signals combine with two trace expansions using another
>>>> funnel and fed into the Embedded Trace FIFO(ETF0).
>>>>
>>>> The output trace data stream of the funnel is then replicated before it
>>>> is sent to either the:
>>>> - Trace Port Interface Unit(TPIU), that sends it out using the trace
>>>> port.
>>>> - ETR that can write the trace data to memory located in the application
>>>> memory space
>>>
>>>
>>> Hi Sudeep,
>>>
>>> Did you try booting this on juno-r0? On my side the system won't boot
>>> unless I enable the debug power domain by externally connecting to the
>>> system using DS-5.
>>>
>>
>> As you have already realized that you need SCPI power domain patches for
>> the functionality. However, in absence of those patches or when it's
>> disabled, it shouldn't cause any boot or runtime issues. Only ETM or
>> coresight won't work. If it's causing any crash or hang, please do let
>> me know, that needs to be fixed. I have only tested with latest
>> firmware. Let me know the details of hang/crash and firmware version you
>> are using.
>
> We have a problem then. Booting with this branch[1] and the 3 DT
> patches from this set the system hangs. But before going any further
> I'd bet the FW on my board is too old. This is what I get on my side:
>
> RM V2M-Juno Boot loader v1.0.0
> HBI0262 build 1684
>
> ARM V2M_Juno Firmware v1.3.4
> Build Date: Aug 27 2015
>
Yes looks old *but* these are motherboard firmware, while I was
interested in SCP firmware. Anyways can you provide more details on the
hang (where/what/...)? Also the boot log(what ever you are getting out
if any)
--
Regards,
Sudeep
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/3] arm64: dts: juno: add arm,primecell-periphid override
[not found] ` <1465228765-14038-3-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
2016-06-08 16:05 ` Liviu Dudau
@ 2016-06-16 14:42 ` Sudeep Holla
1 sibling, 0 replies; 23+ messages in thread
From: Sudeep Holla @ 2016-06-16 14:42 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Sudeep Holla, Jon Medhurst, Mathieu Poirier, Suzuki K Poulose,
Liviu Dudau, Lorenzo Pieralisi,
devicetree-u79uwXL29TY76Z2rM5mHXA
On 06/06/16 16:59, Sudeep Holla wrote:
> The Linux AMBA framework probes the peripheral ids when adding the amba
> devices very early on the boot. Generally they are on APB bus and just
> require APB clocks to be on even when most of the core logic of the IP
> is powered down.
>
> However on Juno, the entire debugsys domain needs to be ON to access
> those CID/PID registers and hence broken by design. Accessing those
> while debugsys power domain is off will lead to the bridge stalling the
> transactions instead of returning the slave error.
>
> Since keeping the power domain on by default affects the core power(by
> preventing cores entering deeper idle states), it's not feasible
> solution. Instead we can provide arm,primecell-periphid override in the
> device tree that prevents accessing the device early in the boot.
>
OK, I recently found out that AMBA bus/infrastructure can deal with
powered off domains even while adding the devices. That makes this patch
redundant. I had missed it initially as I tested with !CONFIG_PM
option.
So I raised the issue with !CONFIG_PM option[1] and it was suggested to
make platform select the same[2] as there's no simple way to deal with
that.
Hence I will drop this patch but will post patch to select PM from
ARCH_VEXPRESS to ensure we always have it enabled to deal with this
platform issue.
--
Regards,
Sudeep
[1] http://marc.info/?l=linux-pm&m=146607608629880&w=2
[2] http://marc.info/?l=linux-pm&m=146608125731479&w=2
--
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] arm64: dts: juno: add coresight support
2016-06-06 15:59 ` [PATCH 1/3] arm64: dts: juno: add coresight support Sudeep Holla
@ 2016-06-17 15:29 ` Mathieu Poirier
[not found] ` <CANLsYkyWhknAb9QeGGjM2Et0+VUVjz7W2xyUJGstxfNc2bC20Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
[not found] ` <1465228765-14038-2-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
1 sibling, 1 reply; 23+ messages in thread
From: Mathieu Poirier @ 2016-06-17 15:29 UTC (permalink / raw)
To: Sudeep Holla
Cc: Jon Medhurst, devicetree, Lorenzo Pieralisi, Suzuki K Poulose,
Liviu Dudau, linux-arm-kernel
On 6 June 2016 at 09:59, Sudeep Holla <sudeep.holla@arm.com> wrote:
> Most of the debug-related components on Juno are located in the coreSight
> subsystem while others are located in the Cortex-Axx clusters, the SCP
> subsystem, and in the main system.
>
> Each core in the two processor clusters contain an Embedded Trace
> Macrocell(ETM) which generates real-time trace information that trace
> tools can use and an ATB trace output that is sent to a funnel before
> going to the CoreSight subsystem.
>
> The trace output signals combine with two trace expansions using another
> funnel and fed into the Embedded Trace FIFO(ETF0).
>
> The output trace data stream of the funnel is then replicated before it
> is sent to either the:
> - Trace Port Interface Unit(TPIU), that sends it out using the trace port.
> - ETR that can write the trace data to memory located in the application
> memory space
>
> Cc: Liviu Dudau <liviu.dudau@arm.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
> ---
> arch/arm64/boot/dts/arm/juno-base.dtsi | 296 +++++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/arm/juno-r1.dts | 24 +++
> arch/arm64/boot/dts/arm/juno-r2.dts | 24 +++
> arch/arm64/boot/dts/arm/juno.dts | 24 +++
> 4 files changed, 368 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
> index dee2386d3b9b..90a8710f7032 100644
> --- a/arch/arm64/boot/dts/arm/juno-base.dtsi
> +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
> @@ -56,6 +56,302 @@
> <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
> };
>
> + /*
> + * Juno TRMs specify the size for these coresight components as 64K.
> + * The actual size is just 4K though 64K is reserved. Access to the
> + * unmapped reserved region results in a DECERR response.
> + */
> + etf@20010000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x20010000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* input port */
> + port@0 {
> + reg = <0>;
> + etf_in_port: endpoint {
> + slave-mode;
> + remote-endpoint = <&main_funnel_out_port>;
> + };
> + };
> +
> + /* output port */
> + port@1 {
> + reg = <0>;
> + etf_out_port: endpoint {
> + remote-endpoint = <&replicator_in_port0>;
> + };
> + };
> + };
> + };
> +
> + tpiu@20030000 {
> + compatible = "arm,coresight-tpiu", "arm,primecell";
> + reg = <0 0x20030000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + tpiu_in_port: endpoint {
> + slave-mode;
> + remote-endpoint = <&replicator_out_port0>;
> + };
> + };
> + };
> +
> + main_funnel@20040000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x20040000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + main_funnel_out_port: endpoint {
> + remote-endpoint = <&etf_in_port>;
> + };
> + };
> +
> + port@1 {
> + reg = <0>;
> + main_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster0_funnel_out_port>;
> + };
> + };
> +
> + port@2 {
> + reg = <1>;
> + main_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_funnel_out_port>;
> + };
> + };
> +
> + };
> + };
> +
> + etr@20070000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x20070000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + etr_in_port: endpoint {
> + slave-mode;
> + remote-endpoint = <&replicator_out_port1>;
> + };
> + };
> + };
> +
> + coresight-replicator {
> + /* non-configurable replicators don't show up on the
> + * AMBA bus. As such no need to add "arm,primecell".
> + */
Please use kernel documentation style.
> + compatible = "arm,coresight-replicator";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* replicator output ports */
> + port@0 {
> + reg = <0>;
> + replicator_out_port0: endpoint {
> + remote-endpoint = <&tpiu_in_port>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + replicator_out_port1: endpoint {
> + remote-endpoint = <&etr_in_port>;
> + };
> + };
> +
> + /* replicator input port */
> + port@2 {
> + reg = <0>;
> + replicator_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&etf_out_port>;
> + };
> + };
> + };
> + };
> +
> + cluster0_funnel@220c0000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x220c0000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + cluster0_funnel_out_port: endpoint {
> + remote-endpoint = <&main_funnel_in_port0>;
> + };
> + };
> +
> + port@1 {
> + reg = <0>;
> + cluster0_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster0_etm0_out_port>;
> + };
> + };
> +
> + port@2 {
> + reg = <1>;
> + cluster0_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster0_etm1_out_port>;
> + };
> + };
> + };
> + };
> +
> + cluster1_funnel@230c0000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x230c0000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + cluster1_funnel_out_port: endpoint {
> + remote-endpoint = <&main_funnel_in_port1>;
> + };
> + };
> +
> + port@1 {
> + reg = <0>;
> + cluster1_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_etm0_out_port>;
> + };
> + };
> +
> + port@2 {
> + reg = <1>;
> + cluster1_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_etm1_out_port>;
> + };
> + };
> + port@3 {
> + reg = <2>;
> + cluster1_funnel_in_port2: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_etm2_out_port>;
> + };
> + };
> + port@4 {
> + reg = <3>;
> + cluster1_funnel_in_port3: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_etm3_out_port>;
> + };
> + };
> + };
> + };
> +
> + etm0: etm@22040000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x22040000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster0_etm0_out_port: endpoint {
> + remote-endpoint = <&cluster0_funnel_in_port0>;
> + };
> + };
> + };
> +
> + etm1: etm@22140000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x22140000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster0_etm1_out_port: endpoint {
> + remote-endpoint = <&cluster0_funnel_in_port1>;
> + };
> + };
> + };
> +
> + etm2: etm@23040000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x23040000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster1_etm0_out_port: endpoint {
> + remote-endpoint = <&cluster1_funnel_in_port0>;
> + };
> + };
> + };
> +
> + etm3: etm@23140000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x23140000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster1_etm1_out_port: endpoint {
> + remote-endpoint = <&cluster1_funnel_in_port1>;
> + };
> + };
> + };
> +
> + etm4: etm@23240000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x23240000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster1_etm2_out_port: endpoint {
> + remote-endpoint = <&cluster1_funnel_in_port2>;
> + };
> + };
> + };
> +
> + etm5: etm@23340000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x23340000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster1_etm3_out_port: endpoint {
> + remote-endpoint = <&cluster1_funnel_in_port3>;
> + };
> + };
> + };
> +
> sram: sram@2e000000 {
> compatible = "arm,juno-sram-ns", "mmio-sram";
> reg = <0x0 0x2e000000 0x0 0x8000>;
> diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
> index d95d9e7e2dc0..f4f8f54f8b85 100644
> --- a/arch/arm64/boot/dts/arm/juno-r1.dts
> +++ b/arch/arm64/boot/dts/arm/juno-r1.dts
> @@ -181,3 +181,27 @@
> &pcie_ctlr {
> status = "okay";
> };
> +
> +&etm0 {
> + cpu = <&A57_0>;
> +};
> +
> +&etm1 {
> + cpu = <&A57_1>;
> +};
> +
> +&etm2 {
> + cpu = <&A53_0>;
> +};
> +
> +&etm3 {
> + cpu = <&A53_1>;
> +};
> +
> +&etm4 {
> + cpu = <&A53_2>;
> +};
> +
> +&etm5 {
> + cpu = <&A53_3>;
> +};
> diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
> index 88ecd6182b67..d903e545b64c 100644
> --- a/arch/arm64/boot/dts/arm/juno-r2.dts
> +++ b/arch/arm64/boot/dts/arm/juno-r2.dts
> @@ -181,3 +181,27 @@
> &pcie_ctlr {
> status = "okay";
> };
> +
> +&etm0 {
> + cpu = <&A72_0>;
> +};
> +
> +&etm1 {
> + cpu = <&A72_1>;
> +};
> +
> +&etm2 {
> + cpu = <&A53_0>;
> +};
> +
> +&etm3 {
> + cpu = <&A53_1>;
> +};
> +
> +&etm4 {
> + cpu = <&A53_2>;
> +};
> +
> +&etm5 {
> + cpu = <&A53_3>;
> +};
> diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
> index dcfcf15a17f5..a7270eff6939 100644
> --- a/arch/arm64/boot/dts/arm/juno.dts
> +++ b/arch/arm64/boot/dts/arm/juno.dts
> @@ -173,3 +173,27 @@
>
> #include "juno-base.dtsi"
> };
> +
> +&etm0 {
> + cpu = <&A57_0>;
> +};
> +
> +&etm1 {
> + cpu = <&A57_1>;
> +};
> +
> +&etm2 {
> + cpu = <&A53_0>;
> +};
> +
> +&etm3 {
> + cpu = <&A53_1>;
> +};
> +
> +&etm4 {
> + cpu = <&A53_2>;
> +};
> +
> +&etm5 {
> + cpu = <&A53_3>;
> +};
> --
> 2.7.4
>
With the above change:
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/3] arm64: dts: juno: add SCPI power domains for device power management
[not found] ` <1465228765-14038-4-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
2016-06-08 16:05 ` Liviu Dudau
@ 2016-06-17 15:30 ` Mathieu Poirier
1 sibling, 0 replies; 23+ messages in thread
From: Mathieu Poirier @ 2016-06-17 15:30 UTC (permalink / raw)
To: Sudeep Holla
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Jon Medhurst,
Suzuki K Poulose, Liviu Dudau, Lorenzo Pieralisi,
devicetree-u79uwXL29TY76Z2rM5mHXA
On 6 June 2016 at 09:59, Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> wrote:
> This patch adds power domain information to coresight devices using
> SCPI power domains.
>
> Cc: Liviu Dudau <liviu.dudau-5wv7dgnIgG8@public.gmane.org>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
> ---
> arch/arm64/boot/dts/arm/juno-base.dtsi | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
> index 49fa55cdc977..ef054094d5a8 100644
> --- a/arch/arm64/boot/dts/arm/juno-base.dtsi
> +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
> @@ -75,6 +75,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -105,6 +106,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> port {
> tpiu_in_port: endpoint {
> slave-mode;
> @@ -120,6 +122,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -157,6 +160,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> port {
> etr_in_port: endpoint {
> slave-mode;
> @@ -208,6 +212,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -244,6 +249,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -293,6 +299,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> port {
> cluster0_etm0_out_port: endpoint {
> remote-endpoint = <&cluster0_funnel_in_port0>;
> @@ -306,6 +313,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> port {
> cluster0_etm1_out_port: endpoint {
> remote-endpoint = <&cluster0_funnel_in_port1>;
> @@ -319,6 +327,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> port {
> cluster1_etm0_out_port: endpoint {
> remote-endpoint = <&cluster1_funnel_in_port0>;
> @@ -332,6 +341,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> port {
> cluster1_etm1_out_port: endpoint {
> remote-endpoint = <&cluster1_funnel_in_port1>;
> @@ -345,6 +355,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> port {
> cluster1_etm2_out_port: endpoint {
> remote-endpoint = <&cluster1_funnel_in_port2>;
> @@ -358,6 +369,7 @@
>
> clocks = <&soc_smc50mhz>;
> clock-names = "apb_pclk";
> + power-domains = <&scpi_devpd 0>;
> port {
> cluster1_etm3_out_port: endpoint {
> remote-endpoint = <&cluster1_funnel_in_port3>;
> @@ -428,6 +440,12 @@
> };
> };
>
> + scpi_devpd: scpi-power-domains {
> + compatible = "arm,scpi-power-domains";
> + num-domains = <2>;
> + #power-domain-cells = <1>;
> + };
> +
> scpi_sensors0: sensors {
> compatible = "arm,scpi-sensors";
> #thermal-sensor-cells = <1>;
> --
> 2.7.4
>
Acked-by: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] arm64: dts: juno: add coresight support
[not found] ` <CANLsYkyWhknAb9QeGGjM2Et0+VUVjz7W2xyUJGstxfNc2bC20Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2016-06-17 15:33 ` Sudeep Holla
0 siblings, 0 replies; 23+ messages in thread
From: Sudeep Holla @ 2016-06-17 15:33 UTC (permalink / raw)
To: Mathieu Poirier
Cc: Sudeep Holla, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Jon Medhurst, Suzuki K Poulose, Liviu Dudau, Lorenzo Pieralisi,
devicetree-u79uwXL29TY76Z2rM5mHXA
On 17/06/16 16:29, Mathieu Poirier wrote:
> On 6 June 2016 at 09:59, Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> wrote:
>> Most of the debug-related components on Juno are located in the coreSight
>> subsystem while others are located in the Cortex-Axx clusters, the SCP
>> subsystem, and in the main system.
>>
>> Each core in the two processor clusters contain an Embedded Trace
>> Macrocell(ETM) which generates real-time trace information that trace
>> tools can use and an ATB trace output that is sent to a funnel before
>> going to the CoreSight subsystem.
>>
>> The trace output signals combine with two trace expansions using another
>> funnel and fed into the Embedded Trace FIFO(ETF0).
>>
>> The output trace data stream of the funnel is then replicated before it
>> is sent to either the:
>> - Trace Port Interface Unit(TPIU), that sends it out using the trace port.
>> - ETR that can write the trace data to memory located in the application
>> memory space
>>
>> Cc: Liviu Dudau <liviu.dudau-5wv7dgnIgG8@public.gmane.org>
>> Cc: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
>> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
>> ---
>> arch/arm64/boot/dts/arm/juno-base.dtsi | 296 +++++++++++++++++++++++++++++++++
>> arch/arm64/boot/dts/arm/juno-r1.dts | 24 +++
>> arch/arm64/boot/dts/arm/juno-r2.dts | 24 +++
>> arch/arm64/boot/dts/arm/juno.dts | 24 +++
>> 4 files changed, 368 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
>> index dee2386d3b9b..90a8710f7032 100644
>> --- a/arch/arm64/boot/dts/arm/juno-base.dtsi
>> +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
[...]
>> +
>> + coresight-replicator {
>> + /* non-configurable replicators don't show up on the
>> + * AMBA bus. As such no need to add "arm,primecell".
>> + */
>
> Please use kernel documentation style.
>
Ah, that's copy paste from arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts ;)
[...]
>>
>
> With the above change:
>
> Acked-by: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>
Thanks.
--
Regards,
Sudeep
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] arm64: dts: juno: add coresight support
[not found] ` <1465228765-14038-2-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
2016-06-08 16:04 ` Liviu Dudau
2016-06-12 21:57 ` Mathieu Poirier
@ 2016-06-21 5:41 ` Olof Johansson
2016-06-21 8:44 ` Suzuki K Poulose
[not found] ` <CAOesGMjQNEOcmYpUAxUxBJLyUYZQuRKK48a31Ys9LuTJFWqMFA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2 siblings, 2 replies; 23+ messages in thread
From: Olof Johansson @ 2016-06-21 5:41 UTC (permalink / raw)
To: Sudeep Holla
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Jon Medhurst,
Mathieu Poirier, Suzuki K Poulose, Liviu Dudau,
Lorenzo Pieralisi, devicetree-u79uwXL29TY76Z2rM5mHXA
Hi,
Some nits below.
On Mon, Jun 6, 2016 at 8:59 AM, Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> wrote:
> Most of the debug-related components on Juno are located in the coreSight
> subsystem while others are located in the Cortex-Axx clusters, the SCP
> subsystem, and in the main system.
>
> Each core in the two processor clusters contain an Embedded Trace
> Macrocell(ETM) which generates real-time trace information that trace
> tools can use and an ATB trace output that is sent to a funnel before
> going to the CoreSight subsystem.
>
> The trace output signals combine with two trace expansions using another
> funnel and fed into the Embedded Trace FIFO(ETF0).
>
> The output trace data stream of the funnel is then replicated before it
> is sent to either the:
> - Trace Port Interface Unit(TPIU), that sends it out using the trace port.
> - ETR that can write the trace data to memory located in the application
> memory space
>
> Cc: Liviu Dudau <liviu.dudau-5wv7dgnIgG8@public.gmane.org>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
> ---
> arch/arm64/boot/dts/arm/juno-base.dtsi | 296 +++++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/arm/juno-r1.dts | 24 +++
> arch/arm64/boot/dts/arm/juno-r2.dts | 24 +++
> arch/arm64/boot/dts/arm/juno.dts | 24 +++
> 4 files changed, 368 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
> index dee2386d3b9b..90a8710f7032 100644
> --- a/arch/arm64/boot/dts/arm/juno-base.dtsi
> +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
> @@ -56,6 +56,302 @@
> <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
> };
>
> + /*
> + * Juno TRMs specify the size for these coresight components as 64K.
> + * The actual size is just 4K though 64K is reserved. Access to the
> + * unmapped reserved region results in a DECERR response.
> + */
> + etf@20010000 {
Would it make sense to name it something like trace-fifo instead? We
normally name the nodes based on type of device (ethernet@, pci@,
etc).
> + compatible = "arm,coresight-tmc", "arm,primecell";
Is there a more specific compatible needed here, or does
arm,coresight-tmc give you all the information you need on how to use
this interface?
The bindings doc is sort of sparse in this area, all it says is "you
might use one of these compatibles".
> + tpiu@20030000 {
Again, these names are not great. Luckily they don't affect the
binding, so they can be fixed. What would be a more human readable and
functionally describing name here?
> + compatible = "arm,coresight-tpiu", "arm,primecell";
> + reg = <0 0x20030000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + tpiu_in_port: endpoint {
> + slave-mode;
> + remote-endpoint = <&replicator_out_port0>;
> + };
> + };
> + };
> +
> + main_funnel@20040000 {
Underscores are usually frowned upon. funnel@ or ideally a better more
descriptive name should be used here.
Use dashes if you really have to.
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x20040000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + main_funnel_out_port: endpoint {
> + remote-endpoint = <&etf_in_port>;
> + };
> + };
> +
> + port@1 {
> + reg = <0>;
> + main_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster0_funnel_out_port>;
> + };
> + };
> +
> + port@2 {
> + reg = <1>;
> + main_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_funnel_out_port>;
> + };
> + };
> +
> + };
> + };
> +
> + etr@20070000 {
Again..
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x20070000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + etr_in_port: endpoint {
> + slave-mode;
> + remote-endpoint = <&replicator_out_port1>;
> + };
> + };
> + };
> +
> + coresight-replicator {
Hm. It'd sort of be nice to stick all the coresight stuff under one
node instead of having them all at the toplevel, but that doesn't
really go with the concept of having each device where it's at in the
bus/address hierarchy.
Should _all_ the nodes be at the toplevel though? Looks like you have
a few address ranges that most of the toplevel devices are at, is
there really not a physical bus they're each connected to that you can
describe?
> + /* non-configurable replicators don't show up on the
> + * AMBA bus. As such no need to add "arm,primecell".
> + */
> + compatible = "arm,coresight-replicator";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* replicator output ports */
> + port@0 {
> + reg = <0>;
> + replicator_out_port0: endpoint {
> + remote-endpoint = <&tpiu_in_port>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + replicator_out_port1: endpoint {
> + remote-endpoint = <&etr_in_port>;
> + };
> + };
> +
> + /* replicator input port */
> + port@2 {
> + reg = <0>;
> + replicator_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&etf_out_port>;
> + };
> + };
> + };
> + };
> +
> + cluster0_funnel@220c0000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x220c0000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + cluster0_funnel_out_port: endpoint {
> + remote-endpoint = <&main_funnel_in_port0>;
> + };
> + };
> +
> + port@1 {
> + reg = <0>;
> + cluster0_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster0_etm0_out_port>;
> + };
> + };
> +
> + port@2 {
> + reg = <1>;
> + cluster0_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster0_etm1_out_port>;
> + };
> + };
> + };
> + };
> +
> + cluster1_funnel@230c0000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x230c0000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + cluster1_funnel_out_port: endpoint {
> + remote-endpoint = <&main_funnel_in_port1>;
> + };
> + };
> +
> + port@1 {
> + reg = <0>;
> + cluster1_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_etm0_out_port>;
> + };
> + };
> +
> + port@2 {
> + reg = <1>;
> + cluster1_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_etm1_out_port>;
> + };
> + };
> + port@3 {
> + reg = <2>;
> + cluster1_funnel_in_port2: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_etm2_out_port>;
> + };
> + };
> + port@4 {
> + reg = <3>;
> + cluster1_funnel_in_port3: endpoint {
> + slave-mode;
> + remote-endpoint = <&cluster1_etm3_out_port>;
> + };
> + };
> + };
> + };
> +
> + etm0: etm@22040000 {
If this file is sorted on reg values, then this node and the two after
are out of order.
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x22040000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster0_etm0_out_port: endpoint {
> + remote-endpoint = <&cluster0_funnel_in_port0>;
> + };
> + };
> + };
> +
> + etm1: etm@22140000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x22140000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster0_etm1_out_port: endpoint {
> + remote-endpoint = <&cluster0_funnel_in_port1>;
> + };
> + };
> + };
> +
> + etm2: etm@23040000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x23040000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster1_etm0_out_port: endpoint {
> + remote-endpoint = <&cluster1_funnel_in_port0>;
> + };
> + };
> + };
> +
> + etm3: etm@23140000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x23140000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster1_etm1_out_port: endpoint {
> + remote-endpoint = <&cluster1_funnel_in_port1>;
> + };
> + };
> + };
> +
> + etm4: etm@23240000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x23240000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster1_etm2_out_port: endpoint {
> + remote-endpoint = <&cluster1_funnel_in_port2>;
> + };
> + };
> + };
> +
> + etm5: etm@23340000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x23340000 0 0x1000>;
> +
> + clocks = <&soc_smc50mhz>;
> + clock-names = "apb_pclk";
> + port {
> + cluster1_etm3_out_port: endpoint {
> + remote-endpoint = <&cluster1_funnel_in_port3>;
> + };
> + };
> + };
> +
> sram: sram@2e000000 {
> compatible = "arm,juno-sram-ns", "mmio-sram";
> reg = <0x0 0x2e000000 0x0 0x8000>;
> diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
> index d95d9e7e2dc0..f4f8f54f8b85 100644
> --- a/arch/arm64/boot/dts/arm/juno-r1.dts
> +++ b/arch/arm64/boot/dts/arm/juno-r1.dts
> @@ -181,3 +181,27 @@
> &pcie_ctlr {
> status = "okay";
> };
> +
> +&etm0 {
> + cpu = <&A57_0>;
> +};
> +
> +&etm1 {
> + cpu = <&A57_1>;
> +};
> +
> +&etm2 {
> + cpu = <&A53_0>;
> +};
> +
> +&etm3 {
> + cpu = <&A53_1>;
> +};
> +
> +&etm4 {
> + cpu = <&A53_2>;
> +};
> +
> +&etm5 {
> + cpu = <&A53_3>;
> +};
> diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
> index 88ecd6182b67..d903e545b64c 100644
> --- a/arch/arm64/boot/dts/arm/juno-r2.dts
> +++ b/arch/arm64/boot/dts/arm/juno-r2.dts
> @@ -181,3 +181,27 @@
> &pcie_ctlr {
> status = "okay";
> };
> +
> +&etm0 {
> + cpu = <&A72_0>;
> +};
> +
> +&etm1 {
> + cpu = <&A72_1>;
> +};
> +
> +&etm2 {
> + cpu = <&A53_0>;
> +};
> +
> +&etm3 {
> + cpu = <&A53_1>;
> +};
> +
> +&etm4 {
> + cpu = <&A53_2>;
> +};
> +
> +&etm5 {
> + cpu = <&A53_3>;
> +};
> diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
> index dcfcf15a17f5..a7270eff6939 100644
> --- a/arch/arm64/boot/dts/arm/juno.dts
> +++ b/arch/arm64/boot/dts/arm/juno.dts
> @@ -173,3 +173,27 @@
>
> #include "juno-base.dtsi"
> };
> +
> +&etm0 {
> + cpu = <&A57_0>;
> +};
> +
> +&etm1 {
> + cpu = <&A57_1>;
> +};
> +
> +&etm2 {
> + cpu = <&A53_0>;
> +};
> +
> +&etm3 {
> + cpu = <&A53_1>;
> +};
> +
> +&etm4 {
> + cpu = <&A53_2>;
> +};
> +
> +&etm5 {
> + cpu = <&A53_3>;
> +};
> --
> 2.7.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] arm64: dts: juno: add coresight support
2016-06-21 5:41 ` Olof Johansson
@ 2016-06-21 8:44 ` Suzuki K Poulose
[not found] ` <CAOesGMjQNEOcmYpUAxUxBJLyUYZQuRKK48a31Ys9LuTJFWqMFA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
1 sibling, 0 replies; 23+ messages in thread
From: Suzuki K Poulose @ 2016-06-21 8:44 UTC (permalink / raw)
To: Olof Johansson, Sudeep Holla
Cc: Jon Medhurst, devicetree, Lorenzo Pieralisi, Mathieu Poirier,
Liviu Dudau, linux-arm-kernel
On 21/06/16 06:41, Olof Johansson wrote:
Hi Olof,
>> + /*
>> + * Juno TRMs specify the size for these coresight components as 64K.
>> + * The actual size is just 4K though 64K is reserved. Access to the
>> + * unmapped reserved region results in a DECERR response.
>> + */
>> + etf@20010000 {
>
> Would it make sense to name it something like trace-fifo instead? We
> normally name the nodes based on type of device (ethernet@, pci@,
> etc).
ETF (Embedded Trace FIFO) is one of the modes[1] in which you can configure
the Coresight TMC at integration time. The other available modes are
ETR(Embedded Trace Router) and ETB(Embedded Trace Buffer).
>
>
>> + compatible = "arm,coresight-tmc", "arm,primecell";
>
> Is there a more specific compatible needed here, or does
> arm,coresight-tmc give you all the information you need on how to use
> this interface?
The coresight TMC driver will read the "configured mode" to determine
the mode of operation and initialise it accordingly. Hence we don't
need a specific compatible.
>
> The bindings doc is sort of sparse in this area, all it says is "you
> might use one of these compatibles".
I agree.
>
>> + tpiu@20030000 {
>
> Again, these names are not great. Luckily they don't affect the
> binding, so they can be fixed. What would be a more human readable and
> functionally describing name here?
Again, TPIU (Trace Port Interface Unit), is standard Coresight component in
Coresight architecture. [2]
>> +
>> + etr@20070000 {
>
> Again..
>
Same as ETF [1]
>> +
>> + etm0: etm@22040000 {
>
> If this file is sorted on reg values, then this node and the two after
> are out of order.
They are numbered after the CPU which they are associated with. This is used
to reuse the dts for Juno-r0/r1 vs r2 (where we have A72 replacing A57).
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0461b/CACECIII.html
[2] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0314h/Babhdhfb.html
Cheers
Suzuki
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] arm64: dts: juno: add coresight support
[not found] ` <CAOesGMjQNEOcmYpUAxUxBJLyUYZQuRKK48a31Ys9LuTJFWqMFA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2016-06-21 11:27 ` Sudeep Holla
[not found] ` <57692488.2030507-5wv7dgnIgG8@public.gmane.org>
0 siblings, 1 reply; 23+ messages in thread
From: Sudeep Holla @ 2016-06-21 11:27 UTC (permalink / raw)
To: Olof Johansson
Cc: Sudeep Holla, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Jon Medhurst, Mathieu Poirier, Suzuki K Poulose, Liviu Dudau,
Lorenzo Pieralisi, devicetree-u79uwXL29TY76Z2rM5mHXA
On 21/06/16 06:41, Olof Johansson wrote:
> Hi,
>
> Some nits below.
>
My bad, I blindly copy-pasted it from vexpress TC2 platform.
> On Mon, Jun 6, 2016 at 8:59 AM, Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> wrote:
>> Most of the debug-related components on Juno are located in the coreSight
>> subsystem while others are located in the Cortex-Axx clusters, the SCP
>> subsystem, and in the main system.
>>
>> Each core in the two processor clusters contain an Embedded Trace
>> Macrocell(ETM) which generates real-time trace information that trace
>> tools can use and an ATB trace output that is sent to a funnel before
>> going to the CoreSight subsystem.
>>
>> The trace output signals combine with two trace expansions using another
>> funnel and fed into the Embedded Trace FIFO(ETF0).
>>
>> The output trace data stream of the funnel is then replicated before it
>> is sent to either the:
>> - Trace Port Interface Unit(TPIU), that sends it out using the trace port.
>> - ETR that can write the trace data to memory located in the application
>> memory space
>>
>> Cc: Liviu Dudau <liviu.dudau-5wv7dgnIgG8@public.gmane.org>
>> Cc: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
>> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
>> ---
>> arch/arm64/boot/dts/arm/juno-base.dtsi | 296 +++++++++++++++++++++++++++++++++
>> arch/arm64/boot/dts/arm/juno-r1.dts | 24 +++
>> arch/arm64/boot/dts/arm/juno-r2.dts | 24 +++
>> arch/arm64/boot/dts/arm/juno.dts | 24 +++
>> 4 files changed, 368 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
>> index dee2386d3b9b..90a8710f7032 100644
>> --- a/arch/arm64/boot/dts/arm/juno-base.dtsi
>> +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
>> @@ -56,6 +56,302 @@
>> <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
>> };
>>
>> + /*
>> + * Juno TRMs specify the size for these coresight components as 64K.
>> + * The actual size is just 4K though 64K is reserved. Access to the
>> + * unmapped reserved region results in a DECERR response.
>> + */
>> + etf@20010000 {
>
> Would it make sense to name it something like trace-fifo instead? We
> normally name the nodes based on type of device (ethernet@, pci@,
> etc).
>
As Suzuki already pointed out, these are standard acronyms used in
various CoreSight specifications. Let me know if you need them to be
expanded instead of abbreviations.
>
>> + compatible = "arm,coresight-tmc", "arm,primecell";
>
> Is there a more specific compatible needed here, or does
> arm,coresight-tmc give you all the information you need on how to use
> this interface?
>
> The bindings doc is sort of sparse in this area, all it says is "you
> might use one of these compatibles".
>
Again Suzuki commented on that. I will leave it to Mathieu who is the
author of the binding to comment further(if any).
But I agree, it would be good to have one line description on each of
them as they are pretty much standard primecells or even URL to their
specifications.
>> + tpiu@20030000 {
>
> Again, these names are not great. Luckily they don't affect the
> binding, so they can be fixed. What would be a more human readable and
> functionally describing name here?
>
>> + compatible = "arm,coresight-tpiu", "arm,primecell";
>> + reg = <0 0x20030000 0 0x1000>;
>> +
>> + clocks = <&soc_smc50mhz>;
>> + clock-names = "apb_pclk";
>> + port {
>> + tpiu_in_port: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&replicator_out_port0>;
>> + };
>> + };
>> + };
>> +
>> + main_funnel@20040000 {
>
> Underscores are usually frowned upon. funnel@ or ideally a better more
> descriptive name should be used here.
> Use dashes if you really have to.
>
Agreed and fixed locally now.
[...]
>> + compatible = "arm,coresight-tmc", "arm,primecell";
>> + reg = <0 0x20070000 0 0x1000>;
>> +
>> + clocks = <&soc_smc50mhz>;
>> + clock-names = "apb_pclk";
>> + port {
>> + etr_in_port: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&replicator_out_port1>;
>> + };
>> + };
>> + };
>> +
>> + coresight-replicator {
>
> Hm. It'd sort of be nice to stick all the coresight stuff under one
> node instead of having them all at the toplevel, but that doesn't
> really go with the concept of having each device where it's at in the
> bus/address hierarchy.
>
I understand.
> Should _all_ the nodes be at the toplevel though? Looks like you have
> a few address ranges that most of the toplevel devices are at, is
> there really not a physical bus they're each connected to that you can
> describe?
>
I need to look at the Juno documents again and refine. It may affect
other devices too. Can that be addressed later separately ?
[...]
>> +
>> + etm0: etm@22040000 {
>
> If this file is sorted on reg values, then this node and the two after
> are out of order.
>
Yes that was the intent, will fix it. But I see some oddities, may be
will fix those once I address the address/bus hierarchy.
--
--
Regards,
Sudeep
--
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] arm64: dts: juno: add coresight support
[not found] ` <57692488.2030507-5wv7dgnIgG8@public.gmane.org>
@ 2016-06-21 16:30 ` Mathieu Poirier
2016-06-28 17:03 ` Sudeep Holla
1 sibling, 0 replies; 23+ messages in thread
From: Mathieu Poirier @ 2016-06-21 16:30 UTC (permalink / raw)
To: Sudeep Holla
Cc: Olof Johansson,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Jon Medhurst,
Suzuki K Poulose, Liviu Dudau, Lorenzo Pieralisi,
devicetree-u79uwXL29TY76Z2rM5mHXA
On 21 June 2016 at 05:27, Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> wrote:
>
>
> On 21/06/16 06:41, Olof Johansson wrote:
>>
>> Hi,
>>
>> Some nits below.
>>
>
> My bad, I blindly copy-pasted it from vexpress TC2 platform.
>
>> On Mon, Jun 6, 2016 at 8:59 AM, Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> wrote:
>>>
>>> Most of the debug-related components on Juno are located in the coreSight
>>> subsystem while others are located in the Cortex-Axx clusters, the SCP
>>> subsystem, and in the main system.
>>>
>>> Each core in the two processor clusters contain an Embedded Trace
>>> Macrocell(ETM) which generates real-time trace information that trace
>>> tools can use and an ATB trace output that is sent to a funnel before
>>> going to the CoreSight subsystem.
>>>
>>> The trace output signals combine with two trace expansions using another
>>> funnel and fed into the Embedded Trace FIFO(ETF0).
>>>
>>> The output trace data stream of the funnel is then replicated before it
>>> is sent to either the:
>>> - Trace Port Interface Unit(TPIU), that sends it out using the trace
>>> port.
>>> - ETR that can write the trace data to memory located in the application
>>> memory space
>>>
>>> Cc: Liviu Dudau <liviu.dudau-5wv7dgnIgG8@public.gmane.org>
>>> Cc: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
>>> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>>> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>>> Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
>>> ---
>>> arch/arm64/boot/dts/arm/juno-base.dtsi | 296
>>> +++++++++++++++++++++++++++++++++
>>> arch/arm64/boot/dts/arm/juno-r1.dts | 24 +++
>>> arch/arm64/boot/dts/arm/juno-r2.dts | 24 +++
>>> arch/arm64/boot/dts/arm/juno.dts | 24 +++
>>> 4 files changed, 368 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi
>>> b/arch/arm64/boot/dts/arm/juno-base.dtsi
>>> index dee2386d3b9b..90a8710f7032 100644
>>> --- a/arch/arm64/boot/dts/arm/juno-base.dtsi
>>> +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
>>> @@ -56,6 +56,302 @@
>>> <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
>>> IRQ_TYPE_LEVEL_LOW)>;
>>> };
>>>
>>> + /*
>>> + * Juno TRMs specify the size for these coresight components as
>>> 64K.
>>> + * The actual size is just 4K though 64K is reserved. Access to
>>> the
>>> + * unmapped reserved region results in a DECERR response.
>>> + */
>>> + etf@20010000 {
>>
>>
>> Would it make sense to name it something like trace-fifo instead? We
>> normally name the nodes based on type of device (ethernet@, pci@,
>> etc).
>>
>
> As Suzuki already pointed out, these are standard acronyms used in
> various CoreSight specifications. Let me know if you need them to be
> expanded instead of abbreviations.
>
>>
>>> + compatible = "arm,coresight-tmc", "arm,primecell";
>>
>>
>> Is there a more specific compatible needed here, or does
>> arm,coresight-tmc give you all the information you need on how to use
>> this interface?
>>
>> The bindings doc is sort of sparse in this area, all it says is "you
>> might use one of these compatibles".
>>
>
> Again Suzuki commented on that. I will leave it to Mathieu who is the
> author of the binding to comment further(if any).
>
> But I agree, it would be good to have one line description on each of
> them as they are pretty much standard primecells or even URL to their
> specifications.
I initially wrote the bindings from a developer's point of view, or
someone implementing CoreSight on their system. As such there would
be no doubts about the acronyms found in the bindings as the same
nomenclature is used throughout the documentation.
But from an onlooker's perspective I can see how they can be
confusing. As Sudeep suggested I will add a short description for
each binding.
>
>>> + tpiu@20030000 {
>>
>>
>> Again, these names are not great. Luckily they don't affect the
>> binding, so they can be fixed. What would be a more human readable and
>> functionally describing name here?
>>
>>> + compatible = "arm,coresight-tpiu", "arm,primecell";
>>> + reg = <0 0x20030000 0 0x1000>;
>>> +
>>> + clocks = <&soc_smc50mhz>;
>>> + clock-names = "apb_pclk";
>>> + port {
>>> + tpiu_in_port: endpoint {
>>> + slave-mode;
>>> + remote-endpoint =
>>> <&replicator_out_port0>;
>>> + };
>>> + };
>>> + };
>>> +
>>> + main_funnel@20040000 {
>>
>>
>> Underscores are usually frowned upon. funnel@ or ideally a better more
>> descriptive name should be used here.
>> Use dashes if you really have to.
>>
>
> Agreed and fixed locally now.
>
> [...]
>
>>> + compatible = "arm,coresight-tmc", "arm,primecell";
>>> + reg = <0 0x20070000 0 0x1000>;
>>> +
>>> + clocks = <&soc_smc50mhz>;
>>> + clock-names = "apb_pclk";
>>> + port {
>>> + etr_in_port: endpoint {
>>> + slave-mode;
>>> + remote-endpoint =
>>> <&replicator_out_port1>;
>>> + };
>>> + };
>>> + };
>>> +
>>> + coresight-replicator {
>>
>>
>> Hm. It'd sort of be nice to stick all the coresight stuff under one
>> node instead of having them all at the toplevel, but that doesn't
>> really go with the concept of having each device where it's at in the
>> bus/address hierarchy.
I thought long and hard about this when initially working on the
bindings. All CoreSight blocks are independent from one another and
they don't need a bus to be accessed or configured.
>>
>
> I understand.
>
>> Should _all_ the nodes be at the toplevel though? Looks like you have
>> a few address ranges that most of the toplevel devices are at, is
>> there really not a physical bus they're each connected to that you can
>> describe?
>>
>
> I need to look at the Juno documents again and refine. It may affect
> other devices too. Can that be addressed later separately ?
>
> [...]
>
>
>>> +
>>> + etm0: etm@22040000 {
>>
>>
>> If this file is sorted on reg values, then this node and the two after
>> are out of order.
>>
>
> Yes that was the intent, will fix it. But I see some oddities, may be
> will fix those once I address the address/bus hierarchy.
>
> --
> --
> Regards,
> Sudeep
--
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/3] arm64: dts: juno: add coresight support
[not found] ` <57692488.2030507-5wv7dgnIgG8@public.gmane.org>
2016-06-21 16:30 ` Mathieu Poirier
@ 2016-06-28 17:03 ` Sudeep Holla
1 sibling, 0 replies; 23+ messages in thread
From: Sudeep Holla @ 2016-06-28 17:03 UTC (permalink / raw)
To: Olof Johansson
Cc: Sudeep Holla, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Jon Medhurst, Mathieu Poirier, Suzuki K Poulose, Liviu Dudau,
Lorenzo Pieralisi, devicetree-u79uwXL29TY76Z2rM5mHXA
Hi Olof,
On 21/06/16 12:27, Sudeep Holla wrote:
>
>
> On 21/06/16 06:41, Olof Johansson wrote:
>> Hi,
>>
>> Some nits below.
>>
>
> My bad, I blindly copy-pasted it from vexpress TC2 platform.
>
Any further comments on the replies so far ?
--
Regards,
Sudeep
--
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^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 0/2] arm64: dts: juno: add coresight support
[not found] ` <1465228765-14038-1-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
` (2 preceding siblings ...)
2016-06-06 15:59 ` [PATCH 3/3] arm64: dts: juno: add SCPI power domains for device power management Sudeep Holla
@ 2016-07-06 10:15 ` Sudeep Holla
[not found] ` <1467800137-17533-1-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
3 siblings, 1 reply; 23+ messages in thread
From: Sudeep Holla @ 2016-07-06 10:15 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Sudeep Holla, Jon Medhurst, Mathieu Poirier, Liviu Dudau,
Lorenzo Pieralisi, Olof Johansson
This series adds support for coresight debug subsystem based on similar
support on Vexpress TC2 platform by Mathieu Poirier. It also contains
a workaround required to prevent bus stall quite early in the boot.
It uses power domain provided by SCPI, so it depends on scpi patches[1].
Regards,
Sudeep
v1[0]->v2:
- Dropped arm,primecell-periphid override addition
- Sorted the nodes based on reg fields and replaced underscores
with dashes as suggested by Olof
- Retained coresight acronyms aas Matheiu added definations to
the binding[1]
[0] http://www.spinics.net/lists/arm-kernel/msg508733.html
[1] https://patchwork.kernel.org/patch/9193133/
Sudeep Holla (2):
arm64: dts: juno: add coresight support
arm64: dts: juno: add SCPI power domains for device power management
arch/arm64/boot/dts/arm/juno-base.dtsi | 315 +++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/arm/juno-r1.dts | 24 +++
arch/arm64/boot/dts/arm/juno-r2.dts | 24 +++
arch/arm64/boot/dts/arm/juno.dts | 24 +++
4 files changed, 387 insertions(+)
--
2.7.4
--
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^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 1/2] arm64: dts: juno: add coresight support
[not found] ` <1467800137-17533-1-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
@ 2016-07-06 10:15 ` Sudeep Holla
2016-07-06 10:15 ` [PATCH v2 2/2] arm64: dts: juno: add SCPI power domains for device power management Sudeep Holla
1 sibling, 0 replies; 23+ messages in thread
From: Sudeep Holla @ 2016-07-06 10:15 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Sudeep Holla, Jon Medhurst, Mathieu Poirier, Liviu Dudau,
Lorenzo Pieralisi, Olof Johansson
Most of the debug-related components on Juno are located in the coreSight
subsystem while others are located in the Cortex-Axx clusters, the SCP
subsystem, and in the main system.
Each core in the two processor clusters contain an Embedded Trace
Macrocell(ETM) which generates real-time trace information that trace
tools can use and an ATB trace output that is sent to a funnel before
going to the CoreSight subsystem.
The trace output signals combine with two trace expansions using another
funnel and fed into the Embedded Trace FIFO(ETF0).
The output trace data stream of the funnel is then replicated before it
is sent to either the:
- Trace Port Interface Unit(TPIU), that sends it out using the trace port.
- ETR that can write the trace data to memory located in the application
memory space
Cc: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
Acked-by: Liviu Dudau <liviu.dudau-5wv7dgnIgG8@public.gmane.org>
Acked-by: Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 297 +++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/arm/juno-r1.dts | 24 +++
arch/arm64/boot/dts/arm/juno-r2.dts | 24 +++
arch/arm64/boot/dts/arm/juno.dts | 24 +++
4 files changed, 369 insertions(+)
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index dee2386d3b9b..4ea40a476906 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -56,6 +56,303 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
};
+ /*
+ * Juno TRMs specify the size for these coresight components as 64K.
+ * The actual size is just 4K though 64K is reserved. Access to the
+ * unmapped reserved region results in a DECERR response.
+ */
+ etf@20010000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x20010000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* input port */
+ port@0 {
+ reg = <0>;
+ etf_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&main_funnel_out_port>;
+ };
+ };
+
+ /* output port */
+ port@1 {
+ reg = <0>;
+ etf_out_port: endpoint {
+ remote-endpoint = <&replicator_in_port0>;
+ };
+ };
+ };
+ };
+
+ tpiu@20030000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0 0x20030000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ port {
+ tpiu_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&replicator_out_port0>;
+ };
+ };
+ };
+
+ main-funnel@20040000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x20040000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ main_funnel_out_port: endpoint {
+ remote-endpoint = <&etf_in_port>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ main_funnel_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&cluster0_funnel_out_port>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ main_funnel_in_port1: endpoint {
+ slave-mode;
+ remote-endpoint = <&cluster1_funnel_out_port>;
+ };
+ };
+
+ };
+ };
+
+ etr@20070000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x20070000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ port {
+ etr_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&replicator_out_port1>;
+ };
+ };
+ };
+
+ etm0: etm@22040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x22040000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ port {
+ cluster0_etm0_out_port: endpoint {
+ remote-endpoint = <&cluster0_funnel_in_port0>;
+ };
+ };
+ };
+
+ cluster0-funnel@220c0000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x220c0000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ cluster0_funnel_out_port: endpoint {
+ remote-endpoint = <&main_funnel_in_port0>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ cluster0_funnel_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&cluster0_etm0_out_port>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ cluster0_funnel_in_port1: endpoint {
+ slave-mode;
+ remote-endpoint = <&cluster0_etm1_out_port>;
+ };
+ };
+ };
+ };
+
+ etm1: etm@22140000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x22140000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ port {
+ cluster0_etm1_out_port: endpoint {
+ remote-endpoint = <&cluster0_funnel_in_port1>;
+ };
+ };
+ };
+
+ etm2: etm@23040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x23040000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ port {
+ cluster1_etm0_out_port: endpoint {
+ remote-endpoint = <&cluster1_funnel_in_port0>;
+ };
+ };
+ };
+
+ cluster1-funnel@230c0000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x230c0000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ cluster1_funnel_out_port: endpoint {
+ remote-endpoint = <&main_funnel_in_port1>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ cluster1_funnel_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&cluster1_etm0_out_port>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ cluster1_funnel_in_port1: endpoint {
+ slave-mode;
+ remote-endpoint = <&cluster1_etm1_out_port>;
+ };
+ };
+ port@3 {
+ reg = <2>;
+ cluster1_funnel_in_port2: endpoint {
+ slave-mode;
+ remote-endpoint = <&cluster1_etm2_out_port>;
+ };
+ };
+ port@4 {
+ reg = <3>;
+ cluster1_funnel_in_port3: endpoint {
+ slave-mode;
+ remote-endpoint = <&cluster1_etm3_out_port>;
+ };
+ };
+ };
+ };
+
+ etm3: etm@23140000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x23140000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ port {
+ cluster1_etm1_out_port: endpoint {
+ remote-endpoint = <&cluster1_funnel_in_port1>;
+ };
+ };
+ };
+
+ etm4: etm@23240000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x23240000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ port {
+ cluster1_etm2_out_port: endpoint {
+ remote-endpoint = <&cluster1_funnel_in_port2>;
+ };
+ };
+ };
+
+ etm5: etm@23340000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x23340000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ port {
+ cluster1_etm3_out_port: endpoint {
+ remote-endpoint = <&cluster1_funnel_in_port3>;
+ };
+ };
+ };
+
+ coresight-replicator {
+ /*
+ * Non-configurable replicators don't show up on the
+ * AMBA bus. As such no need to add "arm,primecell".
+ */
+ compatible = "arm,coresight-replicator";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* replicator output ports */
+ port@0 {
+ reg = <0>;
+ replicator_out_port0: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ replicator_out_port1: endpoint {
+ remote-endpoint = <&etr_in_port>;
+ };
+ };
+
+ /* replicator input port */
+ port@2 {
+ reg = <0>;
+ replicator_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&etf_out_port>;
+ };
+ };
+ };
+ };
+
sram: sram@2e000000 {
compatible = "arm,juno-sram-ns", "mmio-sram";
reg = <0x0 0x2e000000 0x0 0x8000>;
diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
index d95d9e7e2dc0..f4f8f54f8b85 100644
--- a/arch/arm64/boot/dts/arm/juno-r1.dts
+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
@@ -181,3 +181,27 @@
&pcie_ctlr {
status = "okay";
};
+
+&etm0 {
+ cpu = <&A57_0>;
+};
+
+&etm1 {
+ cpu = <&A57_1>;
+};
+
+&etm2 {
+ cpu = <&A53_0>;
+};
+
+&etm3 {
+ cpu = <&A53_1>;
+};
+
+&etm4 {
+ cpu = <&A53_2>;
+};
+
+&etm5 {
+ cpu = <&A53_3>;
+};
diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
index 88ecd6182b67..d903e545b64c 100644
--- a/arch/arm64/boot/dts/arm/juno-r2.dts
+++ b/arch/arm64/boot/dts/arm/juno-r2.dts
@@ -181,3 +181,27 @@
&pcie_ctlr {
status = "okay";
};
+
+&etm0 {
+ cpu = <&A72_0>;
+};
+
+&etm1 {
+ cpu = <&A72_1>;
+};
+
+&etm2 {
+ cpu = <&A53_0>;
+};
+
+&etm3 {
+ cpu = <&A53_1>;
+};
+
+&etm4 {
+ cpu = <&A53_2>;
+};
+
+&etm5 {
+ cpu = <&A53_3>;
+};
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index dcfcf15a17f5..a7270eff6939 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -173,3 +173,27 @@
#include "juno-base.dtsi"
};
+
+&etm0 {
+ cpu = <&A57_0>;
+};
+
+&etm1 {
+ cpu = <&A57_1>;
+};
+
+&etm2 {
+ cpu = <&A53_0>;
+};
+
+&etm3 {
+ cpu = <&A53_1>;
+};
+
+&etm4 {
+ cpu = <&A53_2>;
+};
+
+&etm5 {
+ cpu = <&A53_3>;
+};
--
2.7.4
--
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^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 2/2] arm64: dts: juno: add SCPI power domains for device power management
[not found] ` <1467800137-17533-1-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
2016-07-06 10:15 ` [PATCH v2 1/2] " Sudeep Holla
@ 2016-07-06 10:15 ` Sudeep Holla
1 sibling, 0 replies; 23+ messages in thread
From: Sudeep Holla @ 2016-07-06 10:15 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Sudeep Holla, Jon Medhurst, Mathieu Poirier, Liviu Dudau,
Lorenzo Pieralisi, Olof Johansson
This patch adds power domain information to coresight devices using
SCPI power domains.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
Acked-by: Liviu Dudau <liviu.dudau-5wv7dgnIgG8@public.gmane.org>
Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 4ea40a476906..53820fa79bab 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -67,6 +67,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -96,6 +97,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
port {
tpiu_in_port: endpoint {
slave-mode;
@@ -110,6 +112,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -146,6 +149,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
port {
etr_in_port: endpoint {
slave-mode;
@@ -160,6 +164,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
port {
cluster0_etm0_out_port: endpoint {
remote-endpoint = <&cluster0_funnel_in_port0>;
@@ -173,6 +178,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -208,6 +214,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
port {
cluster0_etm1_out_port: endpoint {
remote-endpoint = <&cluster0_funnel_in_port1>;
@@ -221,6 +228,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
port {
cluster1_etm0_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port0>;
@@ -234,6 +242,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -283,6 +292,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
port {
cluster1_etm1_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port1>;
@@ -296,6 +306,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
port {
cluster1_etm2_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port2>;
@@ -309,6 +320,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
port {
cluster1_etm3_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port3>;
@@ -416,6 +428,12 @@
};
};
+ scpi_devpd: scpi-power-domains {
+ compatible = "arm,scpi-power-domains";
+ num-domains = <2>;
+ #power-domain-cells = <1>;
+ };
+
scpi_sensors0: sensors {
compatible = "arm,scpi-sensors";
#thermal-sensor-cells = <1>;
--
2.7.4
--
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^ permalink raw reply related [flat|nested] 23+ messages in thread
end of thread, other threads:[~2016-07-06 10:15 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <1465228765-14038-1-git-send-email-sudeep.holla@arm.com>
[not found] ` <1465228765-14038-1-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
2016-06-06 15:59 ` [PATCH 1/3] arm64: dts: juno: add coresight support Sudeep Holla
2016-06-17 15:29 ` Mathieu Poirier
[not found] ` <CANLsYkyWhknAb9QeGGjM2Et0+VUVjz7W2xyUJGstxfNc2bC20Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-06-17 15:33 ` Sudeep Holla
[not found] ` <1465228765-14038-2-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
2016-06-08 16:04 ` Liviu Dudau
2016-06-12 21:57 ` Mathieu Poirier
[not found] ` <CANLsYkzbtW2nFsntQ8vLafu=JS+qcjXm+6HQpi3F_P2a5CsHaw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-06-13 3:05 ` Mathieu Poirier
2016-06-13 9:18 ` Sudeep Holla
[not found] ` <575E7A56.6070005-5wv7dgnIgG8@public.gmane.org>
2016-06-13 14:47 ` Mathieu Poirier
[not found] ` <CANLsYkzSOrypAZaDYAvvaFBB50ugkOpGFKCh-Sd=EyCE8bG0gg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-06-13 14:53 ` Sudeep Holla
2016-06-21 5:41 ` Olof Johansson
2016-06-21 8:44 ` Suzuki K Poulose
[not found] ` <CAOesGMjQNEOcmYpUAxUxBJLyUYZQuRKK48a31Ys9LuTJFWqMFA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-06-21 11:27 ` Sudeep Holla
[not found] ` <57692488.2030507-5wv7dgnIgG8@public.gmane.org>
2016-06-21 16:30 ` Mathieu Poirier
2016-06-28 17:03 ` Sudeep Holla
2016-06-06 15:59 ` [PATCH 2/3] arm64: dts: juno: add arm,primecell-periphid override Sudeep Holla
[not found] ` <1465228765-14038-3-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
2016-06-08 16:05 ` Liviu Dudau
2016-06-16 14:42 ` Sudeep Holla
2016-06-06 15:59 ` [PATCH 3/3] arm64: dts: juno: add SCPI power domains for device power management Sudeep Holla
[not found] ` <1465228765-14038-4-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
2016-06-08 16:05 ` Liviu Dudau
2016-06-17 15:30 ` Mathieu Poirier
2016-07-06 10:15 ` [PATCH v2 0/2] arm64: dts: juno: add coresight support Sudeep Holla
[not found] ` <1467800137-17533-1-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
2016-07-06 10:15 ` [PATCH v2 1/2] " Sudeep Holla
2016-07-06 10:15 ` [PATCH v2 2/2] arm64: dts: juno: add SCPI power domains for device power management Sudeep Holla
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